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STG4000InitDevice.c
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1 /*
2  * linux/drivers/video/kyro/STG4000InitDevice.c
3  *
4  * Copyright (C) 2000 Imagination Technologies Ltd
5  * Copyright (C) 2002 STMicroelectronics
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License. See the file COPYING in the main directory of this archive
9  * for more details.
10  */
11 
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/types.h>
15 #include <linux/pci.h>
16 
17 #include "STG4000Reg.h"
18 #include "STG4000Interface.h"
19 
20 /* SDRAM fixed settings */
21 #define SDRAM_CFG_0 0x49A1
22 #define SDRAM_CFG_1 0xA732
23 #define SDRAM_CFG_2 0x31
24 #define SDRAM_ARB_CFG 0xA0
25 #define SDRAM_REFRESH 0x20
26 
27 /* Reset values */
28 #define PMX2_SOFTRESET_DAC_RST 0x0001
29 #define PMX2_SOFTRESET_C1_RST 0x0004
30 #define PMX2_SOFTRESET_C2_RST 0x0008
31 #define PMX2_SOFTRESET_3D_RST 0x0010
32 #define PMX2_SOFTRESET_VIDIN_RST 0x0020
33 #define PMX2_SOFTRESET_TLB_RST 0x0040
34 #define PMX2_SOFTRESET_SD_RST 0x0080
35 #define PMX2_SOFTRESET_VGA_RST 0x0100
36 #define PMX2_SOFTRESET_ROM_RST 0x0200 /* reserved bit, do not reset */
37 #define PMX2_SOFTRESET_TA_RST 0x0400
38 #define PMX2_SOFTRESET_REG_RST 0x4000
39 #define PMX2_SOFTRESET_ALL 0x7fff
40 
41 /* Core clock freq */
42 #define CORE_PLL_FREQ 1000000
43 
44 /* Reference Clock freq */
45 #define REF_FREQ 14318
46 
47 /* PCI Registers */
48 static u16 CorePllControl = 0x70;
49 
50 #define PCI_CONFIG_SUBSYS_ID 0x2e
51 
52 /* Misc */
53 #define CORE_PLL_MODE_REG_0_7 3
54 #define CORE_PLL_MODE_REG_8_15 2
55 #define CORE_PLL_MODE_CONFIG_REG 1
56 #define DAC_PLL_CONFIG_REG 0
57 
58 #define STG_MAX_VCO 500000
59 #define STG_MIN_VCO 100000
60 
61 /* PLL Clock */
62 #define STG4K3_PLL_SCALER 8 /* scale numbers by 2^8 for fixed point calc */
63 #define STG4K3_PLL_MIN_R 2 /* Minimum multiplier */
64 #define STG4K3_PLL_MAX_R 33 /* Max */
65 #define STG4K3_PLL_MIN_F 2 /* Minimum divisor */
66 #define STG4K3_PLL_MAX_F 513 /* Max */
67 #define STG4K3_PLL_MIN_OD 0 /* Min output divider (shift) */
68 #define STG4K3_PLL_MAX_OD 2 /* Max */
69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
76 
77 #define OS_DELAY(X) \
78 { \
79 volatile u32 i,count=0; \
80  for(i=0;i<X;i++) count++; \
81 }
82 
83 static u32 InitSDRAMRegisters(volatile STG4000REG __iomem *pSTGReg,
84  u32 dwSubSysID, u32 dwRevID)
85 {
86  u32 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 };
87  u32 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 };
88  u32 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 };
89  u32 adwSDRAMRsh[] = { 36, 39, 40 };
90  u32 adwChipSpeed[] = { 110, 120, 125 };
91  u32 dwMemTypeIdx;
92  u32 dwChipSpeedIdx;
93 
94  /* Get memory tpye and chip speed indexs from the SubSysDevID */
95  dwMemTypeIdx = (dwSubSysID & 0x70) >> 4;
96  dwChipSpeedIdx = (dwSubSysID & 0x180) >> 7;
97 
98  if (dwMemTypeIdx > 4 || dwChipSpeedIdx > 2)
99  return 0;
100 
101  /* Program SD-RAM interface */
102  STG_WRITE_REG(SDRAMArbiterConf, adwSDRAMArgCfg0[dwMemTypeIdx]);
103  if (dwRevID < 5) {
104  STG_WRITE_REG(SDRAMConf0, 0x49A1);
105  STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg1[dwMemTypeIdx]);
106  } else {
107  STG_WRITE_REG(SDRAMConf0, 0x4DF1);
108  STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg2[dwMemTypeIdx]);
109  }
110 
111  STG_WRITE_REG(SDRAMConf2, 0x31);
112  STG_WRITE_REG(SDRAMRefresh, adwSDRAMRsh[dwChipSpeedIdx]);
113 
114  return adwChipSpeed[dwChipSpeedIdx] * 10000;
115 }
116 
117 u32 ProgramClock(u32 refClock,
118  u32 coreClock,
119  u32 * FOut, u32 * ROut, u32 * POut)
120 {
121  u32 R = 0, F = 0, OD = 0, ODIndex = 0;
122  u32 ulBestR = 0, ulBestF = 0, ulBestOD = 0;
123  u32 ulBestVCO = 0, ulBestClk = 0, ulBestScore = 0;
124  u32 ulScore, ulPhaseScore, ulVcoScore;
125  u32 ulTmp = 0, ulVCO;
126  u32 ulScaleClockReq, ulMinClock, ulMaxClock;
127  u32 ODValues[] = { 1, 2, 0 };
128 
129  /* Translate clock in Hz */
130  coreClock *= 100; /* in Hz */
131  refClock *= 1000; /* in Hz */
132 
133  /* Work out acceptable clock
134  * The method calculates ~ +- 0.4% (1/256)
135  */
136  ulMinClock = coreClock - (coreClock >> 8);
137  ulMaxClock = coreClock + (coreClock >> 8);
138 
139  /* Scale clock required for use in calculations */
140  ulScaleClockReq = coreClock >> STG4K3_PLL_SCALER;
141 
142  /* Iterate through post divider values */
143  for (ODIndex = 0; ODIndex < 3; ODIndex++) {
144  OD = ODValues[ODIndex];
145  R = STG4K3_PLL_MIN_R;
146 
147  /* loop for pre-divider from min to max */
148  while (R <= STG4K3_PLL_MAX_R) {
149  /* estimate required feedback multiplier */
150  ulTmp = R * (ulScaleClockReq << OD);
151 
152  /* F = ClkRequired * R * (2^OD) / Fref */
153  F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER));
154 
155  /* compensate for accuracy */
156  if (F > STG4K3_PLL_MIN_F)
157  F--;
158 
159 
160  /*
161  * We should be close to our target frequency (if it's
162  * achievable with current OD & R) let's iterate
163  * through F for best fit
164  */
165  while ((F >= STG4K3_PLL_MIN_F) &&
166  (F <= STG4K3_PLL_MAX_F)) {
167  /* Calc VCO at full accuracy */
168  ulVCO = refClock / R;
169  ulVCO = F * ulVCO;
170 
171  /*
172  * Check it's within restricted VCO range
173  * unless of course the desired frequency is
174  * above the restricted range, then test
175  * against VCO limit
176  */
177  if ((ulVCO >= STG4K3_PLL_MINR_VCO) &&
178  ((ulVCO <= STG4K3_PLL_MAXR_VCO) ||
179  ((coreClock > STG4K3_PLL_MAXR_VCO)
180  && (ulVCO <= STG4K3_PLL_MAX_VCO)))) {
181  ulTmp = (ulVCO >> OD); /* Clock = VCO / (2^OD) */
182 
183  /* Is this clock good enough? */
184  if ((ulTmp >= ulMinClock)
185  && (ulTmp <= ulMaxClock)) {
186  ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K3_PLL_MAX_R)) >> 10);
187 
188  ulVcoScore = ((ulVCO - STG4K3_PLL_MINR_VCO)) / ((STG4K3_PLL_MAXR_VCO - STG4K3_PLL_MINR_VCO) >> 10);
189  ulScore = ulPhaseScore + ulVcoScore;
190 
191  if (!ulBestScore) {
192  ulBestVCO = ulVCO;
193  ulBestOD = OD;
194  ulBestF = F;
195  ulBestR = R;
196  ulBestClk = ulTmp;
197  ulBestScore =
198  ulScore;
199  }
200  /* is this better, ( aim for highest Score) */
201  /*--------------------------------------------------------------------------
202  Here we want to use a scoring system which will take account of both the
203  value at the phase comparater and the VCO output
204  to do this we will use a cumulative score between the two
205  The way this ends up is that we choose the first value in the loop anyway
206  but we shall keep this code in case new restrictions come into play
207  --------------------------------------------------------------------------*/
208  if ((ulScore >= ulBestScore) && (OD > 0)) {
209  ulBestVCO = ulVCO;
210  ulBestOD = OD;
211  ulBestF = F;
212  ulBestR = R;
213  ulBestClk = ulTmp;
214  ulBestScore =
215  ulScore;
216  }
217  }
218  }
219  F++;
220  }
221  R++;
222  }
223  }
224 
225  /*
226  did we find anything?
227  Then return RFOD
228  */
229  if (ulBestScore) {
230  *ROut = ulBestR;
231  *FOut = ulBestF;
232 
233  if ((ulBestOD == 2) || (ulBestOD == 3)) {
234  *POut = 3;
235  } else
236  *POut = ulBestOD;
237 
238  }
239 
240  return (ulBestClk);
241 }
242 
243 int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev)
244 {
245  u32 F, R, P;
246  u16 core_pll = 0, sub;
247  u32 ulCoreClock;
248  u32 tmp;
249  u32 ulChipSpeed;
250 
251  STG_WRITE_REG(IntMask, 0xFFFF);
252 
253  /* Disable Primary Core Thread0 */
254  tmp = STG_READ_REG(Thread0Enable);
255  CLEAR_BIT(0);
256  STG_WRITE_REG(Thread0Enable, tmp);
257 
258  /* Disable Primary Core Thread1 */
259  tmp = STG_READ_REG(Thread1Enable);
260  CLEAR_BIT(0);
261  STG_WRITE_REG(Thread1Enable, tmp);
262 
263  STG_WRITE_REG(SoftwareReset,
264  PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST);
265  STG_WRITE_REG(SoftwareReset,
266  PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST |
267  PMX2_SOFTRESET_ROM_RST);
268 
269  /* Need to play around to reset TA */
270  STG_WRITE_REG(TAConfiguration, 0);
271  STG_WRITE_REG(SoftwareReset,
272  PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST);
273  STG_WRITE_REG(SoftwareReset,
274  PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST |
275  PMX2_SOFTRESET_ROM_RST);
276 
277  pci_read_config_word(pDev, PCI_CONFIG_SUBSYS_ID, &sub);
278 
279  ulChipSpeed = InitSDRAMRegisters(pSTGReg, (u32)sub,
280  (u32)pDev->revision);
281 
282  if (ulChipSpeed == 0)
283  return -EINVAL;
284 
285  ulCoreClock = ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P);
286 
287  core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
288 
289  /* Set Core PLL Control to Core PLL Mode */
290 
291  /* Send bits 0:7 of the Core PLL Mode register */
292  tmp = ((CORE_PLL_MODE_REG_0_7 << 8) | (core_pll & 0x00FF));
293  pci_write_config_word(pDev, CorePllControl, tmp);
294  /* Without some delay between the PCI config writes the clock does
295  not reliably set when the code is compiled -O3
296  */
297  OS_DELAY(1000000);
298 
299  tmp |= SET_BIT(14);
300  pci_write_config_word(pDev, CorePllControl, tmp);
301  OS_DELAY(1000000);
302 
303  /* Send bits 8:15 of the Core PLL Mode register */
304  tmp =
305  ((CORE_PLL_MODE_REG_8_15 << 8) | ((core_pll & 0xFF00) >> 8));
306  pci_write_config_word(pDev, CorePllControl, tmp);
307  OS_DELAY(1000000);
308 
309  tmp |= SET_BIT(14);
310  pci_write_config_word(pDev, CorePllControl, tmp);
311  OS_DELAY(1000000);
312 
313  STG_WRITE_REG(SoftwareReset, PMX2_SOFTRESET_ALL);
314 
315 #if 0
316  /* Enable Primary Core Thread0 */
317  tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0));
318  STG_WRITE_REG(Thread0Enable, tmp);
319 
320  /* Enable Primary Core Thread1 */
321  tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0));
322  STG_WRITE_REG(Thread1Enable, tmp);
323 #endif
324 
325  return 0;
326 }
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