Go to the source code of this file.
| #define ACE_BYTE_SWAP_BD 0x02 |
| #define ACE_BYTE_SWAP_DMA 0x10 |
| #define ACE_FATAL 0x40000000 |
| #define ACE_JUMBO_MTU 9000 |
| #define ACE_NO_JUMBO_FRAG 0x200 |
| #define ACE_SHORT_DELAY 2 |
| #define ACE_TRACE_SIZE 0x8000 |
| #define ACE_WINDOW_SIZE 0x800 |
| #define ACE_WORD_SWAP_BD 0x04 /* not actually used */ |
| #define BD_FLG_BCAST 0x60 |
| #define BD_FLG_COAL_NOW 0x800 |
| #define BD_FLG_FRAME_ERROR 0x400 |
| #define BD_FLG_IP_FRAG 0x80 |
| #define BD_FLG_IP_FRAG_END 0x100 |
| #define BD_FLG_IP_SUM 0x02 |
| #define BD_FLG_JUMBO 0x10 |
| #define BD_FLG_MCAST 0x40 |
| #define BD_FLG_MINI 0x1000 |
| #define BD_FLG_TCP_UDP_SUM 0x01 |
| #define BD_FLG_TYP_MASK 0x60 |
| #define BD_FLG_UCAST 0x20 |
| #define BD_FLG_VLAN_TAG 0x200 |
| #define C_ADD_MULTICAST_ADDR 0x08 |
| #define C_C_FDR_FILT_DISABLE 0x02 |
| #define C_C_FDR_FILT_ENABLE 0x01 |
| #define C_C_MCAST_DISABLE 0x02 |
| #define C_C_MCAST_ENABLE 0x01 |
| #define C_C_NEGOTIATE_10_100 0x02 |
| #define C_C_NEGOTIATE_BOTH 0x00 |
| #define C_C_NEGOTIATE_GIG 0x01 |
| #define C_C_PROMISC_DISABLE 0x02 |
| #define C_C_PROMISC_ENABLE 0x01 |
| #define C_C_STACK_DOWN 0x02 |
| #define C_C_STACK_UP 0x01 |
| #define C_CLEAR_PROFILE 0x0d |
| #define C_CLEAR_STATS 0x0f |
| #define C_DEL_MULTICAST_ADDR 0x09 |
| #define C_FDR_FILTERING 0x02 |
| #define C_HOST_STATE 0x01 |
| #define C_LNK_NEGOTIATION 0x0b |
| #define C_REFRESH_STATS 0x11 |
| #define C_RESET_JUMBO_RNG 0x05 |
| #define C_SET_MAC_ADDR 0x0c |
| #define C_SET_MULTICAST_MODE 0x0e |
| #define C_SET_PROMISC_MODE 0x0a |
| #define C_SET_RX_JUMBO_PRD_IDX 0x10 |
| #define C_SET_RX_PRD_IDX 0x03 |
| #define C_UPDATE_STATS 0x04 |
| #define CMD_RING_ENTRIES 64 |
| #define CPU_HALT 0x00010000 |
| #define CPU_HALTED 0xffff0000 |
| #define CPU_PROM_FAILED 0x10 |
| #define DMA_READ_MAX_128 0x14 |
| #define DMA_READ_MAX_16 0x08 |
| #define DMA_READ_MAX_1K 0x1c |
| #define DMA_READ_MAX_256 0x18 |
| #define DMA_READ_MAX_32 0x0c |
| #define DMA_READ_MAX_4 0x04 |
| #define DMA_READ_MAX_64 0x10 |
| #define DMA_READ_WRITE_MASK 0xfc |
| #define DMA_THRESH_16W 0x100 |
| #define DMA_THRESH_1W 0x10 |
| #define DMA_THRESH_2W 0x20 |
| #define DMA_THRESH_32W 0x0 /* not described in doc, but exists. */ |
| #define DMA_THRESH_4W 0x40 |
| #define DMA_THRESH_8W 0x80 |
| #define DMA_WRITE_ALL_ALIGN 0x00800000 |
| #define DMA_WRITE_MAX_128 0xa0 |
| #define DMA_WRITE_MAX_16 0x40 |
| #define DMA_WRITE_MAX_1K 0xe0 |
| #define DMA_WRITE_MAX_256 0xc0 |
| #define DMA_WRITE_MAX_32 0x60 |
| #define DMA_WRITE_MAX_4 0x20 |
| #define DMA_WRITE_MAX_64 0x80 |
| #define E_C_ERR_BAD_CFG 0x03 |
| #define E_C_ERR_INVAL_CMD 0x01 |
| #define E_C_ERR_UNIMP_CMD 0x02 |
| #define E_C_LINK_10_100 0x03 |
| #define E_C_LINK_DOWN 0x02 |
| #define E_C_MCAST_ADDR_ADD 0x01 |
| #define E_C_MCAST_ADDR_DEL 0x02 |
| #define E_FW_RUNNING 0x01 |
| #define E_MCAST_LIST 0x08 |
| #define E_RESET_JUMBO_RNG 0x09 |
| #define E_STATS_UPDATE 0x04 |
| #define E_STATS_UPDATED 0x04 |
| #define EEPROM_BASE 0xa0000000 |
| #define EEPROM_CLK_OUT 0x100000 |
| #define EEPROM_DATA_IN 0x800000 |
| #define EEPROM_DATA_OUT 0x400000 |
| #define EEPROM_READ_SELECT 0xa1 |
| #define EEPROM_WRITE_ENABLE 0x200000 |
| #define EEPROM_WRITE_SELECT 0xa0 |
| #define EVT_RING_ENTRIES 256 |
| #define LNK_1000MB 0x00040000 |
| #define LNK_100MB 0x00020000 |
| #define LNK_10MB 0x00010000 |
| #define LNK_ALTEON 0x08000000 |
| #define LNK_ENABLE 0x40000000 |
| #define LNK_FULL_DUPLEX 0x00080000 |
| #define LNK_HALF_DUPLEX 0x00100000 |
| #define LNK_JAM 0x02000000 |
| #define LNK_JUMBO 0x04000000 |
| #define LNK_NEG_ADVANCED 0x00400000 |
| #define LNK_NEG_FCTL 0x10000000 |
| #define LNK_NEGOTIATE 0x20000000 |
| #define LNK_NIC 0x01000000 |
| #define LNK_PREF 0x00008000 |
| #define LNK_RX_FLOW_CTL_Y 0x00800000 |
| #define LNK_TX_FLOW_CTL_Y 0x00200000 |
| #define LNK_UP 0x80000000 |
| #define MAX_TX_RING_ENTRIES 256 |
| #define MEM_READ_MULTIPLE 0x00020000 |
| #define PCI_32BIT 0x00100000 |
| #define PCI_66MHZ 0x00080000 |
| #define RCB_FLG_COAL_INT_ONLY 0x20 |
| #define RCB_FLG_EXT_RX_BD 0x100 |
| #define RCB_FLG_IEEE_SNAP_SUM 0x80 |
| #define RCB_FLG_IP_SUM 0x02 |
| #define RCB_FLG_NO_PSEUDO_HDR 0x08 |
| #define RCB_FLG_RNG_DISABLE 0x200 |
| #define RCB_FLG_TCP_UDP_SUM 0x01 |
| #define RCB_FLG_TX_HOST_RING 0x40 |
| #define RCB_FLG_VLAN_ASSIST 0x10 |
| #define READ_CMD_MEM 0x06000000 |
| #define RX_JUMBO_RING_ENTRIES 256 |
| #define RX_MINI_RING_ENTRIES 1024 |
| #define RX_RETURN_RING_ENTRIES 2048 |
| #define RX_RETURN_RING_SIZE |
Value:(RX_MAX_RETURN_RING_ENTRIES * \
Definition at line 485 of file acenic.h.
| #define RX_STD_RING_ENTRIES 512 |
| #define SRAM_BANK_512K 0x200 |
| #define SYNC_SRAM_TIMING 0x100000 |
| #define TICKS_PER_SEC 1000000 |
| #define TIGON_I_TX_RING_ENTRIES 128 |
| #define tx_free |
( |
|
ap | ) |
tx_space((ap)->tx_ret_csm, (ap)->tx_prd, ap) |
| #define TX_RING_BASE 0x3800 |
| #define tx_ring_full |
( |
|
ap, |
|
|
|
csm, |
|
|
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prd |
|
) |
| (tx_space(ap, csm, prd) <= TX_RESERVED) |
| #define USE_TX_COAL_NOW 0 |
| #define WRITE_CMD_MEM 0x70000000 |
1.8.2