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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | pll_data |
| struct | clk |
Macros | |
| #define | DAVINCI_PLL1_BASE 0x01c40800 |
| #define | DAVINCI_PLL2_BASE 0x01c40c00 |
| #define | MAX_PLL 2 |
| #define | PLLCTL 0x100 |
| #define | PLLCTL_PLLEN BIT(0) |
| #define | PLLCTL_PLLPWRDN BIT(1) |
| #define | PLLCTL_PLLRST BIT(3) |
| #define | PLLCTL_PLLDIS BIT(4) |
| #define | PLLCTL_PLLENSRC BIT(5) |
| #define | PLLCTL_CLKMODE BIT(8) |
| #define | PLLM 0x110 |
| #define | PLLM_PLLM_MASK 0xff |
| #define | PREDIV 0x114 |
| #define | PLLDIV1 0x118 |
| #define | PLLDIV2 0x11c |
| #define | PLLDIV3 0x120 |
| #define | POSTDIV 0x128 |
| #define | BPDIV 0x12c |
| #define | PLLCMD 0x138 |
| #define | PLLSTAT 0x13c |
| #define | PLLALNCTL 0x140 |
| #define | PLLDCHANGE 0x144 |
| #define | PLLCKEN 0x148 |
| #define | PLLCKSTAT 0x14c |
| #define | PLLSYSTAT 0x150 |
| #define | PLLDIV4 0x160 |
| #define | PLLDIV5 0x164 |
| #define | PLLDIV6 0x168 |
| #define | PLLDIV7 0x16c |
| #define | PLLDIV8 0x170 |
| #define | PLLDIV9 0x174 |
| #define | PLLDIV_EN BIT(15) |
| #define | PLLDIV_RATIO_MASK 0x1f |
| #define | PLL_BYPASS_TIME 1 |
| #define | PLL_RESET_TIME 1 |
| #define | PLL_LOCK_TIME 20 |
| #define | PLLSTAT_GOSTAT BIT(0) |
| #define | PLLCMD_GOSET BIT(0) |
| #define | PLL_HAS_PREDIV 0x01 |
| #define | PLL_HAS_POSTDIV 0x02 |
| #define | ALWAYS_ENABLED BIT(1) |
| #define | CLK_PSC BIT(2) |
| #define | CLK_PLL BIT(3) /* PLL-derived clock */ |
| #define | PRE_PLL BIT(4) /* source is before PLL mult/div */ |
| #define | PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ |
| #define | PSC_FORCE BIT(6) /* Force module state transtition */ |
| #define | CLK(dev, con, ck) |
Functions | |
| int | davinci_clk_init (struct clk_lookup *clocks) |
| int | davinci_set_pllrate (struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv) |
| int | davinci_set_sysclk_rate (struct clk *clk, unsigned long rate) |
| int | davinci_set_refclk_rate (unsigned long rate) |
| int | davinci_simple_set_rate (struct clk *clk, unsigned long rate) |
| void | davinci_watchdog_reset (struct platform_device *) |
Variables | |
| struct platform_device | davinci_wdt_device |
| #define CLK | ( | dev, | |
| con, | |||
| ck | |||
| ) |
| int davinci_clk_init | ( | struct clk_lookup * | clocks | ) |
| int davinci_set_pllrate | ( | struct pll_data * | pll, |
| unsigned int | prediv, | ||
| unsigned int | mult, | ||
| unsigned int | postdiv | ||
| ) |
davinci_set_pllrate - set the output rate of a given PLL.
Note: Currently tested to work with OMAP-L138 only.
: pll whose rate needs to be changed. : The pre divider value. Passing 0 disables the pre-divider. : The multiplier value. Passing 0 leads to multiply-by-one. : The post divider value. Passing 0 disables the post-divider.
davinci_set_refclk_rate() - Set the reference clock rate : The new rate.
Sets the reference clock rate to a given value. This will most likely result in the entire clock tree getting updated.
This is used to support boards which use a reference clock different than that used by default in <soc>.c file. The reference clock rate should be updated early in the boot process; ideally soon after the clock tree has been initialized once with the default reference clock rate (davinci_common_init()).
Returns 0 on success, error otherwise.
| void davinci_watchdog_reset | ( | struct platform_device * | ) |
| struct platform_device davinci_wdt_device |
1.8.2