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Data Structures | Macros | Functions | Variables
clock.h File Reference
#include <linux/list.h>
#include <linux/clkdev.h>

Go to the source code of this file.

Data Structures

struct  pll_data
 
struct  clk
 

Macros

#define DAVINCI_PLL1_BASE   0x01c40800
 
#define DAVINCI_PLL2_BASE   0x01c40c00
 
#define MAX_PLL   2
 
#define PLLCTL   0x100
 
#define PLLCTL_PLLEN   BIT(0)
 
#define PLLCTL_PLLPWRDN   BIT(1)
 
#define PLLCTL_PLLRST   BIT(3)
 
#define PLLCTL_PLLDIS   BIT(4)
 
#define PLLCTL_PLLENSRC   BIT(5)
 
#define PLLCTL_CLKMODE   BIT(8)
 
#define PLLM   0x110
 
#define PLLM_PLLM_MASK   0xff
 
#define PREDIV   0x114
 
#define PLLDIV1   0x118
 
#define PLLDIV2   0x11c
 
#define PLLDIV3   0x120
 
#define POSTDIV   0x128
 
#define BPDIV   0x12c
 
#define PLLCMD   0x138
 
#define PLLSTAT   0x13c
 
#define PLLALNCTL   0x140
 
#define PLLDCHANGE   0x144
 
#define PLLCKEN   0x148
 
#define PLLCKSTAT   0x14c
 
#define PLLSYSTAT   0x150
 
#define PLLDIV4   0x160
 
#define PLLDIV5   0x164
 
#define PLLDIV6   0x168
 
#define PLLDIV7   0x16c
 
#define PLLDIV8   0x170
 
#define PLLDIV9   0x174
 
#define PLLDIV_EN   BIT(15)
 
#define PLLDIV_RATIO_MASK   0x1f
 
#define PLL_BYPASS_TIME   1
 
#define PLL_RESET_TIME   1
 
#define PLL_LOCK_TIME   20
 
#define PLLSTAT_GOSTAT   BIT(0)
 
#define PLLCMD_GOSET   BIT(0)
 
#define PLL_HAS_PREDIV   0x01
 
#define PLL_HAS_POSTDIV   0x02
 
#define ALWAYS_ENABLED   BIT(1)
 
#define CLK_PSC   BIT(2)
 
#define CLK_PLL   BIT(3) /* PLL-derived clock */
 
#define PRE_PLL   BIT(4) /* source is before PLL mult/div */
 
#define PSC_SWRSTDISABLE   BIT(5) /* Disable state is SwRstDisable */
 
#define PSC_FORCE   BIT(6) /* Force module state transtition */
 
#define CLK(dev, con, ck)
 

Functions

int davinci_clk_init (struct clk_lookup *clocks)
 
int davinci_set_pllrate (struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv)
 
int davinci_set_sysclk_rate (struct clk *clk, unsigned long rate)
 
int davinci_set_refclk_rate (unsigned long rate)
 
int davinci_simple_set_rate (struct clk *clk, unsigned long rate)
 
void davinci_watchdog_reset (struct platform_device *)
 

Variables

struct platform_device davinci_wdt_device
 

Macro Definition Documentation

#define ALWAYS_ENABLED   BIT(1)

Definition at line 109 of file clock.h.

#define BPDIV   0x12c

Definition at line 36 of file clock.h.

#define CLK (   dev,
  con,
  ck 
)
Value:
{ \
.dev_id = dev, \
.con_id = con, \
.clk = ck, \
} \

Definition at line 116 of file clock.h.

#define CLK_PLL   BIT(3) /* PLL-derived clock */

Definition at line 111 of file clock.h.

#define CLK_PSC   BIT(2)

Definition at line 110 of file clock.h.

#define DAVINCI_PLL1_BASE   0x01c40800

Definition at line 15 of file clock.h.

#define DAVINCI_PLL2_BASE   0x01c40c00

Definition at line 16 of file clock.h.

#define MAX_PLL   2

Definition at line 17 of file clock.h.

#define PLL_BYPASS_TIME   1

Definition at line 59 of file clock.h.

#define PLL_HAS_POSTDIV   0x02

Definition at line 85 of file clock.h.

#define PLL_HAS_PREDIV   0x01

Definition at line 84 of file clock.h.

#define PLL_LOCK_TIME   20

Definition at line 66 of file clock.h.

#define PLL_RESET_TIME   1

Definition at line 61 of file clock.h.

#define PLLALNCTL   0x140

Definition at line 39 of file clock.h.

#define PLLCKEN   0x148

Definition at line 41 of file clock.h.

#define PLLCKSTAT   0x14c

Definition at line 42 of file clock.h.

#define PLLCMD   0x138

Definition at line 37 of file clock.h.

#define PLLCMD_GOSET   BIT(0)

Definition at line 74 of file clock.h.

#define PLLCTL   0x100

Definition at line 20 of file clock.h.

#define PLLCTL_CLKMODE   BIT(8)

Definition at line 26 of file clock.h.

#define PLLCTL_PLLDIS   BIT(4)

Definition at line 24 of file clock.h.

#define PLLCTL_PLLEN   BIT(0)

Definition at line 21 of file clock.h.

#define PLLCTL_PLLENSRC   BIT(5)

Definition at line 25 of file clock.h.

#define PLLCTL_PLLPWRDN   BIT(1)

Definition at line 22 of file clock.h.

#define PLLCTL_PLLRST   BIT(3)

Definition at line 23 of file clock.h.

#define PLLDCHANGE   0x144

Definition at line 40 of file clock.h.

#define PLLDIV1   0x118

Definition at line 32 of file clock.h.

#define PLLDIV2   0x11c

Definition at line 33 of file clock.h.

#define PLLDIV3   0x120

Definition at line 34 of file clock.h.

#define PLLDIV4   0x160

Definition at line 44 of file clock.h.

#define PLLDIV5   0x164

Definition at line 45 of file clock.h.

#define PLLDIV6   0x168

Definition at line 46 of file clock.h.

#define PLLDIV7   0x16c

Definition at line 47 of file clock.h.

#define PLLDIV8   0x170

Definition at line 48 of file clock.h.

#define PLLDIV9   0x174

Definition at line 49 of file clock.h.

#define PLLDIV_EN   BIT(15)

Definition at line 50 of file clock.h.

#define PLLDIV_RATIO_MASK   0x1f

Definition at line 51 of file clock.h.

#define PLLM   0x110

Definition at line 28 of file clock.h.

#define PLLM_PLLM_MASK   0xff

Definition at line 29 of file clock.h.

#define PLLSTAT   0x13c

Definition at line 38 of file clock.h.

#define PLLSTAT_GOSTAT   BIT(0)

Definition at line 73 of file clock.h.

#define PLLSYSTAT   0x150

Definition at line 43 of file clock.h.

#define POSTDIV   0x128

Definition at line 35 of file clock.h.

#define PRE_PLL   BIT(4) /* source is before PLL mult/div */

Definition at line 112 of file clock.h.

#define PREDIV   0x114

Definition at line 31 of file clock.h.

#define PSC_FORCE   BIT(6) /* Force module state transtition */

Definition at line 114 of file clock.h.

#define PSC_SWRSTDISABLE   BIT(5) /* Disable state is SwRstDisable */

Definition at line 113 of file clock.h.

Function Documentation

int davinci_clk_init ( struct clk_lookup clocks)

Definition at line 537 of file clock.c.

int davinci_set_pllrate ( struct pll_data pll,
unsigned int  prediv,
unsigned int  mult,
unsigned int  postdiv 
)

davinci_set_pllrate - set the output rate of a given PLL.

Note: Currently tested to work with OMAP-L138 only.

: pll whose rate needs to be changed. : The pre divider value. Passing 0 disables the pre-divider. : The multiplier value. Passing 0 leads to multiply-by-one. : The post divider value. Passing 0 disables the post-divider.

Definition at line 438 of file clock.c.

int davinci_set_refclk_rate ( unsigned long  rate)

davinci_set_refclk_rate() - Set the reference clock rate : The new rate.

Sets the reference clock rate to a given value. This will most likely result in the entire clock tree getting updated.

This is used to support boards which use a reference clock different than that used by default in <soc>.c file. The reference clock rate should be updated early in the boot process; ideally soon after the clock tree has been initialized once with the default reference clock rate (davinci_common_init()).

Returns 0 on success, error otherwise.

Definition at line 520 of file clock.c.

int davinci_set_sysclk_rate ( struct clk clk,
unsigned long  rate 
)

Definition at line 280 of file clock.c.

int davinci_simple_set_rate ( struct clk clk,
unsigned long  rate 
)

Definition at line 361 of file clock.c.

void davinci_watchdog_reset ( struct platform_device )

Definition at line 419 of file time.c.

Variable Documentation

struct platform_device davinci_wdt_device

Definition at line 297 of file devices.c.