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setup.c File Reference
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/m32r.h>
#include <asm/io.h>

Go to the source code of this file.

Data Structures

struct  pld_icu_data_t


#define irq2port(x)   (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
#define irq2pldirq(x)   ((x) - M32700UT_PLD_IRQ_BASE)
#define pldirq2port(x)
#define irq2lanpldirq(x)   ((x) - M32700UT_LAN_PLD_IRQ_BASE)
#define lanpldirq2port(x)
#define irq2lcdpldirq(x)   ((x) - M32700UT_LCD_PLD_IRQ_BASE)
#define lcdpldirq2port(x)


void __init init_IRQ (void)
 arch_initcall (platform_init)


icu_data_t icu_data [M32700UT_NUM_CPU_IRQ]

Macro Definition Documentation

#define irq2lanpldirq (   x)    ((x) - M32700UT_LAN_PLD_IRQ_BASE)

Definition at line 140 of file setup.c.

#define irq2lcdpldirq (   x)    ((x) - M32700UT_LCD_PLD_IRQ_BASE)

Definition at line 200 of file setup.c.

#define irq2pldirq (   x)    ((x) - M32700UT_PLD_IRQ_BASE)

Definition at line 76 of file setup.c.

#define irq2port (   x)    (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

Definition at line 25 of file setup.c.

#define lanpldirq2port (   x)
(unsigned long)((int)M32700UT_LAN_ICUCR1 + \
(((x) - 1) * sizeof(unsigned short)))

Definition at line 141 of file setup.c.

#define lcdpldirq2port (   x)
(unsigned long)((int)M32700UT_LCD_ICUCR1 + \
(((x) - 1) * sizeof(unsigned short)))

Definition at line 201 of file setup.c.

#define pldirq2port (   x)
(unsigned long)((int)PLD_ICUCR1 + \
(((x) - 1) * sizeof(unsigned short)))

Definition at line 77 of file setup.c.

Function Documentation

arch_initcall ( platform_init  )
void __init init_IRQ ( void  )

The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.

The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.

Definition at line 257 of file setup.c.

Variable Documentation

icu_data_t icu_data[M32700UT_NUM_CPU_IRQ]

Definition at line 27 of file setup.c.