10 #define pcibios_assign_all_busses() 1
17 struct pci_channel *
next;
23 unsigned int nr_resources;
25 unsigned long io_offset;
26 unsigned long mem_offset;
28 unsigned long reg_base;
29 unsigned long io_map_base;
32 unsigned int need_domain_info;
36 unsigned int err_irq, serr_irq;
46 extern int early_read_config_byte(
struct pci_channel *hose,
int top_bus,
48 extern int early_read_config_word(
struct pci_channel *hose,
int top_bus,
50 extern int early_read_config_dword(
struct pci_channel *hose,
int top_bus,
52 extern int early_write_config_byte(
struct pci_channel *hose,
int top_bus,
54 extern int early_write_config_word(
struct pci_channel *hose,
int top_bus,
56 extern int early_write_config_dword(
struct pci_channel *hose,
int top_bus,
60 unsigned int status,
struct pci_channel *hose);
62 int top_bus,
int current_bus);
86 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
93 #define PCI_DISABLE_MWI
96 enum pci_dma_burst_strategy *strat,
97 unsigned long *strategy_parameter)
99 unsigned long cacheline_size;
107 cacheline_size = byte << 2;
109 *strat = PCI_DMA_BURST_MULTIPLE;
110 *strategy_parameter = cacheline_size;
117 #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
121 struct pci_channel *hose = bus->
sysdata;
122 return hose->need_domain_info;
128 return channel ? 15 : 14;