|
| #define | PCI_DMA_BIDIRECTIONAL 0 |
| |
| #define | PCI_DMA_TODEVICE 1 |
| |
| #define | PCI_DMA_FROMDEVICE 2 |
| |
| #define | PCI_DMA_NONE 3 |
| |
| #define | PCI_BRIDGE_RESOURCE_NUM 4 |
| |
| #define | PCI_D0 ((pci_power_t __force) 0) |
| |
| #define | PCI_D1 ((pci_power_t __force) 1) |
| |
| #define | PCI_D2 ((pci_power_t __force) 2) |
| |
| #define | PCI_D3hot ((pci_power_t __force) 3) |
| |
| #define | PCI_D3cold ((pci_power_t __force) 4) |
| |
| #define | PCI_UNKNOWN ((pci_power_t __force) 5) |
| |
| #define | PCI_POWER_ERROR ((pci_power_t __force) -1) |
| |
| #define | PCI_PM_D2_DELAY 200 |
| |
| #define | PCI_PM_D3_WAIT 10 |
| |
| #define | PCI_PM_D3COLD_WAIT 100 |
| |
| #define | PCI_PM_BUS_WAIT 50 |
| |
| #define | to_pci_dev(n) container_of(n, struct pci_dev, dev) |
| |
| #define | for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
| |
| #define | to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
| |
| #define | PCI_SUBTRACTIVE_DECODE 0x1 |
| |
| #define | PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
| |
| #define | pci_bus_b(n) list_entry(n, struct pci_bus, node) |
| |
| #define | to_pci_bus(n) container_of(n, struct pci_bus, dev) |
| |
| #define | PCIBIOS_SUCCESSFUL 0x00 |
| |
| #define | PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
| |
| #define | PCIBIOS_BAD_VENDOR_ID 0x83 |
| |
| #define | PCIBIOS_DEVICE_NOT_FOUND 0x86 |
| |
| #define | PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
| |
| #define | PCIBIOS_SET_FAILED 0x88 |
| |
| #define | PCIBIOS_BUFFER_TOO_SMALL 0x89 |
| |
| #define | to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
| |
| #define | DEFINE_PCI_DEVICE_TABLE(_table) const struct pci_device_id _table[] __devinitconst |
| |
| #define | PCI_DEVICE(vend, dev) |
| |
| #define | PCI_DEVICE_CLASS(dev_class, dev_class_mask) |
| |
| #define | PCI_VDEVICE(vendor, device) |
| |
| #define | _PCI_NOP(o, s, t) |
| |
| #define | _PCI_NOP_ALL(o, x) |
| |
| #define | pci_dev_present(ids) (0) |
| |
| #define | no_pci_devices() (1) |
| |
| #define | pci_dev_put(dev) do { } while (0) |
| |
| #define | pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
| |
| #define | dev_is_pci(d) (false) |
| |
| #define | dev_is_pf(d) (false) |
| |
| #define | dev_num_vf(d) (0) |
| |
| #define | PCIBIOS_MAX_MEM_32 (-1) |
| |
| #define | pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
| |
| #define | pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
| |
| #define | pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
| |
| #define | pci_resource_len(dev, bar) |
| |
| #define | DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,class_shift, hook) |
| |
| #define | DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) |
| |
| #define | DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) |
| |
| #define | DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) |
| |
| #define | DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) |
| |
| #define | DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) |
| |
| #define | DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) |
| |
| #define | DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) |
| |
| #define | PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
| |
| #define | PCIPCI_TRITON 2 |
| |
| #define | PCIPCI_NATOMA 4 |
| |
| #define | PCIPCI_VIAETBF 8 |
| |
| #define | PCIPCI_VSFX 16 |
| |
| #define | PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
| |
| #define | PCIAGP_FAIL 64 /* No PCI to AGP DMA */ |
| |
| #define | PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
| |
| #define | PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) |
| |
| #define | PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ |
| |
| #define | PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ |
| |
| #define | PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ |
| |
| #define | PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) |
| |
| #define | PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) |
| |
| #define | PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) |
| |
| #define | PCI_VPD_STIN_END 0x78 /* End */ |
| |
| #define | PCI_VPD_SRDT_END PCI_VPD_STIN_END |
| |
| #define | PCI_VPD_SRDT_TIN_MASK 0x78 |
| |
| #define | PCI_VPD_SRDT_LEN_MASK 0x07 |
| |
| #define | PCI_VPD_LRDT_TAG_SIZE 3 |
| |
| #define | PCI_VPD_SRDT_TAG_SIZE 1 |
| |
| #define | PCI_VPD_INFO_FLD_HDR_SIZE 3 |
| |
| #define | PCI_VPD_RO_KEYWORD_PARTNO "PN" |
| |
| #define | PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
| |
| #define | PCI_VPD_RO_KEYWORD_VENDOR0 "V0" |
| |
| #define | PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
| |
|
| enum | pci_mmap_state { pci_mmap_io,
pci_mmap_mem
} |
| |
| enum | {
PCI_STD_RESOURCES,
PCI_STD_RESOURCE_END = 5,
PCI_ROM_RESOURCE,
PCI_BRIDGE_RESOURCES,
PCI_BRIDGE_RESOURCE_END,
PCI_NUM_RESOURCES,
DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES
} |
| |
| enum | pci_channel_state { pci_channel_io_normal = (__force pci_channel_state_t) 1,
pci_channel_io_frozen = (__force pci_channel_state_t) 2,
pci_channel_io_perm_failure = (__force pci_channel_state_t) 3
} |
| |
| enum | pcie_reset_state { pcie_deassert_reset = (__force pcie_reset_state_t) 1,
pcie_warm_reset = (__force pcie_reset_state_t) 2,
pcie_hot_reset = (__force pcie_reset_state_t) 3
} |
| |
| enum | pci_dev_flags { PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4
} |
| |
| enum | pci_irq_reroute_variant { INTEL_IRQ_REROUTE_VARIANT = 1,
MAX_IRQ_REROUTE_VARIANTS = 3
} |
| |
| enum | pci_bus_flags { PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2
} |
| |
| enum | pci_bus_speed {
PCI_SPEED_33MHz = 0x00,
PCI_SPEED_66MHz = 0x01,
PCI_SPEED_66MHz_PCIX = 0x02,
PCI_SPEED_100MHz_PCIX = 0x03,
PCI_SPEED_133MHz_PCIX = 0x04,
PCI_SPEED_66MHz_PCIX_ECC = 0x05,
PCI_SPEED_100MHz_PCIX_ECC = 0x06,
PCI_SPEED_133MHz_PCIX_ECC = 0x07,
PCI_SPEED_66MHz_PCIX_266 = 0x09,
PCI_SPEED_100MHz_PCIX_266 = 0x0a,
PCI_SPEED_133MHz_PCIX_266 = 0x0b,
AGP_UNKNOWN = 0x0c,
AGP_1X = 0x0d,
AGP_2X = 0x0e,
AGP_4X = 0x0f,
AGP_8X = 0x10,
PCI_SPEED_66MHz_PCIX_533 = 0x11,
PCI_SPEED_100MHz_PCIX_533 = 0x12,
PCI_SPEED_133MHz_PCIX_533 = 0x13,
PCIE_SPEED_2_5GT = 0x14,
PCIE_SPEED_5_0GT = 0x15,
PCIE_SPEED_8_0GT = 0x16,
PCI_SPEED_UNKNOWN = 0xff
} |
| |
| enum | pci_ers_result {
PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5
} |
| |
| enum | pci_fixup_pass {
pci_fixup_early,
pci_fixup_header,
pci_fixup_final,
pci_fixup_enable,
pci_fixup_resume,
pci_fixup_suspend,
pci_fixup_resume_early
} |
| |
|
| struct pci_dev * | alloc_pci_dev (void) |
| |
| void | pci_set_host_bridge_release (struct pci_host_bridge *bridge, void(*release_fn)(struct pci_host_bridge *), void *release_data) |
| |
| int | raw_pci_read (unsigned int domain, unsigned int bus, unsigned int devfn, int reg, int len, u32 *val) |
| |
| int | raw_pci_write (unsigned int domain, unsigned int bus, unsigned int devfn, int reg, int len, u32 val) |
| |
| void __iomem * | pcim_iomap (struct pci_dev *pdev, int bar, unsigned long maxlen) |
| |
| void | pcim_iounmap (struct pci_dev *pdev, void __iomem *addr) |
| |
| void __iomem *const * | pcim_iomap_table (struct pci_dev *pdev) |
| |
| int | pcim_iomap_regions (struct pci_dev *pdev, int mask, const char *name) |
| |
| int | pcim_iomap_regions_request_all (struct pci_dev *pdev, int mask, const char *name) |
| |
| void | pcim_iounmap_regions (struct pci_dev *pdev, int mask) |
| |
| int | pcibios_add_platform_entries (struct pci_dev *dev) |
| |
| void | pcibios_disable_device (struct pci_dev *dev) |
| |
| void | pcibios_set_master (struct pci_dev *dev) |
| |
| int | pcibios_set_pcie_reset_state (struct pci_dev *dev, enum pcie_reset_state state) |
| |
| int | pci_ext_cfg_avail (struct pci_dev *dev) |
| |
| void __iomem * | pci_ioremap_bar (struct pci_dev *pdev, int bar) |
| |
| void | pci_request_acs (void) |
| |
| bool | pci_acs_enabled (struct pci_dev *pdev, u16 acs_flags) |
| |
| bool | pci_acs_path_enabled (struct pci_dev *start, struct pci_dev *end, u16 acs_flags) |
| |
| int | pci_vpd_find_tag (const u8 *buf, unsigned int off, unsigned int len, u8 rdt) |
| |
| int | pci_vpd_find_info_keyword (const u8 *buf, unsigned int off, unsigned int len, const char *kw) |
| |
| struct pci_dev * | pci_find_upstream_pcie_bridge (struct pci_dev *pdev) |
| |
| #define PCI_DEVICE_CLASS |
( |
|
dev_class, |
|
|
|
dev_class_mask |
|
) |
| |
Value:.class = (
dev_class), .class_mask = (dev_class_mask), \
PCI_DEVICE_CLASS - macro used to describe a specific pci device class : the class, subclass, prog-if triple for this device : the class mask for this device
This macro is used to create a struct pci_device_id that matches a specific PCI class. The vendor, device, subvendor, and subdevice fields will be set to PCI_ANY_ID.
Definition at line 615 of file pci.h.
pcibios_set_pcie_slot_reset - Set PCI-E reset state : pci device struct : reset state to enter
Return value: 0 if success
pcibios_set_pcie_reset_state - set reset state for device dev : the PCIe device reset : Reset state to enter into
Sets the PCIe reset state for the device. This is the default implementation. Architecture implementations can override this.
Definition at line 462 of file eeh.c.
1.8.2