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pci_regs.h File Reference

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Macros

#define PCI_STD_HEADER_SIZEOF   64
 
#define PCI_VENDOR_ID   0x00 /* 16 bits */
 
#define PCI_DEVICE_ID   0x02 /* 16 bits */
 
#define PCI_COMMAND   0x04 /* 16 bits */
 
#define PCI_COMMAND_IO   0x1 /* Enable response in I/O space */
 
#define PCI_COMMAND_MEMORY   0x2 /* Enable response in Memory space */
 
#define PCI_COMMAND_MASTER   0x4 /* Enable bus mastering */
 
#define PCI_COMMAND_SPECIAL   0x8 /* Enable response to special cycles */
 
#define PCI_COMMAND_INVALIDATE   0x10 /* Use memory write and invalidate */
 
#define PCI_COMMAND_VGA_PALETTE   0x20 /* Enable palette snooping */
 
#define PCI_COMMAND_PARITY   0x40 /* Enable parity checking */
 
#define PCI_COMMAND_WAIT   0x80 /* Enable address/data stepping */
 
#define PCI_COMMAND_SERR   0x100 /* Enable SERR */
 
#define PCI_COMMAND_FAST_BACK   0x200 /* Enable back-to-back writes */
 
#define PCI_COMMAND_INTX_DISABLE   0x400 /* INTx Emulation Disable */
 
#define PCI_STATUS   0x06 /* 16 bits */
 
#define PCI_STATUS_INTERRUPT   0x08 /* Interrupt status */
 
#define PCI_STATUS_CAP_LIST   0x10 /* Support Capability List */
 
#define PCI_STATUS_66MHZ   0x20 /* Support 66 Mhz PCI 2.1 bus */
 
#define PCI_STATUS_UDF   0x40 /* Support User Definable Features [obsolete] */
 
#define PCI_STATUS_FAST_BACK   0x80 /* Accept fast-back to back */
 
#define PCI_STATUS_PARITY   0x100 /* Detected parity error */
 
#define PCI_STATUS_DEVSEL_MASK   0x600 /* DEVSEL timing */
 
#define PCI_STATUS_DEVSEL_FAST   0x000
 
#define PCI_STATUS_DEVSEL_MEDIUM   0x200
 
#define PCI_STATUS_DEVSEL_SLOW   0x400
 
#define PCI_STATUS_SIG_TARGET_ABORT   0x800 /* Set on target abort */
 
#define PCI_STATUS_REC_TARGET_ABORT   0x1000 /* Master ack of " */
 
#define PCI_STATUS_REC_MASTER_ABORT   0x2000 /* Set on master abort */
 
#define PCI_STATUS_SIG_SYSTEM_ERROR   0x4000 /* Set when we drive SERR */
 
#define PCI_STATUS_DETECTED_PARITY   0x8000 /* Set on parity error */
 
#define PCI_CLASS_REVISION   0x08 /* High 24 bits are class, low 8 revision */
 
#define PCI_REVISION_ID   0x08 /* Revision ID */
 
#define PCI_CLASS_PROG   0x09 /* Reg. Level Programming Interface */
 
#define PCI_CLASS_DEVICE   0x0a /* Device class */
 
#define PCI_CACHE_LINE_SIZE   0x0c /* 8 bits */
 
#define PCI_LATENCY_TIMER   0x0d /* 8 bits */
 
#define PCI_HEADER_TYPE   0x0e /* 8 bits */
 
#define PCI_HEADER_TYPE_NORMAL   0
 
#define PCI_HEADER_TYPE_BRIDGE   1
 
#define PCI_HEADER_TYPE_CARDBUS   2
 
#define PCI_BIST   0x0f /* 8 bits */
 
#define PCI_BIST_CODE_MASK   0x0f /* Return result */
 
#define PCI_BIST_START   0x40 /* 1 to start BIST, 2 secs or less */
 
#define PCI_BIST_CAPABLE   0x80 /* 1 if BIST capable */
 
#define PCI_BASE_ADDRESS_0   0x10 /* 32 bits */
 
#define PCI_BASE_ADDRESS_1   0x14 /* 32 bits [htype 0,1 only] */
 
#define PCI_BASE_ADDRESS_2   0x18 /* 32 bits [htype 0 only] */
 
#define PCI_BASE_ADDRESS_3   0x1c /* 32 bits */
 
#define PCI_BASE_ADDRESS_4   0x20 /* 32 bits */
 
#define PCI_BASE_ADDRESS_5   0x24 /* 32 bits */
 
#define PCI_BASE_ADDRESS_SPACE   0x01 /* 0 = memory, 1 = I/O */
 
#define PCI_BASE_ADDRESS_SPACE_IO   0x01
 
#define PCI_BASE_ADDRESS_SPACE_MEMORY   0x00
 
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK   0x06
 
#define PCI_BASE_ADDRESS_MEM_TYPE_32   0x00 /* 32 bit address */
 
#define PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02 /* Below 1M [obsolete] */
 
#define PCI_BASE_ADDRESS_MEM_TYPE_64   0x04 /* 64 bit address */
 
#define PCI_BASE_ADDRESS_MEM_PREFETCH   0x08 /* prefetchable? */
 
#define PCI_BASE_ADDRESS_MEM_MASK   (~0x0fUL)
 
#define PCI_BASE_ADDRESS_IO_MASK   (~0x03UL)
 
#define PCI_CARDBUS_CIS   0x28
 
#define PCI_SUBSYSTEM_VENDOR_ID   0x2c
 
#define PCI_SUBSYSTEM_ID   0x2e
 
#define PCI_ROM_ADDRESS   0x30 /* Bits 31..11 are address, 10..1 reserved */
 
#define PCI_ROM_ADDRESS_ENABLE   0x01
 
#define PCI_ROM_ADDRESS_MASK   (~0x7ffUL)
 
#define PCI_CAPABILITY_LIST   0x34 /* Offset of first capability list entry */
 
#define PCI_INTERRUPT_LINE   0x3c /* 8 bits */
 
#define PCI_INTERRUPT_PIN   0x3d /* 8 bits */
 
#define PCI_MIN_GNT   0x3e /* 8 bits */
 
#define PCI_MAX_LAT   0x3f /* 8 bits */
 
#define PCI_PRIMARY_BUS   0x18 /* Primary bus number */
 
#define PCI_SECONDARY_BUS   0x19 /* Secondary bus number */
 
#define PCI_SUBORDINATE_BUS   0x1a /* Highest bus number behind the bridge */
 
#define PCI_SEC_LATENCY_TIMER   0x1b /* Latency timer for secondary interface */
 
#define PCI_IO_BASE   0x1c /* I/O range behind the bridge */
 
#define PCI_IO_LIMIT   0x1d
 
#define PCI_IO_RANGE_TYPE_MASK   0x0fUL /* I/O bridging type */
 
#define PCI_IO_RANGE_TYPE_16   0x00
 
#define PCI_IO_RANGE_TYPE_32   0x01
 
#define PCI_IO_RANGE_MASK   (~0x0fUL) /* Standard 4K I/O windows */
 
#define PCI_IO_1K_RANGE_MASK   (~0x03UL) /* Intel 1K I/O windows */
 
#define PCI_SEC_STATUS   0x1e /* Secondary status register, only bit 14 used */
 
#define PCI_MEMORY_BASE   0x20 /* Memory range behind */
 
#define PCI_MEMORY_LIMIT   0x22
 
#define PCI_MEMORY_RANGE_TYPE_MASK   0x0fUL
 
#define PCI_MEMORY_RANGE_MASK   (~0x0fUL)
 
#define PCI_PREF_MEMORY_BASE   0x24 /* Prefetchable memory range behind */
 
#define PCI_PREF_MEMORY_LIMIT   0x26
 
#define PCI_PREF_RANGE_TYPE_MASK   0x0fUL
 
#define PCI_PREF_RANGE_TYPE_32   0x00
 
#define PCI_PREF_RANGE_TYPE_64   0x01
 
#define PCI_PREF_RANGE_MASK   (~0x0fUL)
 
#define PCI_PREF_BASE_UPPER32   0x28 /* Upper half of prefetchable memory range */
 
#define PCI_PREF_LIMIT_UPPER32   0x2c
 
#define PCI_IO_BASE_UPPER16   0x30 /* Upper half of I/O addresses */
 
#define PCI_IO_LIMIT_UPPER16   0x32
 
#define PCI_ROM_ADDRESS1   0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
 
#define PCI_BRIDGE_CONTROL   0x3e
 
#define PCI_BRIDGE_CTL_PARITY   0x01 /* Enable parity detection on secondary interface */
 
#define PCI_BRIDGE_CTL_SERR   0x02 /* The same for SERR forwarding */
 
#define PCI_BRIDGE_CTL_ISA   0x04 /* Enable ISA mode */
 
#define PCI_BRIDGE_CTL_VGA   0x08 /* Forward VGA addresses */
 
#define PCI_BRIDGE_CTL_MASTER_ABORT   0x20 /* Report master aborts */
 
#define PCI_BRIDGE_CTL_BUS_RESET   0x40 /* Secondary bus reset */
 
#define PCI_BRIDGE_CTL_FAST_BACK   0x80 /* Fast Back2Back enabled on secondary interface */
 
#define PCI_CB_CAPABILITY_LIST   0x14
 
#define PCI_CB_SEC_STATUS   0x16 /* Secondary status */
 
#define PCI_CB_PRIMARY_BUS   0x18 /* PCI bus number */
 
#define PCI_CB_CARD_BUS   0x19 /* CardBus bus number */
 
#define PCI_CB_SUBORDINATE_BUS   0x1a /* Subordinate bus number */
 
#define PCI_CB_LATENCY_TIMER   0x1b /* CardBus latency timer */
 
#define PCI_CB_MEMORY_BASE_0   0x1c
 
#define PCI_CB_MEMORY_LIMIT_0   0x20
 
#define PCI_CB_MEMORY_BASE_1   0x24
 
#define PCI_CB_MEMORY_LIMIT_1   0x28
 
#define PCI_CB_IO_BASE_0   0x2c
 
#define PCI_CB_IO_BASE_0_HI   0x2e
 
#define PCI_CB_IO_LIMIT_0   0x30
 
#define PCI_CB_IO_LIMIT_0_HI   0x32
 
#define PCI_CB_IO_BASE_1   0x34
 
#define PCI_CB_IO_BASE_1_HI   0x36
 
#define PCI_CB_IO_LIMIT_1   0x38
 
#define PCI_CB_IO_LIMIT_1_HI   0x3a
 
#define PCI_CB_IO_RANGE_MASK   (~0x03UL)
 
#define PCI_CB_BRIDGE_CONTROL   0x3e
 
#define PCI_CB_BRIDGE_CTL_PARITY   0x01 /* Similar to standard bridge control register */
 
#define PCI_CB_BRIDGE_CTL_SERR   0x02
 
#define PCI_CB_BRIDGE_CTL_ISA   0x04
 
#define PCI_CB_BRIDGE_CTL_VGA   0x08
 
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT   0x20
 
#define PCI_CB_BRIDGE_CTL_CB_RESET   0x40 /* CardBus reset */
 
#define PCI_CB_BRIDGE_CTL_16BIT_INT   0x80 /* Enable interrupt for 16-bit cards */
 
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0   0x100 /* Prefetch enable for both memory regions */
 
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1   0x200
 
#define PCI_CB_BRIDGE_CTL_POST_WRITES   0x400
 
#define PCI_CB_SUBSYSTEM_VENDOR_ID   0x40
 
#define PCI_CB_SUBSYSTEM_ID   0x42
 
#define PCI_CB_LEGACY_MODE_BASE   0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
 
#define PCI_CAP_LIST_ID   0 /* Capability ID */
 
#define PCI_CAP_ID_PM   0x01 /* Power Management */
 
#define PCI_CAP_ID_AGP   0x02 /* Accelerated Graphics Port */
 
#define PCI_CAP_ID_VPD   0x03 /* Vital Product Data */
 
#define PCI_CAP_ID_SLOTID   0x04 /* Slot Identification */
 
#define PCI_CAP_ID_MSI   0x05 /* Message Signalled Interrupts */
 
#define PCI_CAP_ID_CHSWP   0x06 /* CompactPCI HotSwap */
 
#define PCI_CAP_ID_PCIX   0x07 /* PCI-X */
 
#define PCI_CAP_ID_HT   0x08 /* HyperTransport */
 
#define PCI_CAP_ID_VNDR   0x09 /* Vendor specific */
 
#define PCI_CAP_ID_DBG   0x0A /* Debug port */
 
#define PCI_CAP_ID_CCRC   0x0B /* CompactPCI Central Resource Control */
 
#define PCI_CAP_ID_SHPC   0x0C /* PCI Standard Hot-Plug Controller */
 
#define PCI_CAP_ID_SSVID   0x0D /* Bridge subsystem vendor/device ID */
 
#define PCI_CAP_ID_AGP3   0x0E /* AGP Target PCI-PCI bridge */
 
#define PCI_CAP_ID_SECDEV   0x0F /* Secure Device */
 
#define PCI_CAP_ID_EXP   0x10 /* PCI Express */
 
#define PCI_CAP_ID_MSIX   0x11 /* MSI-X */
 
#define PCI_CAP_ID_SATA   0x12 /* SATA Data/Index Conf. */
 
#define PCI_CAP_ID_AF   0x13 /* PCI Advanced Features */
 
#define PCI_CAP_ID_MAX   PCI_CAP_ID_AF
 
#define PCI_CAP_LIST_NEXT   1 /* Next capability in the list */
 
#define PCI_CAP_FLAGS   2 /* Capability defined flags (16 bits) */
 
#define PCI_CAP_SIZEOF   4
 
#define PCI_PM_PMC   2 /* PM Capabilities Register */
 
#define PCI_PM_CAP_VER_MASK   0x0007 /* Version */
 
#define PCI_PM_CAP_PME_CLOCK   0x0008 /* PME clock required */
 
#define PCI_PM_CAP_RESERVED   0x0010 /* Reserved field */
 
#define PCI_PM_CAP_DSI   0x0020 /* Device specific initialization */
 
#define PCI_PM_CAP_AUX_POWER   0x01C0 /* Auxiliary power support mask */
 
#define PCI_PM_CAP_D1   0x0200 /* D1 power state support */
 
#define PCI_PM_CAP_D2   0x0400 /* D2 power state support */
 
#define PCI_PM_CAP_PME   0x0800 /* PME pin supported */
 
#define PCI_PM_CAP_PME_MASK   0xF800 /* PME Mask of all supported states */
 
#define PCI_PM_CAP_PME_D0   0x0800 /* PME# from D0 */
 
#define PCI_PM_CAP_PME_D1   0x1000 /* PME# from D1 */
 
#define PCI_PM_CAP_PME_D2   0x2000 /* PME# from D2 */
 
#define PCI_PM_CAP_PME_D3   0x4000 /* PME# from D3 (hot) */
 
#define PCI_PM_CAP_PME_D3cold   0x8000 /* PME# from D3 (cold) */
 
#define PCI_PM_CAP_PME_SHIFT   11 /* Start of the PME Mask in PMC */
 
#define PCI_PM_CTRL   4 /* PM control and status register */
 
#define PCI_PM_CTRL_STATE_MASK   0x0003 /* Current power state (D0 to D3) */
 
#define PCI_PM_CTRL_NO_SOFT_RESET   0x0008 /* No reset for D3hot->D0 */
 
#define PCI_PM_CTRL_PME_ENABLE   0x0100 /* PME pin enable */
 
#define PCI_PM_CTRL_DATA_SEL_MASK   0x1e00 /* Data select (??) */
 
#define PCI_PM_CTRL_DATA_SCALE_MASK   0x6000 /* Data scale (??) */
 
#define PCI_PM_CTRL_PME_STATUS   0x8000 /* PME pin status */
 
#define PCI_PM_PPB_EXTENSIONS   6 /* PPB support extensions (??) */
 
#define PCI_PM_PPB_B2_B3   0x40 /* Stop clock when in D3hot (??) */
 
#define PCI_PM_BPCC_ENABLE   0x80 /* Bus power/clock control enable (??) */
 
#define PCI_PM_DATA_REGISTER   7 /* (??) */
 
#define PCI_PM_SIZEOF   8
 
#define PCI_AGP_VERSION   2 /* BCD version number */
 
#define PCI_AGP_RFU   3 /* Rest of capability flags */
 
#define PCI_AGP_STATUS   4 /* Status register */
 
#define PCI_AGP_STATUS_RQ_MASK   0xff000000 /* Maximum number of requests - 1 */
 
#define PCI_AGP_STATUS_SBA   0x0200 /* Sideband addressing supported */
 
#define PCI_AGP_STATUS_64BIT   0x0020 /* 64-bit addressing supported */
 
#define PCI_AGP_STATUS_FW   0x0010 /* FW transfers supported */
 
#define PCI_AGP_STATUS_RATE4   0x0004 /* 4x transfer rate supported */
 
#define PCI_AGP_STATUS_RATE2   0x0002 /* 2x transfer rate supported */
 
#define PCI_AGP_STATUS_RATE1   0x0001 /* 1x transfer rate supported */
 
#define PCI_AGP_COMMAND   8 /* Control register */
 
#define PCI_AGP_COMMAND_RQ_MASK   0xff000000 /* Master: Maximum number of requests */
 
#define PCI_AGP_COMMAND_SBA   0x0200 /* Sideband addressing enabled */
 
#define PCI_AGP_COMMAND_AGP   0x0100 /* Allow processing of AGP transactions */
 
#define PCI_AGP_COMMAND_64BIT   0x0020 /* Allow processing of 64-bit addresses */
 
#define PCI_AGP_COMMAND_FW   0x0010 /* Force FW transfers */
 
#define PCI_AGP_COMMAND_RATE4   0x0004 /* Use 4x rate */
 
#define PCI_AGP_COMMAND_RATE2   0x0002 /* Use 2x rate */
 
#define PCI_AGP_COMMAND_RATE1   0x0001 /* Use 1x rate */
 
#define PCI_AGP_SIZEOF   12
 
#define PCI_VPD_ADDR   2 /* Address to access (15 bits!) */
 
#define PCI_VPD_ADDR_MASK   0x7fff /* Address mask */
 
#define PCI_VPD_ADDR_F   0x8000 /* Write 0, 1 indicates completion */
 
#define PCI_VPD_DATA   4 /* 32-bits of data returned here */
 
#define PCI_CAP_VPD_SIZEOF   8
 
#define PCI_SID_ESR   2 /* Expansion Slot Register */
 
#define PCI_SID_ESR_NSLOTS   0x1f /* Number of expansion slots available */
 
#define PCI_SID_ESR_FIC   0x20 /* First In Chassis Flag */
 
#define PCI_SID_CHASSIS_NR   3 /* Chassis Number */
 
#define PCI_MSI_FLAGS   2 /* Various flags */
 
#define PCI_MSI_FLAGS_64BIT   0x80 /* 64-bit addresses allowed */
 
#define PCI_MSI_FLAGS_QSIZE   0x70 /* Message queue size configured */
 
#define PCI_MSI_FLAGS_QMASK   0x0e /* Maximum queue size available */
 
#define PCI_MSI_FLAGS_ENABLE   0x01 /* MSI feature enabled */
 
#define PCI_MSI_FLAGS_MASKBIT   0x100 /* 64-bit mask bits allowed */
 
#define PCI_MSI_RFU   3 /* Rest of capability flags */
 
#define PCI_MSI_ADDRESS_LO   4 /* Lower 32 bits */
 
#define PCI_MSI_ADDRESS_HI   8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 
#define PCI_MSI_DATA_32   8 /* 16 bits of data for 32-bit devices */
 
#define PCI_MSI_MASK_32   12 /* Mask bits register for 32-bit devices */
 
#define PCI_MSI_PENDING_32   16 /* Pending intrs for 32-bit devices */
 
#define PCI_MSI_DATA_64   12 /* 16 bits of data for 64-bit devices */
 
#define PCI_MSI_MASK_64   16 /* Mask bits register for 64-bit devices */
 
#define PCI_MSI_PENDING_64   20 /* Pending intrs for 64-bit devices */
 
#define PCI_MSIX_FLAGS   2
 
#define PCI_MSIX_FLAGS_QSIZE   0x7FF
 
#define PCI_MSIX_FLAGS_ENABLE   (1 << 15)
 
#define PCI_MSIX_FLAGS_MASKALL   (1 << 14)
 
#define PCI_MSIX_TABLE   4
 
#define PCI_MSIX_PBA   8
 
#define PCI_MSIX_FLAGS_BIRMASK   (7 << 0)
 
#define PCI_CAP_MSIX_SIZEOF   12 /* size of MSIX registers */
 
#define PCI_MSIX_ENTRY_SIZE   16
 
#define PCI_MSIX_ENTRY_LOWER_ADDR   0
 
#define PCI_MSIX_ENTRY_UPPER_ADDR   4
 
#define PCI_MSIX_ENTRY_DATA   8
 
#define PCI_MSIX_ENTRY_VECTOR_CTRL   12
 
#define PCI_MSIX_ENTRY_CTRL_MASKBIT   1
 
#define PCI_CHSWP_CSR   2 /* Control and Status Register */
 
#define PCI_CHSWP_DHA   0x01 /* Device Hiding Arm */
 
#define PCI_CHSWP_EIM   0x02 /* ENUM# Signal Mask */
 
#define PCI_CHSWP_PIE   0x04 /* Pending Insert or Extract */
 
#define PCI_CHSWP_LOO   0x08 /* LED On / Off */
 
#define PCI_CHSWP_PI   0x30 /* Programming Interface */
 
#define PCI_CHSWP_EXT   0x40 /* ENUM# status - extraction */
 
#define PCI_CHSWP_INS   0x80 /* ENUM# status - insertion */
 
#define PCI_AF_LENGTH   2
 
#define PCI_AF_CAP   3
 
#define PCI_AF_CAP_TP   0x01
 
#define PCI_AF_CAP_FLR   0x02
 
#define PCI_AF_CTRL   4
 
#define PCI_AF_CTRL_FLR   0x01
 
#define PCI_AF_STATUS   5
 
#define PCI_AF_STATUS_TP   0x01
 
#define PCI_CAP_AF_SIZEOF   6 /* size of AF registers */
 
#define PCI_X_CMD   2 /* Modes & Features */
 
#define PCI_X_CMD_DPERR_E   0x0001 /* Data Parity Error Recovery Enable */
 
#define PCI_X_CMD_ERO   0x0002 /* Enable Relaxed Ordering */
 
#define PCI_X_CMD_READ_512   0x0000 /* 512 byte maximum read byte count */
 
#define PCI_X_CMD_READ_1K   0x0004 /* 1Kbyte maximum read byte count */
 
#define PCI_X_CMD_READ_2K   0x0008 /* 2Kbyte maximum read byte count */
 
#define PCI_X_CMD_READ_4K   0x000c /* 4Kbyte maximum read byte count */
 
#define PCI_X_CMD_MAX_READ   0x000c /* Max Memory Read Byte Count */
 
#define PCI_X_CMD_SPLIT_1   0x0000 /* Max 1 */
 
#define PCI_X_CMD_SPLIT_2   0x0010 /* Max 2 */
 
#define PCI_X_CMD_SPLIT_3   0x0020 /* Max 3 */
 
#define PCI_X_CMD_SPLIT_4   0x0030 /* Max 4 */
 
#define PCI_X_CMD_SPLIT_8   0x0040 /* Max 8 */
 
#define PCI_X_CMD_SPLIT_12   0x0050 /* Max 12 */
 
#define PCI_X_CMD_SPLIT_16   0x0060 /* Max 16 */
 
#define PCI_X_CMD_SPLIT_32   0x0070 /* Max 32 */
 
#define PCI_X_CMD_MAX_SPLIT   0x0070 /* Max Outstanding Split Transactions */
 
#define PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
 
#define PCI_X_STATUS   4 /* PCI-X capabilities */
 
#define PCI_X_STATUS_DEVFN   0x000000ff /* A copy of devfn */
 
#define PCI_X_STATUS_BUS   0x0000ff00 /* A copy of bus nr */
 
#define PCI_X_STATUS_64BIT   0x00010000 /* 64-bit device */
 
#define PCI_X_STATUS_133MHZ   0x00020000 /* 133 MHz capable */
 
#define PCI_X_STATUS_SPL_DISC   0x00040000 /* Split Completion Discarded */
 
#define PCI_X_STATUS_UNX_SPL   0x00080000 /* Unexpected Split Completion */
 
#define PCI_X_STATUS_COMPLEX   0x00100000 /* Device Complexity */
 
#define PCI_X_STATUS_MAX_READ   0x00600000 /* Designed Max Memory Read Count */
 
#define PCI_X_STATUS_MAX_SPLIT   0x03800000 /* Designed Max Outstanding Split Transactions */
 
#define PCI_X_STATUS_MAX_CUM   0x1c000000 /* Designed Max Cumulative Read Size */
 
#define PCI_X_STATUS_SPL_ERR   0x20000000 /* Rcvd Split Completion Error Msg */
 
#define PCI_X_STATUS_266MHZ   0x40000000 /* 266 MHz capable */
 
#define PCI_X_STATUS_533MHZ   0x80000000 /* 533 MHz capable */
 
#define PCI_X_ECC_CSR   8 /* ECC control and status */
 
#define PCI_CAP_PCIX_SIZEOF_V0   8 /* size of registers for Version 0 */
 
#define PCI_CAP_PCIX_SIZEOF_V1   24 /* size for Version 1 */
 
#define PCI_CAP_PCIX_SIZEOF_V2   PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */
 
#define PCI_SSVID_VENDOR_ID   4 /* PCI-Bridge subsystem vendor id register */
 
#define PCI_SSVID_DEVICE_ID   6 /* PCI-Bridge subsystem device id register */
 
#define PCI_EXP_FLAGS   2 /* Capabilities register */
 
#define PCI_EXP_FLAGS_VERS   0x000f /* Capability version */
 
#define PCI_EXP_FLAGS_TYPE   0x00f0 /* Device/Port type */
 
#define PCI_EXP_TYPE_ENDPOINT   0x0 /* Express Endpoint */
 
#define PCI_EXP_TYPE_LEG_END   0x1 /* Legacy Endpoint */
 
#define PCI_EXP_TYPE_ROOT_PORT   0x4 /* Root Port */
 
#define PCI_EXP_TYPE_UPSTREAM   0x5 /* Upstream Port */
 
#define PCI_EXP_TYPE_DOWNSTREAM   0x6 /* Downstream Port */
 
#define PCI_EXP_TYPE_PCI_BRIDGE   0x7 /* PCI/PCI-X Bridge */
 
#define PCI_EXP_TYPE_PCIE_BRIDGE   0x8 /* PCI/PCI-X to PCIE Bridge */
 
#define PCI_EXP_TYPE_RC_END   0x9 /* Root Complex Integrated Endpoint */
 
#define PCI_EXP_TYPE_RC_EC   0xa /* Root Complex Event Collector */
 
#define PCI_EXP_FLAGS_SLOT   0x0100 /* Slot implemented */
 
#define PCI_EXP_FLAGS_IRQ   0x3e00 /* Interrupt message number */
 
#define PCI_EXP_DEVCAP   4 /* Device capabilities */
 
#define PCI_EXP_DEVCAP_PAYLOAD   0x07 /* Max_Payload_Size */
 
#define PCI_EXP_DEVCAP_PHANTOM   0x18 /* Phantom functions */
 
#define PCI_EXP_DEVCAP_EXT_TAG   0x20 /* Extended tags */
 
#define PCI_EXP_DEVCAP_L0S   0x1c0 /* L0s Acceptable Latency */
 
#define PCI_EXP_DEVCAP_L1   0xe00 /* L1 Acceptable Latency */
 
#define PCI_EXP_DEVCAP_ATN_BUT   0x1000 /* Attention Button Present */
 
#define PCI_EXP_DEVCAP_ATN_IND   0x2000 /* Attention Indicator Present */
 
#define PCI_EXP_DEVCAP_PWR_IND   0x4000 /* Power Indicator Present */
 
#define PCI_EXP_DEVCAP_RBER   0x8000 /* Role-Based Error Reporting */
 
#define PCI_EXP_DEVCAP_PWR_VAL   0x3fc0000 /* Slot Power Limit Value */
 
#define PCI_EXP_DEVCAP_PWR_SCL   0xc000000 /* Slot Power Limit Scale */
 
#define PCI_EXP_DEVCAP_FLR   0x10000000 /* Function Level Reset */
 
#define PCI_EXP_DEVCTL   8 /* Device Control */
 
#define PCI_EXP_DEVCTL_CERE   0x0001 /* Correctable Error Reporting En. */
 
#define PCI_EXP_DEVCTL_NFERE   0x0002 /* Non-Fatal Error Reporting Enable */
 
#define PCI_EXP_DEVCTL_FERE   0x0004 /* Fatal Error Reporting Enable */
 
#define PCI_EXP_DEVCTL_URRE   0x0008 /* Unsupported Request Reporting En. */
 
#define PCI_EXP_DEVCTL_RELAX_EN   0x0010 /* Enable relaxed ordering */
 
#define PCI_EXP_DEVCTL_PAYLOAD   0x00e0 /* Max_Payload_Size */
 
#define PCI_EXP_DEVCTL_EXT_TAG   0x0100 /* Extended Tag Field Enable */
 
#define PCI_EXP_DEVCTL_PHANTOM   0x0200 /* Phantom Functions Enable */
 
#define PCI_EXP_DEVCTL_AUX_PME   0x0400 /* Auxiliary Power PM Enable */
 
#define PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800 /* Enable No Snoop */
 
#define PCI_EXP_DEVCTL_READRQ   0x7000 /* Max_Read_Request_Size */
 
#define PCI_EXP_DEVCTL_BCR_FLR   0x8000 /* Bridge Configuration Retry / FLR */
 
#define PCI_EXP_DEVSTA   10 /* Device Status */
 
#define PCI_EXP_DEVSTA_CED   0x01 /* Correctable Error Detected */
 
#define PCI_EXP_DEVSTA_NFED   0x02 /* Non-Fatal Error Detected */
 
#define PCI_EXP_DEVSTA_FED   0x04 /* Fatal Error Detected */
 
#define PCI_EXP_DEVSTA_URD   0x08 /* Unsupported Request Detected */
 
#define PCI_EXP_DEVSTA_AUXPD   0x10 /* AUX Power Detected */
 
#define PCI_EXP_DEVSTA_TRPND   0x20 /* Transactions Pending */
 
#define PCI_EXP_LNKCAP   12 /* Link Capabilities */
 
#define PCI_EXP_LNKCAP_SLS   0x0000000f /* Supported Link Speeds */
 
#define PCI_EXP_LNKCAP_MLW   0x000003f0 /* Maximum Link Width */
 
#define PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
 
#define PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
 
#define PCI_EXP_LNKCAP_L1EL   0x00038000 /* L1 Exit Latency */
 
#define PCI_EXP_LNKCAP_CLKPM   0x00040000 /* L1 Clock Power Management */
 
#define PCI_EXP_LNKCAP_SDERC   0x00080000 /* Surprise Down Error Reporting Capable */
 
#define PCI_EXP_LNKCAP_DLLLARC   0x00100000 /* Data Link Layer Link Active Reporting Capable */
 
#define PCI_EXP_LNKCAP_LBNC   0x00200000 /* Link Bandwidth Notification Capability */
 
#define PCI_EXP_LNKCAP_PN   0xff000000 /* Port Number */
 
#define PCI_EXP_LNKCTL   16 /* Link Control */
 
#define PCI_EXP_LNKCTL_ASPMC   0x0003 /* ASPM Control */
 
#define PCI_EXP_LNKCTL_RCB   0x0008 /* Read Completion Boundary */
 
#define PCI_EXP_LNKCTL_LD   0x0010 /* Link Disable */
 
#define PCI_EXP_LNKCTL_RL   0x0020 /* Retrain Link */
 
#define PCI_EXP_LNKCTL_CCC   0x0040 /* Common Clock Configuration */
 
#define PCI_EXP_LNKCTL_ES   0x0080 /* Extended Synch */
 
#define PCI_EXP_LNKCTL_CLKREQ_EN   0x100 /* Enable clkreq */
 
#define PCI_EXP_LNKCTL_HAWD   0x0200 /* Hardware Autonomous Width Disable */
 
#define PCI_EXP_LNKCTL_LBMIE   0x0400 /* Link Bandwidth Management Interrupt Enable */
 
#define PCI_EXP_LNKCTL_LABIE   0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
 
#define PCI_EXP_LNKSTA   18 /* Link Status */
 
#define PCI_EXP_LNKSTA_CLS   0x000f /* Current Link Speed */
 
#define PCI_EXP_LNKSTA_CLS_2_5GB   0x01 /* Current Link Speed 2.5GT/s */
 
#define PCI_EXP_LNKSTA_CLS_5_0GB   0x02 /* Current Link Speed 5.0GT/s */
 
#define PCI_EXP_LNKSTA_NLW   0x03f0 /* Nogotiated Link Width */
 
#define PCI_EXP_LNKSTA_NLW_SHIFT   4 /* start of NLW mask in link status */
 
#define PCI_EXP_LNKSTA_LT   0x0800 /* Link Training */
 
#define PCI_EXP_LNKSTA_SLC   0x1000 /* Slot Clock Configuration */
 
#define PCI_EXP_LNKSTA_DLLLA   0x2000 /* Data Link Layer Link Active */
 
#define PCI_EXP_LNKSTA_LBMS   0x4000 /* Link Bandwidth Management Status */
 
#define PCI_EXP_LNKSTA_LABS   0x8000 /* Link Autonomous Bandwidth Status */
 
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1   20 /* v1 endpoints end here */
 
#define PCI_EXP_SLTCAP   20 /* Slot Capabilities */
 
#define PCI_EXP_SLTCAP_ABP   0x00000001 /* Attention Button Present */
 
#define PCI_EXP_SLTCAP_PCP   0x00000002 /* Power Controller Present */
 
#define PCI_EXP_SLTCAP_MRLSP   0x00000004 /* MRL Sensor Present */
 
#define PCI_EXP_SLTCAP_AIP   0x00000008 /* Attention Indicator Present */
 
#define PCI_EXP_SLTCAP_PIP   0x00000010 /* Power Indicator Present */
 
#define PCI_EXP_SLTCAP_HPS   0x00000020 /* Hot-Plug Surprise */
 
#define PCI_EXP_SLTCAP_HPC   0x00000040 /* Hot-Plug Capable */
 
#define PCI_EXP_SLTCAP_SPLV   0x00007f80 /* Slot Power Limit Value */
 
#define PCI_EXP_SLTCAP_SPLS   0x00018000 /* Slot Power Limit Scale */
 
#define PCI_EXP_SLTCAP_EIP   0x00020000 /* Electromechanical Interlock Present */
 
#define PCI_EXP_SLTCAP_NCCS   0x00040000 /* No Command Completed Support */
 
#define PCI_EXP_SLTCAP_PSN   0xfff80000 /* Physical Slot Number */
 
#define PCI_EXP_SLTCTL   24 /* Slot Control */
 
#define PCI_EXP_SLTCTL_ABPE   0x0001 /* Attention Button Pressed Enable */
 
#define PCI_EXP_SLTCTL_PFDE   0x0002 /* Power Fault Detected Enable */
 
#define PCI_EXP_SLTCTL_MRLSCE   0x0004 /* MRL Sensor Changed Enable */
 
#define PCI_EXP_SLTCTL_PDCE   0x0008 /* Presence Detect Changed Enable */
 
#define PCI_EXP_SLTCTL_CCIE   0x0010 /* Command Completed Interrupt Enable */
 
#define PCI_EXP_SLTCTL_HPIE   0x0020 /* Hot-Plug Interrupt Enable */
 
#define PCI_EXP_SLTCTL_AIC   0x00c0 /* Attention Indicator Control */
 
#define PCI_EXP_SLTCTL_PIC   0x0300 /* Power Indicator Control */
 
#define PCI_EXP_SLTCTL_PCC   0x0400 /* Power Controller Control */
 
#define PCI_EXP_SLTCTL_EIC   0x0800 /* Electromechanical Interlock Control */
 
#define PCI_EXP_SLTCTL_DLLSCE   0x1000 /* Data Link Layer State Changed Enable */
 
#define PCI_EXP_SLTSTA   26 /* Slot Status */
 
#define PCI_EXP_SLTSTA_ABP   0x0001 /* Attention Button Pressed */
 
#define PCI_EXP_SLTSTA_PFD   0x0002 /* Power Fault Detected */
 
#define PCI_EXP_SLTSTA_MRLSC   0x0004 /* MRL Sensor Changed */
 
#define PCI_EXP_SLTSTA_PDC   0x0008 /* Presence Detect Changed */
 
#define PCI_EXP_SLTSTA_CC   0x0010 /* Command Completed */
 
#define PCI_EXP_SLTSTA_MRLSS   0x0020 /* MRL Sensor State */
 
#define PCI_EXP_SLTSTA_PDS   0x0040 /* Presence Detect State */
 
#define PCI_EXP_SLTSTA_EIS   0x0080 /* Electromechanical Interlock Status */
 
#define PCI_EXP_SLTSTA_DLLSC   0x0100 /* Data Link Layer State Changed */
 
#define PCI_EXP_RTCTL   28 /* Root Control */
 
#define PCI_EXP_RTCTL_SECEE   0x01 /* System Error on Correctable Error */
 
#define PCI_EXP_RTCTL_SENFEE   0x02 /* System Error on Non-Fatal Error */
 
#define PCI_EXP_RTCTL_SEFEE   0x04 /* System Error on Fatal Error */
 
#define PCI_EXP_RTCTL_PMEIE   0x08 /* PME Interrupt Enable */
 
#define PCI_EXP_RTCTL_CRSSVE   0x10 /* CRS Software Visibility Enable */
 
#define PCI_EXP_RTCAP   30 /* Root Capabilities */
 
#define PCI_EXP_RTSTA   32 /* Root Status */
 
#define PCI_EXP_RTSTA_PME   0x10000 /* PME status */
 
#define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
 
#define PCI_EXP_DEVCAP2   36 /* Device Capabilities 2 */
 
#define PCI_EXP_DEVCAP2_ARI   0x20 /* Alternative Routing-ID */
 
#define PCI_EXP_DEVCAP2_LTR   0x800 /* Latency tolerance reporting */
 
#define PCI_EXP_OBFF_MASK   0xc0000 /* OBFF support mechanism */
 
#define PCI_EXP_OBFF_MSG   0x40000 /* New message signaling */
 
#define PCI_EXP_OBFF_WAKE   0x80000 /* Re-use WAKE# for OBFF */
 
#define PCI_EXP_DEVCTL2   40 /* Device Control 2 */
 
#define PCI_EXP_DEVCTL2_ARI   0x20 /* Alternative Routing-ID */
 
#define PCI_EXP_IDO_REQ_EN   0x100 /* ID-based ordering request enable */
 
#define PCI_EXP_IDO_CMP_EN   0x200 /* ID-based ordering completion enable */
 
#define PCI_EXP_LTR_EN   0x400 /* Latency tolerance reporting */
 
#define PCI_EXP_OBFF_MSGA_EN   0x2000 /* OBFF enable with Message type A */
 
#define PCI_EXP_OBFF_MSGB_EN   0x4000 /* OBFF enable with Message type B */
 
#define PCI_EXP_OBFF_WAKE_EN   0x6000 /* OBFF using WAKE# signaling */
 
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2   44 /* v2 endpoints end here */
 
#define PCI_EXP_LNKCAP2   44 /* Link Capability 2 */
 
#define PCI_EXP_LNKCAP2_SLS_2_5GB   0x01 /* Current Link Speed 2.5GT/s */
 
#define PCI_EXP_LNKCAP2_SLS_5_0GB   0x02 /* Current Link Speed 5.0GT/s */
 
#define PCI_EXP_LNKCAP2_SLS_8_0GB   0x04 /* Current Link Speed 8.0GT/s */
 
#define PCI_EXP_LNKCAP2_CROSSLINK   0x100 /* Crosslink supported */
 
#define PCI_EXP_LNKCTL2   48 /* Link Control 2 */
 
#define PCI_EXP_LNKSTA2   50 /* Link Status 2 */
 
#define PCI_EXP_SLTCTL2   56 /* Slot Control 2 */
 
#define PCI_EXT_CAP_ID(header)   (header & 0x0000ffff)
 
#define PCI_EXT_CAP_VER(header)   ((header >> 16) & 0xf)
 
#define PCI_EXT_CAP_NEXT(header)   ((header >> 20) & 0xffc)
 
#define PCI_EXT_CAP_ID_ERR   0x01 /* Advanced Error Reporting */
 
#define PCI_EXT_CAP_ID_VC   0x02 /* Virtual Channel Capability */
 
#define PCI_EXT_CAP_ID_DSN   0x03 /* Device Serial Number */
 
#define PCI_EXT_CAP_ID_PWR   0x04 /* Power Budgeting */
 
#define PCI_EXT_CAP_ID_RCLD   0x05 /* Root Complex Link Declaration */
 
#define PCI_EXT_CAP_ID_RCILC   0x06 /* Root Complex Internal Link Control */
 
#define PCI_EXT_CAP_ID_RCEC   0x07 /* Root Complex Event Collector */
 
#define PCI_EXT_CAP_ID_MFVC   0x08 /* Multi-Function VC Capability */
 
#define PCI_EXT_CAP_ID_VC9   0x09 /* same as _VC */
 
#define PCI_EXT_CAP_ID_RCRB   0x0A /* Root Complex RB? */
 
#define PCI_EXT_CAP_ID_VNDR   0x0B /* Vendor Specific */
 
#define PCI_EXT_CAP_ID_CAC   0x0C /* Config Access - obsolete */
 
#define PCI_EXT_CAP_ID_ACS   0x0D /* Access Control Services */
 
#define PCI_EXT_CAP_ID_ARI   0x0E /* Alternate Routing ID */
 
#define PCI_EXT_CAP_ID_ATS   0x0F /* Address Translation Services */
 
#define PCI_EXT_CAP_ID_SRIOV   0x10 /* Single Root I/O Virtualization */
 
#define PCI_EXT_CAP_ID_MRIOV   0x11 /* Multi Root I/O Virtualization */
 
#define PCI_EXT_CAP_ID_MCAST   0x12 /* Multicast */
 
#define PCI_EXT_CAP_ID_PRI   0x13 /* Page Request Interface */
 
#define PCI_EXT_CAP_ID_AMD_XXX   0x14 /* reserved for AMD */
 
#define PCI_EXT_CAP_ID_REBAR   0x15 /* resizable BAR */
 
#define PCI_EXT_CAP_ID_DPA   0x16 /* dynamic power alloc */
 
#define PCI_EXT_CAP_ID_TPH   0x17 /* TPH request */
 
#define PCI_EXT_CAP_ID_LTR   0x18 /* latency tolerance reporting */
 
#define PCI_EXT_CAP_ID_SECPCI   0x19 /* Secondary PCIe */
 
#define PCI_EXT_CAP_ID_PMUX   0x1A /* Protocol Multiplexing */
 
#define PCI_EXT_CAP_ID_PASID   0x1B /* Process Address Space ID */
 
#define PCI_EXT_CAP_ID_MAX   PCI_EXT_CAP_ID_PASID
 
#define PCI_EXT_CAP_DSN_SIZEOF   12
 
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF   40
 
#define PCI_ERR_UNCOR_STATUS   4 /* Uncorrectable Error Status */
 
#define PCI_ERR_UNC_TRAIN   0x00000001 /* Training */
 
#define PCI_ERR_UNC_DLP   0x00000010 /* Data Link Protocol */
 
#define PCI_ERR_UNC_SURPDN   0x00000020 /* Surprise Down */
 
#define PCI_ERR_UNC_POISON_TLP   0x00001000 /* Poisoned TLP */
 
#define PCI_ERR_UNC_FCP   0x00002000 /* Flow Control Protocol */
 
#define PCI_ERR_UNC_COMP_TIME   0x00004000 /* Completion Timeout */
 
#define PCI_ERR_UNC_COMP_ABORT   0x00008000 /* Completer Abort */
 
#define PCI_ERR_UNC_UNX_COMP   0x00010000 /* Unexpected Completion */
 
#define PCI_ERR_UNC_RX_OVER   0x00020000 /* Receiver Overflow */
 
#define PCI_ERR_UNC_MALF_TLP   0x00040000 /* Malformed TLP */
 
#define PCI_ERR_UNC_ECRC   0x00080000 /* ECRC Error Status */
 
#define PCI_ERR_UNC_UNSUP   0x00100000 /* Unsupported Request */
 
#define PCI_ERR_UNC_ACSV   0x00200000 /* ACS Violation */
 
#define PCI_ERR_UNC_INTN   0x00400000 /* internal error */
 
#define PCI_ERR_UNC_MCBTLP   0x00800000 /* MC blocked TLP */
 
#define PCI_ERR_UNC_ATOMEG   0x01000000 /* Atomic egress blocked */
 
#define PCI_ERR_UNC_TLPPRE   0x02000000 /* TLP prefix blocked */
 
#define PCI_ERR_UNCOR_MASK   8 /* Uncorrectable Error Mask */
 
#define PCI_ERR_UNCOR_SEVER   12 /* Uncorrectable Error Severity */
 
#define PCI_ERR_COR_STATUS   16 /* Correctable Error Status */
 
#define PCI_ERR_COR_RCVR   0x00000001 /* Receiver Error Status */
 
#define PCI_ERR_COR_BAD_TLP   0x00000040 /* Bad TLP Status */
 
#define PCI_ERR_COR_BAD_DLLP   0x00000080 /* Bad DLLP Status */
 
#define PCI_ERR_COR_REP_ROLL   0x00000100 /* REPLAY_NUM Rollover */
 
#define PCI_ERR_COR_REP_TIMER   0x00001000 /* Replay Timer Timeout */
 
#define PCI_ERR_COR_ADV_NFAT   0x00002000 /* Advisory Non-Fatal */
 
#define PCI_ERR_COR_INTERNAL   0x00004000 /* Corrected Internal */
 
#define PCI_ERR_COR_LOG_OVER   0x00008000 /* Header Log Overflow */
 
#define PCI_ERR_COR_MASK   20 /* Correctable Error Mask */
 
#define PCI_ERR_CAP   24 /* Advanced Error Capabilities */
 
#define PCI_ERR_CAP_FEP(x)   ((x) & 31) /* First Error Pointer */
 
#define PCI_ERR_CAP_ECRC_GENC   0x00000020 /* ECRC Generation Capable */
 
#define PCI_ERR_CAP_ECRC_GENE   0x00000040 /* ECRC Generation Enable */
 
#define PCI_ERR_CAP_ECRC_CHKC   0x00000080 /* ECRC Check Capable */
 
#define PCI_ERR_CAP_ECRC_CHKE   0x00000100 /* ECRC Check Enable */
 
#define PCI_ERR_HEADER_LOG   28 /* Header Log Register (16 bytes) */
 
#define PCI_ERR_ROOT_COMMAND   44 /* Root Error Command */
 
#define PCI_ERR_ROOT_CMD_COR_EN   0x00000001
 
#define PCI_ERR_ROOT_CMD_NONFATAL_EN   0x00000002
 
#define PCI_ERR_ROOT_CMD_FATAL_EN   0x00000004
 
#define PCI_ERR_ROOT_STATUS   48
 
#define PCI_ERR_ROOT_COR_RCV   0x00000001 /* ERR_COR Received */
 
#define PCI_ERR_ROOT_MULTI_COR_RCV   0x00000002
 
#define PCI_ERR_ROOT_UNCOR_RCV   0x00000004
 
#define PCI_ERR_ROOT_MULTI_UNCOR_RCV   0x00000008
 
#define PCI_ERR_ROOT_FIRST_FATAL   0x00000010 /* First Fatal */
 
#define PCI_ERR_ROOT_NONFATAL_RCV   0x00000020 /* Non-Fatal Received */
 
#define PCI_ERR_ROOT_FATAL_RCV   0x00000040 /* Fatal Received */
 
#define PCI_ERR_ROOT_ERR_SRC   52 /* Error Source Identification */
 
#define PCI_VC_PORT_REG1   4
 
#define PCI_VC_REG1_EVCC   0x7 /* extended vc count */
 
#define PCI_VC_PORT_REG2   8
 
#define PCI_VC_REG2_32_PHASE   0x2
 
#define PCI_VC_REG2_64_PHASE   0x4
 
#define PCI_VC_REG2_128_PHASE   0x8
 
#define PCI_VC_PORT_CTRL   12
 
#define PCI_VC_PORT_STATUS   14
 
#define PCI_VC_RES_CAP   16
 
#define PCI_VC_RES_CTRL   20
 
#define PCI_VC_RES_STATUS   26
 
#define PCI_CAP_VC_BASE_SIZEOF   0x10
 
#define PCI_CAP_VC_PER_VC_SIZEOF   0x0C
 
#define PCI_PWR_DSR   4 /* Data Select Register */
 
#define PCI_PWR_DATA   8 /* Data Register */
 
#define PCI_PWR_DATA_BASE(x)   ((x) & 0xff) /* Base Power */
 
#define PCI_PWR_DATA_SCALE(x)   (((x) >> 8) & 3) /* Data Scale */
 
#define PCI_PWR_DATA_PM_SUB(x)   (((x) >> 10) & 7) /* PM Sub State */
 
#define PCI_PWR_DATA_PM_STATE(x)   (((x) >> 13) & 3) /* PM State */
 
#define PCI_PWR_DATA_TYPE(x)   (((x) >> 15) & 7) /* Type */
 
#define PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7) /* Power Rail */
 
#define PCI_PWR_CAP   12 /* Capability */
 
#define PCI_PWR_CAP_BUDGET(x)   ((x) & 1) /* Included in system budget */
 
#define PCI_EXT_CAP_PWR_SIZEOF   16
 
#define PCI_VNDR_HEADER   4 /* Vendor-Specific Header */
 
#define PCI_VNDR_HEADER_ID(x)   ((x) & 0xffff)
 
#define PCI_VNDR_HEADER_REV(x)   (((x) >> 16) & 0xf)
 
#define PCI_VNDR_HEADER_LEN(x)   (((x) >> 20) & 0xfff)
 
#define HT_3BIT_CAP_MASK   0xE0
 
#define HT_CAPTYPE_SLAVE   0x00 /* Slave/Primary link configuration */
 
#define HT_CAPTYPE_HOST   0x20 /* Host/Secondary link configuration */
 
#define HT_5BIT_CAP_MASK   0xF8
 
#define HT_CAPTYPE_IRQ   0x80 /* IRQ Configuration */
 
#define HT_CAPTYPE_REMAPPING_40   0xA0 /* 40 bit address remapping */
 
#define HT_CAPTYPE_REMAPPING_64   0xA2 /* 64 bit address remapping */
 
#define HT_CAPTYPE_UNITID_CLUMP   0x90 /* Unit ID clumping */
 
#define HT_CAPTYPE_EXTCONF   0x98 /* Extended Configuration Space Access */
 
#define HT_CAPTYPE_MSI_MAPPING   0xA8 /* MSI Mapping Capability */
 
#define HT_MSI_FLAGS   0x02 /* Offset to flags */
 
#define HT_MSI_FLAGS_ENABLE   0x1 /* Mapping enable */
 
#define HT_MSI_FLAGS_FIXED   0x2 /* Fixed mapping only */
 
#define HT_MSI_FIXED_ADDR   0x00000000FEE00000ULL /* Fixed addr */
 
#define HT_MSI_ADDR_LO   0x04 /* Offset to low addr bits */
 
#define HT_MSI_ADDR_LO_MASK   0xFFF00000 /* Low address bit mask */
 
#define HT_MSI_ADDR_HI   0x08 /* Offset to high addr bits */
 
#define HT_CAPTYPE_DIRECT_ROUTE   0xB0 /* Direct routing configuration */
 
#define HT_CAPTYPE_VCSET   0xB8 /* Virtual Channel configuration */
 
#define HT_CAPTYPE_ERROR_RETRY   0xC0 /* Retry on error configuration */
 
#define HT_CAPTYPE_GEN3   0xD0 /* Generation 3 hypertransport configuration */
 
#define HT_CAPTYPE_PM   0xE0 /* Hypertransport powermanagement configuration */
 
#define HT_CAP_SIZEOF_LONG   28 /* slave & primary */
 
#define HT_CAP_SIZEOF_SHORT   24 /* host & secondary */
 
#define PCI_ARI_CAP   0x04 /* ARI Capability Register */
 
#define PCI_ARI_CAP_MFVC   0x0001 /* MFVC Function Groups Capability */
 
#define PCI_ARI_CAP_ACS   0x0002 /* ACS Function Groups Capability */
 
#define PCI_ARI_CAP_NFN(x)   (((x) >> 8) & 0xff) /* Next Function Number */
 
#define PCI_ARI_CTRL   0x06 /* ARI Control Register */
 
#define PCI_ARI_CTRL_MFVC   0x0001 /* MFVC Function Groups Enable */
 
#define PCI_ARI_CTRL_ACS   0x0002 /* ACS Function Groups Enable */
 
#define PCI_ARI_CTRL_FG(x)   (((x) >> 4) & 7) /* Function Group */
 
#define PCI_EXT_CAP_ARI_SIZEOF   8
 
#define PCI_ATS_CAP   0x04 /* ATS Capability Register */
 
#define PCI_ATS_CAP_QDEP(x)   ((x) & 0x1f) /* Invalidate Queue Depth */
 
#define PCI_ATS_MAX_QDEP   32 /* Max Invalidate Queue Depth */
 
#define PCI_ATS_CTRL   0x06 /* ATS Control Register */
 
#define PCI_ATS_CTRL_ENABLE   0x8000 /* ATS Enable */
 
#define PCI_ATS_CTRL_STU(x)   ((x) & 0x1f) /* Smallest Translation Unit */
 
#define PCI_ATS_MIN_STU   12 /* shift of minimum STU block */
 
#define PCI_EXT_CAP_ATS_SIZEOF   8
 
#define PCI_PRI_CTRL   0x04 /* PRI control register */
 
#define PCI_PRI_CTRL_ENABLE   0x01 /* Enable */
 
#define PCI_PRI_CTRL_RESET   0x02 /* Reset */
 
#define PCI_PRI_STATUS   0x06 /* PRI status register */
 
#define PCI_PRI_STATUS_RF   0x001 /* Response Failure */
 
#define PCI_PRI_STATUS_UPRGI   0x002 /* Unexpected PRG index */
 
#define PCI_PRI_STATUS_STOPPED   0x100 /* PRI Stopped */
 
#define PCI_PRI_MAX_REQ   0x08 /* PRI max reqs supported */
 
#define PCI_PRI_ALLOC_REQ   0x0c /* PRI max reqs allowed */
 
#define PCI_EXT_CAP_PRI_SIZEOF   16
 
#define PCI_PASID_CAP   0x04 /* PASID feature register */
 
#define PCI_PASID_CAP_EXEC   0x02 /* Exec permissions Supported */
 
#define PCI_PASID_CAP_PRIV   0x04 /* Priviledge Mode Supported */
 
#define PCI_PASID_CTRL   0x06 /* PASID control register */
 
#define PCI_PASID_CTRL_ENABLE   0x01 /* Enable bit */
 
#define PCI_PASID_CTRL_EXEC   0x02 /* Exec permissions Enable */
 
#define PCI_PASID_CTRL_PRIV   0x04 /* Priviledge Mode Enable */
 
#define PCI_EXT_CAP_PASID_SIZEOF   8
 
#define PCI_SRIOV_CAP   0x04 /* SR-IOV Capabilities */
 
#define PCI_SRIOV_CAP_VFM   0x01 /* VF Migration Capable */
 
#define PCI_SRIOV_CAP_INTR(x)   ((x) >> 21) /* Interrupt Message Number */
 
#define PCI_SRIOV_CTRL   0x08 /* SR-IOV Control */
 
#define PCI_SRIOV_CTRL_VFE   0x01 /* VF Enable */
 
#define PCI_SRIOV_CTRL_VFM   0x02 /* VF Migration Enable */
 
#define PCI_SRIOV_CTRL_INTR   0x04 /* VF Migration Interrupt Enable */
 
#define PCI_SRIOV_CTRL_MSE   0x08 /* VF Memory Space Enable */
 
#define PCI_SRIOV_CTRL_ARI   0x10 /* ARI Capable Hierarchy */
 
#define PCI_SRIOV_STATUS   0x0a /* SR-IOV Status */
 
#define PCI_SRIOV_STATUS_VFM   0x01 /* VF Migration Status */
 
#define PCI_SRIOV_INITIAL_VF   0x0c /* Initial VFs */
 
#define PCI_SRIOV_TOTAL_VF   0x0e /* Total VFs */
 
#define PCI_SRIOV_NUM_VF   0x10 /* Number of VFs */
 
#define PCI_SRIOV_FUNC_LINK   0x12 /* Function Dependency Link */
 
#define PCI_SRIOV_VF_OFFSET   0x14 /* First VF Offset */
 
#define PCI_SRIOV_VF_STRIDE   0x16 /* Following VF Stride */
 
#define PCI_SRIOV_VF_DID   0x1a /* VF Device ID */
 
#define PCI_SRIOV_SUP_PGSIZE   0x1c /* Supported Page Sizes */
 
#define PCI_SRIOV_SYS_PGSIZE   0x20 /* System Page Size */
 
#define PCI_SRIOV_BAR   0x24 /* VF BAR0 */
 
#define PCI_SRIOV_NUM_BARS   6 /* Number of VF BARs */
 
#define PCI_SRIOV_VFM   0x3c /* VF Migration State Array Offset*/
 
#define PCI_SRIOV_VFM_BIR(x)   ((x) & 7) /* State BIR */
 
#define PCI_SRIOV_VFM_OFFSET(x)   ((x) & ~7) /* State Offset */
 
#define PCI_SRIOV_VFM_UA   0x0 /* Inactive.Unavailable */
 
#define PCI_SRIOV_VFM_MI   0x1 /* Dormant.MigrateIn */
 
#define PCI_SRIOV_VFM_MO   0x2 /* Active.MigrateOut */
 
#define PCI_SRIOV_VFM_AV   0x3 /* Active.Available */
 
#define PCI_EXT_CAP_SRIOV_SIZEOF   64
 
#define PCI_LTR_MAX_SNOOP_LAT   0x4
 
#define PCI_LTR_MAX_NOSNOOP_LAT   0x6
 
#define PCI_LTR_VALUE_MASK   0x000003ff
 
#define PCI_LTR_SCALE_MASK   0x00001c00
 
#define PCI_LTR_SCALE_SHIFT   10
 
#define PCI_EXT_CAP_LTR_SIZEOF   8
 
#define PCI_ACS_CAP   0x04 /* ACS Capability Register */
 
#define PCI_ACS_SV   0x01 /* Source Validation */
 
#define PCI_ACS_TB   0x02 /* Translation Blocking */
 
#define PCI_ACS_RR   0x04 /* P2P Request Redirect */
 
#define PCI_ACS_CR   0x08 /* P2P Completion Redirect */
 
#define PCI_ACS_UF   0x10 /* Upstream Forwarding */
 
#define PCI_ACS_EC   0x20 /* P2P Egress Control */
 
#define PCI_ACS_DT   0x40 /* Direct Translated P2P */
 
#define PCI_ACS_EGRESS_BITS   0x05 /* ACS Egress Control Vector Size */
 
#define PCI_ACS_CTRL   0x06 /* ACS Control Register */
 
#define PCI_ACS_EGRESS_CTL_V   0x08 /* ACS Egress Control Vector */
 
#define PCI_VSEC_HDR   4 /* extended cap - vendor specific */
 
#define PCI_VSEC_HDR_LEN_SHIFT   20 /* shift for length field */
 
#define PCI_SATA_REGS   4 /* SATA REGs specifier */
 
#define PCI_SATA_REGS_MASK   0xF /* location - BAR#/inline */
 
#define PCI_SATA_REGS_INLINE   0xF /* REGS in config space */
 
#define PCI_SATA_SIZEOF_SHORT   8
 
#define PCI_SATA_SIZEOF_LONG   16
 
#define PCI_REBAR_CTRL   8 /* control register */
 
#define PCI_REBAR_CTRL_NBAR_MASK   (7 << 5) /* mask for # bars */
 
#define PCI_REBAR_CTRL_NBAR_SHIFT   5 /* shift for # bars */
 
#define PCI_DPA_CAP   4 /* capability register */
 
#define PCI_DPA_CAP_SUBSTATE_MASK   0x1F /* # substates - 1 */
 
#define PCI_DPA_BASE_SIZEOF   16 /* size with 0 substates */
 
#define PCI_TPH_CAP   4 /* capability register */
 
#define PCI_TPH_CAP_LOC_MASK   0x600 /* location mask */
 
#define PCI_TPH_LOC_NONE   0x000 /* no location */
 
#define PCI_TPH_LOC_CAP   0x200 /* in capability */
 
#define PCI_TPH_LOC_MSIX   0x400 /* in MSI-X */
 
#define PCI_TPH_CAP_ST_MASK   0x07FF0000 /* st table mask */
 
#define PCI_TPH_CAP_ST_SHIFT   16 /* st table shift */
 
#define PCI_TPH_BASE_SIZEOF   12 /* size with no st table */
 

Macro Definition Documentation

#define HT_3BIT_CAP_MASK   0xE0

Definition at line 695 of file pci_regs.h.

#define HT_5BIT_CAP_MASK   0xF8

Definition at line 699 of file pci_regs.h.

#define HT_CAP_SIZEOF_LONG   28 /* slave & primary */

Definition at line 718 of file pci_regs.h.

#define HT_CAP_SIZEOF_SHORT   24 /* host & secondary */

Definition at line 719 of file pci_regs.h.

#define HT_CAPTYPE_DIRECT_ROUTE   0xB0 /* Direct routing configuration */

Definition at line 713 of file pci_regs.h.

#define HT_CAPTYPE_ERROR_RETRY   0xC0 /* Retry on error configuration */

Definition at line 715 of file pci_regs.h.

#define HT_CAPTYPE_EXTCONF   0x98 /* Extended Configuration Space Access */

Definition at line 704 of file pci_regs.h.

#define HT_CAPTYPE_GEN3   0xD0 /* Generation 3 hypertransport configuration */

Definition at line 716 of file pci_regs.h.

#define HT_CAPTYPE_HOST   0x20 /* Host/Secondary link configuration */

Definition at line 697 of file pci_regs.h.

#define HT_CAPTYPE_IRQ   0x80 /* IRQ Configuration */

Definition at line 700 of file pci_regs.h.

#define HT_CAPTYPE_MSI_MAPPING   0xA8 /* MSI Mapping Capability */

Definition at line 705 of file pci_regs.h.

#define HT_CAPTYPE_PM   0xE0 /* Hypertransport powermanagement configuration */

Definition at line 717 of file pci_regs.h.

#define HT_CAPTYPE_REMAPPING_40   0xA0 /* 40 bit address remapping */

Definition at line 701 of file pci_regs.h.

#define HT_CAPTYPE_REMAPPING_64   0xA2 /* 64 bit address remapping */

Definition at line 702 of file pci_regs.h.

#define HT_CAPTYPE_SLAVE   0x00 /* Slave/Primary link configuration */

Definition at line 696 of file pci_regs.h.

#define HT_CAPTYPE_UNITID_CLUMP   0x90 /* Unit ID clumping */

Definition at line 703 of file pci_regs.h.

#define HT_CAPTYPE_VCSET   0xB8 /* Virtual Channel configuration */

Definition at line 714 of file pci_regs.h.

#define HT_MSI_ADDR_HI   0x08 /* Offset to high addr bits */

Definition at line 712 of file pci_regs.h.

#define HT_MSI_ADDR_LO   0x04 /* Offset to low addr bits */

Definition at line 710 of file pci_regs.h.

#define HT_MSI_ADDR_LO_MASK   0xFFF00000 /* Low address bit mask */

Definition at line 711 of file pci_regs.h.

#define HT_MSI_FIXED_ADDR   0x00000000FEE00000ULL /* Fixed addr */

Definition at line 709 of file pci_regs.h.

#define HT_MSI_FLAGS   0x02 /* Offset to flags */

Definition at line 706 of file pci_regs.h.

#define HT_MSI_FLAGS_ENABLE   0x1 /* Mapping enable */

Definition at line 707 of file pci_regs.h.

#define HT_MSI_FLAGS_FIXED   0x2 /* Fixed mapping only */

Definition at line 708 of file pci_regs.h.

#define PCI_ACS_CAP   0x04 /* ACS Capability Register */

Definition at line 804 of file pci_regs.h.

#define PCI_ACS_CR   0x08 /* P2P Completion Redirect */

Definition at line 808 of file pci_regs.h.

#define PCI_ACS_CTRL   0x06 /* ACS Control Register */

Definition at line 813 of file pci_regs.h.

#define PCI_ACS_DT   0x40 /* Direct Translated P2P */

Definition at line 811 of file pci_regs.h.

#define PCI_ACS_EC   0x20 /* P2P Egress Control */

Definition at line 810 of file pci_regs.h.

#define PCI_ACS_EGRESS_BITS   0x05 /* ACS Egress Control Vector Size */

Definition at line 812 of file pci_regs.h.

#define PCI_ACS_EGRESS_CTL_V   0x08 /* ACS Egress Control Vector */

Definition at line 814 of file pci_regs.h.

#define PCI_ACS_RR   0x04 /* P2P Request Redirect */

Definition at line 807 of file pci_regs.h.

#define PCI_ACS_SV   0x01 /* Source Validation */

Definition at line 805 of file pci_regs.h.

#define PCI_ACS_TB   0x02 /* Translation Blocking */

Definition at line 806 of file pci_regs.h.

#define PCI_ACS_UF   0x10 /* Upstream Forwarding */

Definition at line 809 of file pci_regs.h.

#define PCI_AF_CAP   3

Definition at line 343 of file pci_regs.h.

#define PCI_AF_CAP_FLR   0x02

Definition at line 345 of file pci_regs.h.

#define PCI_AF_CAP_TP   0x01

Definition at line 344 of file pci_regs.h.

#define PCI_AF_CTRL   4

Definition at line 346 of file pci_regs.h.

#define PCI_AF_CTRL_FLR   0x01

Definition at line 347 of file pci_regs.h.

#define PCI_AF_LENGTH   2

Definition at line 342 of file pci_regs.h.

#define PCI_AF_STATUS   5

Definition at line 348 of file pci_regs.h.

#define PCI_AF_STATUS_TP   0x01

Definition at line 349 of file pci_regs.h.

#define PCI_AGP_COMMAND   8 /* Control register */

Definition at line 267 of file pci_regs.h.

#define PCI_AGP_COMMAND_64BIT   0x0020 /* Allow processing of 64-bit addresses */

Definition at line 271 of file pci_regs.h.

#define PCI_AGP_COMMAND_AGP   0x0100 /* Allow processing of AGP transactions */

Definition at line 270 of file pci_regs.h.

#define PCI_AGP_COMMAND_FW   0x0010 /* Force FW transfers */

Definition at line 272 of file pci_regs.h.

#define PCI_AGP_COMMAND_RATE1   0x0001 /* Use 1x rate */

Definition at line 275 of file pci_regs.h.

#define PCI_AGP_COMMAND_RATE2   0x0002 /* Use 2x rate */

Definition at line 274 of file pci_regs.h.

#define PCI_AGP_COMMAND_RATE4   0x0004 /* Use 4x rate */

Definition at line 273 of file pci_regs.h.

#define PCI_AGP_COMMAND_RQ_MASK   0xff000000 /* Master: Maximum number of requests */

Definition at line 268 of file pci_regs.h.

#define PCI_AGP_COMMAND_SBA   0x0200 /* Sideband addressing enabled */

Definition at line 269 of file pci_regs.h.

#define PCI_AGP_RFU   3 /* Rest of capability flags */

Definition at line 258 of file pci_regs.h.

#define PCI_AGP_SIZEOF   12

Definition at line 276 of file pci_regs.h.

#define PCI_AGP_STATUS   4 /* Status register */

Definition at line 259 of file pci_regs.h.

#define PCI_AGP_STATUS_64BIT   0x0020 /* 64-bit addressing supported */

Definition at line 262 of file pci_regs.h.

#define PCI_AGP_STATUS_FW   0x0010 /* FW transfers supported */

Definition at line 263 of file pci_regs.h.

#define PCI_AGP_STATUS_RATE1   0x0001 /* 1x transfer rate supported */

Definition at line 266 of file pci_regs.h.

#define PCI_AGP_STATUS_RATE2   0x0002 /* 2x transfer rate supported */

Definition at line 265 of file pci_regs.h.

#define PCI_AGP_STATUS_RATE4   0x0004 /* 4x transfer rate supported */

Definition at line 264 of file pci_regs.h.

#define PCI_AGP_STATUS_RQ_MASK   0xff000000 /* Maximum number of requests - 1 */

Definition at line 260 of file pci_regs.h.

#define PCI_AGP_STATUS_SBA   0x0200 /* Sideband addressing supported */

Definition at line 261 of file pci_regs.h.

#define PCI_AGP_VERSION   2 /* BCD version number */

Definition at line 257 of file pci_regs.h.

#define PCI_ARI_CAP   0x04 /* ARI Capability Register */

Definition at line 722 of file pci_regs.h.

#define PCI_ARI_CAP_ACS   0x0002 /* ACS Function Groups Capability */

Definition at line 724 of file pci_regs.h.

#define PCI_ARI_CAP_MFVC   0x0001 /* MFVC Function Groups Capability */

Definition at line 723 of file pci_regs.h.

#define PCI_ARI_CAP_NFN (   x)    (((x) >> 8) & 0xff) /* Next Function Number */

Definition at line 725 of file pci_regs.h.

#define PCI_ARI_CTRL   0x06 /* ARI Control Register */

Definition at line 726 of file pci_regs.h.

#define PCI_ARI_CTRL_ACS   0x0002 /* ACS Function Groups Enable */

Definition at line 728 of file pci_regs.h.

#define PCI_ARI_CTRL_FG (   x)    (((x) >> 4) & 7) /* Function Group */

Definition at line 729 of file pci_regs.h.

#define PCI_ARI_CTRL_MFVC   0x0001 /* MFVC Function Groups Enable */

Definition at line 727 of file pci_regs.h.

#define PCI_ATS_CAP   0x04 /* ATS Capability Register */

Definition at line 733 of file pci_regs.h.

#define PCI_ATS_CAP_QDEP (   x)    ((x) & 0x1f) /* Invalidate Queue Depth */

Definition at line 734 of file pci_regs.h.

#define PCI_ATS_CTRL   0x06 /* ATS Control Register */

Definition at line 736 of file pci_regs.h.

#define PCI_ATS_CTRL_ENABLE   0x8000 /* ATS Enable */

Definition at line 737 of file pci_regs.h.

#define PCI_ATS_CTRL_STU (   x)    ((x) & 0x1f) /* Smallest Translation Unit */

Definition at line 738 of file pci_regs.h.

#define PCI_ATS_MAX_QDEP   32 /* Max Invalidate Queue Depth */

Definition at line 735 of file pci_regs.h.

#define PCI_ATS_MIN_STU   12 /* shift of minimum STU block */

Definition at line 739 of file pci_regs.h.

#define PCI_BASE_ADDRESS_0   0x10 /* 32 bits */

Definition at line 85 of file pci_regs.h.

#define PCI_BASE_ADDRESS_1   0x14 /* 32 bits [htype 0,1 only] */

Definition at line 86 of file pci_regs.h.

#define PCI_BASE_ADDRESS_2   0x18 /* 32 bits [htype 0 only] */

Definition at line 87 of file pci_regs.h.

#define PCI_BASE_ADDRESS_3   0x1c /* 32 bits */

Definition at line 88 of file pci_regs.h.

#define PCI_BASE_ADDRESS_4   0x20 /* 32 bits */

Definition at line 89 of file pci_regs.h.

#define PCI_BASE_ADDRESS_5   0x24 /* 32 bits */

Definition at line 90 of file pci_regs.h.

#define PCI_BASE_ADDRESS_IO_MASK   (~0x03UL)

Definition at line 100 of file pci_regs.h.

#define PCI_BASE_ADDRESS_MEM_MASK   (~0x0fUL)

Definition at line 99 of file pci_regs.h.

#define PCI_BASE_ADDRESS_MEM_PREFETCH   0x08 /* prefetchable? */

Definition at line 98 of file pci_regs.h.

#define PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02 /* Below 1M [obsolete] */

Definition at line 96 of file pci_regs.h.

#define PCI_BASE_ADDRESS_MEM_TYPE_32   0x00 /* 32 bit address */

Definition at line 95 of file pci_regs.h.

#define PCI_BASE_ADDRESS_MEM_TYPE_64   0x04 /* 64 bit address */

Definition at line 97 of file pci_regs.h.

#define PCI_BASE_ADDRESS_MEM_TYPE_MASK   0x06

Definition at line 94 of file pci_regs.h.

#define PCI_BASE_ADDRESS_SPACE   0x01 /* 0 = memory, 1 = I/O */

Definition at line 91 of file pci_regs.h.

#define PCI_BASE_ADDRESS_SPACE_IO   0x01

Definition at line 92 of file pci_regs.h.

#define PCI_BASE_ADDRESS_SPACE_MEMORY   0x00

Definition at line 93 of file pci_regs.h.

#define PCI_BIST   0x0f /* 8 bits */

Definition at line 74 of file pci_regs.h.

#define PCI_BIST_CAPABLE   0x80 /* 1 if BIST capable */

Definition at line 77 of file pci_regs.h.

#define PCI_BIST_CODE_MASK   0x0f /* Return result */

Definition at line 75 of file pci_regs.h.

#define PCI_BIST_START   0x40 /* 1 to start BIST, 2 secs or less */

Definition at line 76 of file pci_regs.h.

#define PCI_BRIDGE_CONTROL   0x3e

Definition at line 150 of file pci_regs.h.

#define PCI_BRIDGE_CTL_BUS_RESET   0x40 /* Secondary bus reset */

Definition at line 156 of file pci_regs.h.

#define PCI_BRIDGE_CTL_FAST_BACK   0x80 /* Fast Back2Back enabled on secondary interface */

Definition at line 157 of file pci_regs.h.

#define PCI_BRIDGE_CTL_ISA   0x04 /* Enable ISA mode */

Definition at line 153 of file pci_regs.h.

#define PCI_BRIDGE_CTL_MASTER_ABORT   0x20 /* Report master aborts */

Definition at line 155 of file pci_regs.h.

#define PCI_BRIDGE_CTL_PARITY   0x01 /* Enable parity detection on secondary interface */

Definition at line 151 of file pci_regs.h.

#define PCI_BRIDGE_CTL_SERR   0x02 /* The same for SERR forwarding */

Definition at line 152 of file pci_regs.h.

#define PCI_BRIDGE_CTL_VGA   0x08 /* Forward VGA addresses */

Definition at line 154 of file pci_regs.h.

#define PCI_CACHE_LINE_SIZE   0x0c /* 8 bits */

Definition at line 67 of file pci_regs.h.

#define PCI_CAP_AF_SIZEOF   6 /* size of AF registers */

Definition at line 350 of file pci_regs.h.

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1   20 /* v1 endpoints end here */

Definition at line 479 of file pci_regs.h.

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2   44 /* v2 endpoints end here */

Definition at line 545 of file pci_regs.h.

#define PCI_CAP_FLAGS   2 /* Capability defined flags (16 bits) */

Definition at line 221 of file pci_regs.h.

#define PCI_CAP_ID_AF   0x13 /* PCI Advanced Features */

Definition at line 218 of file pci_regs.h.

#define PCI_CAP_ID_AGP   0x02 /* Accelerated Graphics Port */

Definition at line 201 of file pci_regs.h.

#define PCI_CAP_ID_AGP3   0x0E /* AGP Target PCI-PCI bridge */

Definition at line 213 of file pci_regs.h.

#define PCI_CAP_ID_CCRC   0x0B /* CompactPCI Central Resource Control */

Definition at line 210 of file pci_regs.h.

#define PCI_CAP_ID_CHSWP   0x06 /* CompactPCI HotSwap */

Definition at line 205 of file pci_regs.h.

#define PCI_CAP_ID_DBG   0x0A /* Debug port */

Definition at line 209 of file pci_regs.h.

#define PCI_CAP_ID_EXP   0x10 /* PCI Express */

Definition at line 215 of file pci_regs.h.

#define PCI_CAP_ID_HT   0x08 /* HyperTransport */

Definition at line 207 of file pci_regs.h.

#define PCI_CAP_ID_MAX   PCI_CAP_ID_AF

Definition at line 219 of file pci_regs.h.

#define PCI_CAP_ID_MSI   0x05 /* Message Signalled Interrupts */

Definition at line 204 of file pci_regs.h.

#define PCI_CAP_ID_MSIX   0x11 /* MSI-X */

Definition at line 216 of file pci_regs.h.

#define PCI_CAP_ID_PCIX   0x07 /* PCI-X */

Definition at line 206 of file pci_regs.h.

#define PCI_CAP_ID_PM   0x01 /* Power Management */

Definition at line 200 of file pci_regs.h.

#define PCI_CAP_ID_SATA   0x12 /* SATA Data/Index Conf. */

Definition at line 217 of file pci_regs.h.

#define PCI_CAP_ID_SECDEV   0x0F /* Secure Device */

Definition at line 214 of file pci_regs.h.

#define PCI_CAP_ID_SHPC   0x0C /* PCI Standard Hot-Plug Controller */

Definition at line 211 of file pci_regs.h.

#define PCI_CAP_ID_SLOTID   0x04 /* Slot Identification */

Definition at line 203 of file pci_regs.h.

#define PCI_CAP_ID_SSVID   0x0D /* Bridge subsystem vendor/device ID */

Definition at line 212 of file pci_regs.h.

#define PCI_CAP_ID_VNDR   0x09 /* Vendor specific */

Definition at line 208 of file pci_regs.h.

#define PCI_CAP_ID_VPD   0x03 /* Vital Product Data */

Definition at line 202 of file pci_regs.h.

#define PCI_CAP_LIST_ID   0 /* Capability ID */

Definition at line 199 of file pci_regs.h.

#define PCI_CAP_LIST_NEXT   1 /* Next capability in the list */

Definition at line 220 of file pci_regs.h.

#define PCI_CAP_MSIX_SIZEOF   12 /* size of MSIX registers */

Definition at line 319 of file pci_regs.h.

#define PCI_CAP_PCIX_SIZEOF_V0   8 /* size of registers for Version 0 */

Definition at line 388 of file pci_regs.h.

#define PCI_CAP_PCIX_SIZEOF_V1   24 /* size for Version 1 */

Definition at line 389 of file pci_regs.h.

#define PCI_CAP_PCIX_SIZEOF_V2   PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */

Definition at line 390 of file pci_regs.h.

#define PCI_CAP_SIZEOF   4

Definition at line 222 of file pci_regs.h.

#define PCI_CAP_VC_BASE_SIZEOF   0x10

Definition at line 665 of file pci_regs.h.

#define PCI_CAP_VC_PER_VC_SIZEOF   0x0C

Definition at line 666 of file pci_regs.h.

#define PCI_CAP_VPD_SIZEOF   8

Definition at line 284 of file pci_regs.h.

#define PCI_CAPABILITY_LIST   0x34 /* Offset of first capability list entry */

Definition at line 111 of file pci_regs.h.

#define PCI_CARDBUS_CIS   0x28

Definition at line 104 of file pci_regs.h.

#define PCI_CB_BRIDGE_CONTROL   0x3e

Definition at line 181 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_16BIT_INT   0x80 /* Enable interrupt for 16-bit cards */

Definition at line 188 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_CB_RESET   0x40 /* CardBus reset */

Definition at line 187 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_ISA   0x04

Definition at line 184 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_MASTER_ABORT   0x20

Definition at line 186 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_PARITY   0x01 /* Similar to standard bridge control register */

Definition at line 182 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_POST_WRITES   0x400

Definition at line 191 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0   0x100 /* Prefetch enable for both memory regions */

Definition at line 189 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1   0x200

Definition at line 190 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_SERR   0x02

Definition at line 183 of file pci_regs.h.

#define PCI_CB_BRIDGE_CTL_VGA   0x08

Definition at line 185 of file pci_regs.h.

#define PCI_CB_CAPABILITY_LIST   0x14

Definition at line 160 of file pci_regs.h.

#define PCI_CB_CARD_BUS   0x19 /* CardBus bus number */

Definition at line 164 of file pci_regs.h.

#define PCI_CB_IO_BASE_0   0x2c

Definition at line 171 of file pci_regs.h.

#define PCI_CB_IO_BASE_0_HI   0x2e

Definition at line 172 of file pci_regs.h.

#define PCI_CB_IO_BASE_1   0x34

Definition at line 175 of file pci_regs.h.

#define PCI_CB_IO_BASE_1_HI   0x36

Definition at line 176 of file pci_regs.h.

#define PCI_CB_IO_LIMIT_0   0x30

Definition at line 173 of file pci_regs.h.

#define PCI_CB_IO_LIMIT_0_HI   0x32

Definition at line 174 of file pci_regs.h.

#define PCI_CB_IO_LIMIT_1   0x38

Definition at line 177 of file pci_regs.h.

#define PCI_CB_IO_LIMIT_1_HI   0x3a

Definition at line 178 of file pci_regs.h.

#define PCI_CB_IO_RANGE_MASK   (~0x03UL)

Definition at line 179 of file pci_regs.h.

#define PCI_CB_LATENCY_TIMER   0x1b /* CardBus latency timer */

Definition at line 166 of file pci_regs.h.

#define PCI_CB_LEGACY_MODE_BASE   0x44 /* 16-bit PC Card legacy mode base address (ExCa) */

Definition at line 194 of file pci_regs.h.

#define PCI_CB_MEMORY_BASE_0   0x1c

Definition at line 167 of file pci_regs.h.

#define PCI_CB_MEMORY_BASE_1   0x24

Definition at line 169 of file pci_regs.h.

#define PCI_CB_MEMORY_LIMIT_0   0x20

Definition at line 168 of file pci_regs.h.

#define PCI_CB_MEMORY_LIMIT_1   0x28

Definition at line 170 of file pci_regs.h.

#define PCI_CB_PRIMARY_BUS   0x18 /* PCI bus number */

Definition at line 163 of file pci_regs.h.

#define PCI_CB_SEC_STATUS   0x16 /* Secondary status */

Definition at line 162 of file pci_regs.h.

#define PCI_CB_SUBORDINATE_BUS   0x1a /* Subordinate bus number */

Definition at line 165 of file pci_regs.h.

#define PCI_CB_SUBSYSTEM_ID   0x42

Definition at line 193 of file pci_regs.h.

#define PCI_CB_SUBSYSTEM_VENDOR_ID   0x40

Definition at line 192 of file pci_regs.h.

#define PCI_CHSWP_CSR   2 /* Control and Status Register */

Definition at line 331 of file pci_regs.h.

#define PCI_CHSWP_DHA   0x01 /* Device Hiding Arm */

Definition at line 332 of file pci_regs.h.

#define PCI_CHSWP_EIM   0x02 /* ENUM# Signal Mask */

Definition at line 333 of file pci_regs.h.

#define PCI_CHSWP_EXT   0x40 /* ENUM# status - extraction */

Definition at line 337 of file pci_regs.h.

#define PCI_CHSWP_INS   0x80 /* ENUM# status - insertion */

Definition at line 338 of file pci_regs.h.

#define PCI_CHSWP_LOO   0x08 /* LED On / Off */

Definition at line 335 of file pci_regs.h.

#define PCI_CHSWP_PI   0x30 /* Programming Interface */

Definition at line 336 of file pci_regs.h.

#define PCI_CHSWP_PIE   0x04 /* Pending Insert or Extract */

Definition at line 334 of file pci_regs.h.

#define PCI_CLASS_DEVICE   0x0a /* Device class */

Definition at line 65 of file pci_regs.h.

#define PCI_CLASS_PROG   0x09 /* Reg. Level Programming Interface */

Definition at line 64 of file pci_regs.h.

#define PCI_CLASS_REVISION   0x08 /* High 24 bits are class, low 8 revision */

Definition at line 62 of file pci_regs.h.

#define PCI_COMMAND   0x04 /* 16 bits */

Definition at line 32 of file pci_regs.h.

#define PCI_COMMAND_FAST_BACK   0x200 /* Enable back-to-back writes */

Definition at line 42 of file pci_regs.h.

#define PCI_COMMAND_INTX_DISABLE   0x400 /* INTx Emulation Disable */

Definition at line 43 of file pci_regs.h.

#define PCI_COMMAND_INVALIDATE   0x10 /* Use memory write and invalidate */

Definition at line 37 of file pci_regs.h.

#define PCI_COMMAND_IO   0x1 /* Enable response in I/O space */

Definition at line 33 of file pci_regs.h.

#define PCI_COMMAND_MASTER   0x4 /* Enable bus mastering */

Definition at line 35 of file pci_regs.h.

#define PCI_COMMAND_MEMORY   0x2 /* Enable response in Memory space */

Definition at line 34 of file pci_regs.h.

#define PCI_COMMAND_PARITY   0x40 /* Enable parity checking */

Definition at line 39 of file pci_regs.h.

#define PCI_COMMAND_SERR   0x100 /* Enable SERR */

Definition at line 41 of file pci_regs.h.

#define PCI_COMMAND_SPECIAL   0x8 /* Enable response to special cycles */

Definition at line 36 of file pci_regs.h.

#define PCI_COMMAND_VGA_PALETTE   0x20 /* Enable palette snooping */

Definition at line 38 of file pci_regs.h.

#define PCI_COMMAND_WAIT   0x80 /* Enable address/data stepping */

Definition at line 40 of file pci_regs.h.

#define PCI_DEVICE_ID   0x02 /* 16 bits */

Definition at line 31 of file pci_regs.h.

#define PCI_DPA_BASE_SIZEOF   16 /* size with 0 substates */

Definition at line 834 of file pci_regs.h.

#define PCI_DPA_CAP   4 /* capability register */

Definition at line 832 of file pci_regs.h.

#define PCI_DPA_CAP_SUBSTATE_MASK   0x1F /* # substates - 1 */

Definition at line 833 of file pci_regs.h.

#define PCI_ERR_CAP   24 /* Advanced Error Capabilities */

Definition at line 626 of file pci_regs.h.

#define PCI_ERR_CAP_ECRC_CHKC   0x00000080 /* ECRC Check Capable */

Definition at line 630 of file pci_regs.h.

#define PCI_ERR_CAP_ECRC_CHKE   0x00000100 /* ECRC Check Enable */

Definition at line 631 of file pci_regs.h.

#define PCI_ERR_CAP_ECRC_GENC   0x00000020 /* ECRC Generation Capable */

Definition at line 628 of file pci_regs.h.

#define PCI_ERR_CAP_ECRC_GENE   0x00000040 /* ECRC Generation Enable */

Definition at line 629 of file pci_regs.h.

#define PCI_ERR_CAP_FEP (   x)    ((x) & 31) /* First Error Pointer */

Definition at line 627 of file pci_regs.h.

#define PCI_ERR_COR_ADV_NFAT   0x00002000 /* Advisory Non-Fatal */

Definition at line 621 of file pci_regs.h.

#define PCI_ERR_COR_BAD_DLLP   0x00000080 /* Bad DLLP Status */

Definition at line 618 of file pci_regs.h.

#define PCI_ERR_COR_BAD_TLP   0x00000040 /* Bad TLP Status */

Definition at line 617 of file pci_regs.h.

#define PCI_ERR_COR_INTERNAL   0x00004000 /* Corrected Internal */

Definition at line 622 of file pci_regs.h.

#define PCI_ERR_COR_LOG_OVER   0x00008000 /* Header Log Overflow */

Definition at line 623 of file pci_regs.h.

#define PCI_ERR_COR_MASK   20 /* Correctable Error Mask */

Definition at line 624 of file pci_regs.h.

#define PCI_ERR_COR_RCVR   0x00000001 /* Receiver Error Status */

Definition at line 616 of file pci_regs.h.

#define PCI_ERR_COR_REP_ROLL   0x00000100 /* REPLAY_NUM Rollover */

Definition at line 619 of file pci_regs.h.

#define PCI_ERR_COR_REP_TIMER   0x00001000 /* Replay Timer Timeout */

Definition at line 620 of file pci_regs.h.

#define PCI_ERR_COR_STATUS   16 /* Correctable Error Status */

Definition at line 615 of file pci_regs.h.

#define PCI_ERR_HEADER_LOG   28 /* Header Log Register (16 bytes) */

Definition at line 632 of file pci_regs.h.

#define PCI_ERR_ROOT_CMD_COR_EN   0x00000001

Definition at line 635 of file pci_regs.h.

#define PCI_ERR_ROOT_CMD_FATAL_EN   0x00000004

Definition at line 639 of file pci_regs.h.

#define PCI_ERR_ROOT_CMD_NONFATAL_EN   0x00000002

Definition at line 637 of file pci_regs.h.

#define PCI_ERR_ROOT_COMMAND   44 /* Root Error Command */

Definition at line 633 of file pci_regs.h.

#define PCI_ERR_ROOT_COR_RCV   0x00000001 /* ERR_COR Received */

Definition at line 641 of file pci_regs.h.

#define PCI_ERR_ROOT_ERR_SRC   52 /* Error Source Identification */

Definition at line 651 of file pci_regs.h.

#define PCI_ERR_ROOT_FATAL_RCV   0x00000040 /* Fatal Received */

Definition at line 650 of file pci_regs.h.

#define PCI_ERR_ROOT_FIRST_FATAL   0x00000010 /* First Fatal */

Definition at line 648 of file pci_regs.h.

#define PCI_ERR_ROOT_MULTI_COR_RCV   0x00000002

Definition at line 643 of file pci_regs.h.

#define PCI_ERR_ROOT_MULTI_UNCOR_RCV   0x00000008

Definition at line 647 of file pci_regs.h.

#define PCI_ERR_ROOT_NONFATAL_RCV   0x00000020 /* Non-Fatal Received */

Definition at line 649 of file pci_regs.h.

#define PCI_ERR_ROOT_STATUS   48

Definition at line 640 of file pci_regs.h.

#define PCI_ERR_ROOT_UNCOR_RCV   0x00000004

Definition at line 645 of file pci_regs.h.

#define PCI_ERR_UNC_ACSV   0x00200000 /* ACS Violation */

Definition at line 606 of file pci_regs.h.

#define PCI_ERR_UNC_ATOMEG   0x01000000 /* Atomic egress blocked */

Definition at line 609 of file pci_regs.h.

#define PCI_ERR_UNC_COMP_ABORT   0x00008000 /* Completer Abort */

Definition at line 600 of file pci_regs.h.

#define PCI_ERR_UNC_COMP_TIME   0x00004000 /* Completion Timeout */

Definition at line 599 of file pci_regs.h.

#define PCI_ERR_UNC_DLP   0x00000010 /* Data Link Protocol */

Definition at line 595 of file pci_regs.h.

#define PCI_ERR_UNC_ECRC   0x00080000 /* ECRC Error Status */

Definition at line 604 of file pci_regs.h.

#define PCI_ERR_UNC_FCP   0x00002000 /* Flow Control Protocol */

Definition at line 598 of file pci_regs.h.

#define PCI_ERR_UNC_INTN   0x00400000 /* internal error */

Definition at line 607 of file pci_regs.h.

#define PCI_ERR_UNC_MALF_TLP   0x00040000 /* Malformed TLP */

Definition at line 603 of file pci_regs.h.

#define PCI_ERR_UNC_MCBTLP   0x00800000 /* MC blocked TLP */

Definition at line 608 of file pci_regs.h.

#define PCI_ERR_UNC_POISON_TLP   0x00001000 /* Poisoned TLP */

Definition at line 597 of file pci_regs.h.

#define PCI_ERR_UNC_RX_OVER   0x00020000 /* Receiver Overflow */

Definition at line 602 of file pci_regs.h.

#define PCI_ERR_UNC_SURPDN   0x00000020 /* Surprise Down */

Definition at line 596 of file pci_regs.h.

#define PCI_ERR_UNC_TLPPRE   0x02000000 /* TLP prefix blocked */

Definition at line 610 of file pci_regs.h.

#define PCI_ERR_UNC_TRAIN   0x00000001 /* Training */

Definition at line 594 of file pci_regs.h.

#define PCI_ERR_UNC_UNSUP   0x00100000 /* Unsupported Request */

Definition at line 605 of file pci_regs.h.

#define PCI_ERR_UNC_UNX_COMP   0x00010000 /* Unexpected Completion */

Definition at line 601 of file pci_regs.h.

#define PCI_ERR_UNCOR_MASK   8 /* Uncorrectable Error Mask */

Definition at line 611 of file pci_regs.h.

#define PCI_ERR_UNCOR_SEVER   12 /* Uncorrectable Error Severity */

Definition at line 613 of file pci_regs.h.

#define PCI_ERR_UNCOR_STATUS   4 /* Uncorrectable Error Status */

Definition at line 593 of file pci_regs.h.

#define PCI_EXP_DEVCAP   4 /* Device capabilities */

Definition at line 413 of file pci_regs.h.

#define PCI_EXP_DEVCAP2   36 /* Device Capabilities 2 */

Definition at line 531 of file pci_regs.h.

#define PCI_EXP_DEVCAP2_ARI   0x20 /* Alternative Routing-ID */

Definition at line 532 of file pci_regs.h.

#define PCI_EXP_DEVCAP2_LTR   0x800 /* Latency tolerance reporting */

Definition at line 533 of file pci_regs.h.

#define PCI_EXP_DEVCAP_ATN_BUT   0x1000 /* Attention Button Present */

Definition at line 419 of file pci_regs.h.

#define PCI_EXP_DEVCAP_ATN_IND   0x2000 /* Attention Indicator Present */

Definition at line 420 of file pci_regs.h.

#define PCI_EXP_DEVCAP_EXT_TAG   0x20 /* Extended tags */

Definition at line 416 of file pci_regs.h.

#define PCI_EXP_DEVCAP_FLR   0x10000000 /* Function Level Reset */

Definition at line 425 of file pci_regs.h.

#define PCI_EXP_DEVCAP_L0S   0x1c0 /* L0s Acceptable Latency */

Definition at line 417 of file pci_regs.h.

#define PCI_EXP_DEVCAP_L1   0xe00 /* L1 Acceptable Latency */

Definition at line 418 of file pci_regs.h.

#define PCI_EXP_DEVCAP_PAYLOAD   0x07 /* Max_Payload_Size */

Definition at line 414 of file pci_regs.h.

#define PCI_EXP_DEVCAP_PHANTOM   0x18 /* Phantom functions */

Definition at line 415 of file pci_regs.h.

#define PCI_EXP_DEVCAP_PWR_IND   0x4000 /* Power Indicator Present */

Definition at line 421 of file pci_regs.h.

#define PCI_EXP_DEVCAP_PWR_SCL   0xc000000 /* Slot Power Limit Scale */

Definition at line 424 of file pci_regs.h.

#define PCI_EXP_DEVCAP_PWR_VAL   0x3fc0000 /* Slot Power Limit Value */

Definition at line 423 of file pci_regs.h.

#define PCI_EXP_DEVCAP_RBER   0x8000 /* Role-Based Error Reporting */

Definition at line 422 of file pci_regs.h.

#define PCI_EXP_DEVCTL   8 /* Device Control */

Definition at line 426 of file pci_regs.h.

#define PCI_EXP_DEVCTL2   40 /* Device Control 2 */

Definition at line 537 of file pci_regs.h.

#define PCI_EXP_DEVCTL2_ARI   0x20 /* Alternative Routing-ID */

Definition at line 538 of file pci_regs.h.

#define PCI_EXP_DEVCTL_AUX_PME   0x0400 /* Auxiliary Power PM Enable */

Definition at line 435 of file pci_regs.h.

#define PCI_EXP_DEVCTL_BCR_FLR   0x8000 /* Bridge Configuration Retry / FLR */

Definition at line 438 of file pci_regs.h.

#define PCI_EXP_DEVCTL_CERE   0x0001 /* Correctable Error Reporting En. */

Definition at line 427 of file pci_regs.h.

#define PCI_EXP_DEVCTL_EXT_TAG   0x0100 /* Extended Tag Field Enable */

Definition at line 433 of file pci_regs.h.

#define PCI_EXP_DEVCTL_FERE   0x0004 /* Fatal Error Reporting Enable */

Definition at line 429 of file pci_regs.h.

#define PCI_EXP_DEVCTL_NFERE   0x0002 /* Non-Fatal Error Reporting Enable */

Definition at line 428 of file pci_regs.h.

#define PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800 /* Enable No Snoop */

Definition at line 436 of file pci_regs.h.

#define PCI_EXP_DEVCTL_PAYLOAD   0x00e0 /* Max_Payload_Size */

Definition at line 432 of file pci_regs.h.

#define PCI_EXP_DEVCTL_PHANTOM   0x0200 /* Phantom Functions Enable */

Definition at line 434 of file pci_regs.h.

#define PCI_EXP_DEVCTL_READRQ   0x7000 /* Max_Read_Request_Size */

Definition at line 437 of file pci_regs.h.

#define PCI_EXP_DEVCTL_RELAX_EN   0x0010 /* Enable relaxed ordering */

Definition at line 431 of file pci_regs.h.

#define PCI_EXP_DEVCTL_URRE   0x0008 /* Unsupported Request Reporting En. */

Definition at line 430 of file pci_regs.h.

#define PCI_EXP_DEVSTA   10 /* Device Status */

Definition at line 439 of file pci_regs.h.

#define PCI_EXP_DEVSTA_AUXPD   0x10 /* AUX Power Detected */

Definition at line 444 of file pci_regs.h.

#define PCI_EXP_DEVSTA_CED   0x01 /* Correctable Error Detected */

Definition at line 440 of file pci_regs.h.

#define PCI_EXP_DEVSTA_FED   0x04 /* Fatal Error Detected */

Definition at line 442 of file pci_regs.h.

#define PCI_EXP_DEVSTA_NFED   0x02 /* Non-Fatal Error Detected */

Definition at line 441 of file pci_regs.h.

#define PCI_EXP_DEVSTA_TRPND   0x20 /* Transactions Pending */

Definition at line 445 of file pci_regs.h.

#define PCI_EXP_DEVSTA_URD   0x08 /* Unsupported Request Detected */

Definition at line 443 of file pci_regs.h.

#define PCI_EXP_FLAGS   2 /* Capabilities register */

Definition at line 399 of file pci_regs.h.

#define PCI_EXP_FLAGS_IRQ   0x3e00 /* Interrupt message number */

Definition at line 412 of file pci_regs.h.

#define PCI_EXP_FLAGS_SLOT   0x0100 /* Slot implemented */

Definition at line 411 of file pci_regs.h.

#define PCI_EXP_FLAGS_TYPE   0x00f0 /* Device/Port type */

Definition at line 401 of file pci_regs.h.

#define PCI_EXP_FLAGS_VERS   0x000f /* Capability version */

Definition at line 400 of file pci_regs.h.

#define PCI_EXP_IDO_CMP_EN   0x200 /* ID-based ordering completion enable */

Definition at line 540 of file pci_regs.h.

#define PCI_EXP_IDO_REQ_EN   0x100 /* ID-based ordering request enable */

Definition at line 539 of file pci_regs.h.

#define PCI_EXP_LNKCAP   12 /* Link Capabilities */

Definition at line 446 of file pci_regs.h.

#define PCI_EXP_LNKCAP2   44 /* Link Capability 2 */

Definition at line 546 of file pci_regs.h.

#define PCI_EXP_LNKCAP2_CROSSLINK   0x100 /* Crosslink supported */

Definition at line 550 of file pci_regs.h.

#define PCI_EXP_LNKCAP2_SLS_2_5GB   0x01 /* Current Link Speed 2.5GT/s */

Definition at line 547 of file pci_regs.h.

#define PCI_EXP_LNKCAP2_SLS_5_0GB   0x02 /* Current Link Speed 5.0GT/s */

Definition at line 548 of file pci_regs.h.

#define PCI_EXP_LNKCAP2_SLS_8_0GB   0x04 /* Current Link Speed 8.0GT/s */

Definition at line 549 of file pci_regs.h.

#define PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */

Definition at line 449 of file pci_regs.h.

#define PCI_EXP_LNKCAP_CLKPM   0x00040000 /* L1 Clock Power Management */

Definition at line 452 of file pci_regs.h.

#define PCI_EXP_LNKCAP_DLLLARC   0x00100000 /* Data Link Layer Link Active Reporting Capable */

Definition at line 454 of file pci_regs.h.

#define PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */

Definition at line 450 of file pci_regs.h.

#define PCI_EXP_LNKCAP_L1EL   0x00038000 /* L1 Exit Latency */

Definition at line 451 of file pci_regs.h.

#define PCI_EXP_LNKCAP_LBNC   0x00200000 /* Link Bandwidth Notification Capability */

Definition at line 455 of file pci_regs.h.

#define PCI_EXP_LNKCAP_MLW   0x000003f0 /* Maximum Link Width */

Definition at line 448 of file pci_regs.h.

#define PCI_EXP_LNKCAP_PN   0xff000000 /* Port Number */

Definition at line 456 of file pci_regs.h.

#define PCI_EXP_LNKCAP_SDERC   0x00080000 /* Surprise Down Error Reporting Capable */

Definition at line 453 of file pci_regs.h.

#define PCI_EXP_LNKCAP_SLS   0x0000000f /* Supported Link Speeds */

Definition at line 447 of file pci_regs.h.

#define PCI_EXP_LNKCTL   16 /* Link Control */

Definition at line 457 of file pci_regs.h.

#define PCI_EXP_LNKCTL2   48 /* Link Control 2 */

Definition at line 551 of file pci_regs.h.

#define PCI_EXP_LNKCTL_ASPMC   0x0003 /* ASPM Control */

Definition at line 458 of file pci_regs.h.

#define PCI_EXP_LNKCTL_CCC   0x0040 /* Common Clock Configuration */

Definition at line 462 of file pci_regs.h.

#define PCI_EXP_LNKCTL_CLKREQ_EN   0x100 /* Enable clkreq */

Definition at line 464 of file pci_regs.h.

#define PCI_EXP_LNKCTL_ES   0x0080 /* Extended Synch */

Definition at line 463 of file pci_regs.h.

#define PCI_EXP_LNKCTL_HAWD   0x0200 /* Hardware Autonomous Width Disable */

Definition at line 465 of file pci_regs.h.

#define PCI_EXP_LNKCTL_LABIE   0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */

Definition at line 467 of file pci_regs.h.

#define PCI_EXP_LNKCTL_LBMIE   0x0400 /* Link Bandwidth Management Interrupt Enable */

Definition at line 466 of file pci_regs.h.

#define PCI_EXP_LNKCTL_LD   0x0010 /* Link Disable */

Definition at line 460 of file pci_regs.h.

#define PCI_EXP_LNKCTL_RCB   0x0008 /* Read Completion Boundary */

Definition at line 459 of file pci_regs.h.

#define PCI_EXP_LNKCTL_RL   0x0020 /* Retrain Link */

Definition at line 461 of file pci_regs.h.

#define PCI_EXP_LNKSTA   18 /* Link Status */

Definition at line 468 of file pci_regs.h.

#define PCI_EXP_LNKSTA2   50 /* Link Status 2 */

Definition at line 552 of file pci_regs.h.

#define PCI_EXP_LNKSTA_CLS   0x000f /* Current Link Speed */

Definition at line 469 of file pci_regs.h.

#define PCI_EXP_LNKSTA_CLS_2_5GB   0x01 /* Current Link Speed 2.5GT/s */

Definition at line 470 of file pci_regs.h.

#define PCI_EXP_LNKSTA_CLS_5_0GB   0x02 /* Current Link Speed 5.0GT/s */

Definition at line 471 of file pci_regs.h.

#define PCI_EXP_LNKSTA_DLLLA   0x2000 /* Data Link Layer Link Active */

Definition at line 476 of file pci_regs.h.

#define PCI_EXP_LNKSTA_LABS   0x8000 /* Link Autonomous Bandwidth Status */

Definition at line 478 of file pci_regs.h.

#define PCI_EXP_LNKSTA_LBMS   0x4000 /* Link Bandwidth Management Status */

Definition at line 477 of file pci_regs.h.

#define PCI_EXP_LNKSTA_LT   0x0800 /* Link Training */

Definition at line 474 of file pci_regs.h.

#define PCI_EXP_LNKSTA_NLW   0x03f0 /* Nogotiated Link Width */

Definition at line 472 of file pci_regs.h.

#define PCI_EXP_LNKSTA_NLW_SHIFT   4 /* start of NLW mask in link status */

Definition at line 473 of file pci_regs.h.

#define PCI_EXP_LNKSTA_SLC   0x1000 /* Slot Clock Configuration */

Definition at line 475 of file pci_regs.h.

#define PCI_EXP_LTR_EN   0x400 /* Latency tolerance reporting */

Definition at line 541 of file pci_regs.h.

#define PCI_EXP_OBFF_MASK   0xc0000 /* OBFF support mechanism */

Definition at line 534 of file pci_regs.h.

#define PCI_EXP_OBFF_MSG   0x40000 /* New message signaling */

Definition at line 535 of file pci_regs.h.

#define PCI_EXP_OBFF_MSGA_EN   0x2000 /* OBFF enable with Message type A */

Definition at line 542 of file pci_regs.h.

#define PCI_EXP_OBFF_MSGB_EN   0x4000 /* OBFF enable with Message type B */

Definition at line 543 of file pci_regs.h.

#define PCI_EXP_OBFF_WAKE   0x80000 /* Re-use WAKE# for OBFF */

Definition at line 536 of file pci_regs.h.

#define PCI_EXP_OBFF_WAKE_EN   0x6000 /* OBFF using WAKE# signaling */

Definition at line 544 of file pci_regs.h.

#define PCI_EXP_RTCAP   30 /* Root Capabilities */

Definition at line 521 of file pci_regs.h.

#define PCI_EXP_RTCTL   28 /* Root Control */

Definition at line 515 of file pci_regs.h.

#define PCI_EXP_RTCTL_CRSSVE   0x10 /* CRS Software Visibility Enable */

Definition at line 520 of file pci_regs.h.

#define PCI_EXP_RTCTL_PMEIE   0x08 /* PME Interrupt Enable */

Definition at line 519 of file pci_regs.h.

#define PCI_EXP_RTCTL_SECEE   0x01 /* System Error on Correctable Error */

Definition at line 516 of file pci_regs.h.

#define PCI_EXP_RTCTL_SEFEE   0x04 /* System Error on Fatal Error */

Definition at line 518 of file pci_regs.h.

#define PCI_EXP_RTCTL_SENFEE   0x02 /* System Error on Non-Fatal Error */

Definition at line 517 of file pci_regs.h.

#define PCI_EXP_RTSTA   32 /* Root Status */

Definition at line 522 of file pci_regs.h.

#define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */

Definition at line 524 of file pci_regs.h.

#define PCI_EXP_RTSTA_PME   0x10000 /* PME status */

Definition at line 523 of file pci_regs.h.

#define PCI_EXP_SLTCAP   20 /* Slot Capabilities */

Definition at line 480 of file pci_regs.h.

#define PCI_EXP_SLTCAP_ABP   0x00000001 /* Attention Button Present */

Definition at line 481 of file pci_regs.h.

#define PCI_EXP_SLTCAP_AIP   0x00000008 /* Attention Indicator Present */

Definition at line 484 of file pci_regs.h.

#define PCI_EXP_SLTCAP_EIP   0x00020000 /* Electromechanical Interlock Present */

Definition at line 490 of file pci_regs.h.

#define PCI_EXP_SLTCAP_HPC   0x00000040 /* Hot-Plug Capable */

Definition at line 487 of file pci_regs.h.

#define PCI_EXP_SLTCAP_HPS   0x00000020 /* Hot-Plug Surprise */

Definition at line 486 of file pci_regs.h.

#define PCI_EXP_SLTCAP_MRLSP   0x00000004 /* MRL Sensor Present */

Definition at line 483 of file pci_regs.h.

#define PCI_EXP_SLTCAP_NCCS   0x00040000 /* No Command Completed Support */

Definition at line 491 of file pci_regs.h.

#define PCI_EXP_SLTCAP_PCP   0x00000002 /* Power Controller Present */

Definition at line 482 of file pci_regs.h.

#define PCI_EXP_SLTCAP_PIP   0x00000010 /* Power Indicator Present */

Definition at line 485 of file pci_regs.h.

#define PCI_EXP_SLTCAP_PSN   0xfff80000 /* Physical Slot Number */

Definition at line 492 of file pci_regs.h.

#define PCI_EXP_SLTCAP_SPLS   0x00018000 /* Slot Power Limit Scale */

Definition at line 489 of file pci_regs.h.

#define PCI_EXP_SLTCAP_SPLV   0x00007f80 /* Slot Power Limit Value */

Definition at line 488 of file pci_regs.h.

#define PCI_EXP_SLTCTL   24 /* Slot Control */

Definition at line 493 of file pci_regs.h.

#define PCI_EXP_SLTCTL2   56 /* Slot Control 2 */

Definition at line 553 of file pci_regs.h.

#define PCI_EXP_SLTCTL_ABPE   0x0001 /* Attention Button Pressed Enable */

Definition at line 494 of file pci_regs.h.

#define PCI_EXP_SLTCTL_AIC   0x00c0 /* Attention Indicator Control */

Definition at line 500 of file pci_regs.h.

#define PCI_EXP_SLTCTL_CCIE   0x0010 /* Command Completed Interrupt Enable */

Definition at line 498 of file pci_regs.h.

#define PCI_EXP_SLTCTL_DLLSCE   0x1000 /* Data Link Layer State Changed Enable */

Definition at line 504 of file pci_regs.h.

#define PCI_EXP_SLTCTL_EIC   0x0800 /* Electromechanical Interlock Control */

Definition at line 503 of file pci_regs.h.

#define PCI_EXP_SLTCTL_HPIE   0x0020 /* Hot-Plug Interrupt Enable */

Definition at line 499 of file pci_regs.h.

#define PCI_EXP_SLTCTL_MRLSCE   0x0004 /* MRL Sensor Changed Enable */

Definition at line 496 of file pci_regs.h.

#define PCI_EXP_SLTCTL_PCC   0x0400 /* Power Controller Control */

Definition at line 502 of file pci_regs.h.

#define PCI_EXP_SLTCTL_PDCE   0x0008 /* Presence Detect Changed Enable */

Definition at line 497 of file pci_regs.h.

#define PCI_EXP_SLTCTL_PFDE   0x0002 /* Power Fault Detected Enable */

Definition at line 495 of file pci_regs.h.

#define PCI_EXP_SLTCTL_PIC   0x0300 /* Power Indicator Control */

Definition at line 501 of file pci_regs.h.

#define PCI_EXP_SLTSTA   26 /* Slot Status */

Definition at line 505 of file pci_regs.h.

#define PCI_EXP_SLTSTA_ABP   0x0001 /* Attention Button Pressed */

Definition at line 506 of file pci_regs.h.

#define PCI_EXP_SLTSTA_CC   0x0010 /* Command Completed */

Definition at line 510 of file pci_regs.h.

#define PCI_EXP_SLTSTA_DLLSC   0x0100 /* Data Link Layer State Changed */

Definition at line 514 of file pci_regs.h.

#define PCI_EXP_SLTSTA_EIS   0x0080 /* Electromechanical Interlock Status */

Definition at line 513 of file pci_regs.h.

#define PCI_EXP_SLTSTA_MRLSC   0x0004 /* MRL Sensor Changed */

Definition at line 508 of file pci_regs.h.

#define PCI_EXP_SLTSTA_MRLSS   0x0020 /* MRL Sensor State */

Definition at line 511 of file pci_regs.h.

#define PCI_EXP_SLTSTA_PDC   0x0008 /* Presence Detect Changed */

Definition at line 509 of file pci_regs.h.

#define PCI_EXP_SLTSTA_PDS   0x0040 /* Presence Detect State */

Definition at line 512 of file pci_regs.h.

#define PCI_EXP_SLTSTA_PFD   0x0002 /* Power Fault Detected */

Definition at line 507 of file pci_regs.h.

#define PCI_EXP_TYPE_DOWNSTREAM   0x6 /* Downstream Port */

Definition at line 406 of file pci_regs.h.

#define PCI_EXP_TYPE_ENDPOINT   0x0 /* Express Endpoint */

Definition at line 402 of file pci_regs.h.

#define PCI_EXP_TYPE_LEG_END   0x1 /* Legacy Endpoint */

Definition at line 403 of file pci_regs.h.

#define PCI_EXP_TYPE_PCI_BRIDGE   0x7 /* PCI/PCI-X Bridge */

Definition at line 407 of file pci_regs.h.

#define PCI_EXP_TYPE_PCIE_BRIDGE   0x8 /* PCI/PCI-X to PCIE Bridge */

Definition at line 408 of file pci_regs.h.

#define PCI_EXP_TYPE_RC_EC   0xa /* Root Complex Event Collector */

Definition at line 410 of file pci_regs.h.

#define PCI_EXP_TYPE_RC_END   0x9 /* Root Complex Integrated Endpoint */

Definition at line 409 of file pci_regs.h.

#define PCI_EXP_TYPE_ROOT_PORT   0x4 /* Root Port */

Definition at line 404 of file pci_regs.h.

#define PCI_EXP_TYPE_UPSTREAM   0x5 /* Upstream Port */

Definition at line 405 of file pci_regs.h.

#define PCI_EXT_CAP_ARI_SIZEOF   8

Definition at line 730 of file pci_regs.h.

#define PCI_EXT_CAP_ATS_SIZEOF   8

Definition at line 740 of file pci_regs.h.

#define PCI_EXT_CAP_DSN_SIZEOF   12

Definition at line 589 of file pci_regs.h.

#define PCI_EXT_CAP_ID (   header)    (header & 0x0000ffff)

Definition at line 556 of file pci_regs.h.

#define PCI_EXT_CAP_ID_ACS   0x0D /* Access Control Services */

Definition at line 572 of file pci_regs.h.

#define PCI_EXT_CAP_ID_AMD_XXX   0x14 /* reserved for AMD */

Definition at line 579 of file pci_regs.h.

#define PCI_EXT_CAP_ID_ARI   0x0E /* Alternate Routing ID */

Definition at line 573 of file pci_regs.h.

#define PCI_EXT_CAP_ID_ATS   0x0F /* Address Translation Services */

Definition at line 574 of file pci_regs.h.

#define PCI_EXT_CAP_ID_CAC   0x0C /* Config Access - obsolete */

Definition at line 571 of file pci_regs.h.

#define PCI_EXT_CAP_ID_DPA   0x16 /* dynamic power alloc */

Definition at line 581 of file pci_regs.h.

#define PCI_EXT_CAP_ID_DSN   0x03 /* Device Serial Number */

Definition at line 562 of file pci_regs.h.

#define PCI_EXT_CAP_ID_ERR   0x01 /* Advanced Error Reporting */

Definition at line 560 of file pci_regs.h.

#define PCI_EXT_CAP_ID_LTR   0x18 /* latency tolerance reporting */

Definition at line 583 of file pci_regs.h.

#define PCI_EXT_CAP_ID_MAX   PCI_EXT_CAP_ID_PASID

Definition at line 587 of file pci_regs.h.

#define PCI_EXT_CAP_ID_MCAST   0x12 /* Multicast */

Definition at line 577 of file pci_regs.h.

#define PCI_EXT_CAP_ID_MFVC   0x08 /* Multi-Function VC Capability */

Definition at line 567 of file pci_regs.h.

#define PCI_EXT_CAP_ID_MRIOV   0x11 /* Multi Root I/O Virtualization */

Definition at line 576 of file pci_regs.h.

#define PCI_EXT_CAP_ID_PASID   0x1B /* Process Address Space ID */

Definition at line 586 of file pci_regs.h.

#define PCI_EXT_CAP_ID_PMUX   0x1A /* Protocol Multiplexing */

Definition at line 585 of file pci_regs.h.

#define PCI_EXT_CAP_ID_PRI   0x13 /* Page Request Interface */

Definition at line 578 of file pci_regs.h.

#define PCI_EXT_CAP_ID_PWR   0x04 /* Power Budgeting */

Definition at line 563 of file pci_regs.h.

#define PCI_EXT_CAP_ID_RCEC   0x07 /* Root Complex Event Collector */

Definition at line 566 of file pci_regs.h.

#define PCI_EXT_CAP_ID_RCILC   0x06 /* Root Complex Internal Link Control */

Definition at line 565 of file pci_regs.h.

#define PCI_EXT_CAP_ID_RCLD   0x05 /* Root Complex Link Declaration */

Definition at line 564 of file pci_regs.h.

#define PCI_EXT_CAP_ID_RCRB   0x0A /* Root Complex RB? */

Definition at line 569 of file pci_regs.h.

#define PCI_EXT_CAP_ID_REBAR   0x15 /* resizable BAR */

Definition at line 580 of file pci_regs.h.

#define PCI_EXT_CAP_ID_SECPCI   0x19 /* Secondary PCIe */

Definition at line 584 of file pci_regs.h.

#define PCI_EXT_CAP_ID_SRIOV   0x10 /* Single Root I/O Virtualization */

Definition at line 575 of file pci_regs.h.

#define PCI_EXT_CAP_ID_TPH   0x17 /* TPH request */

Definition at line 582 of file pci_regs.h.

#define PCI_EXT_CAP_ID_VC   0x02 /* Virtual Channel Capability */

Definition at line 561 of file pci_regs.h.

#define PCI_EXT_CAP_ID_VC9   0x09 /* same as _VC */

Definition at line 568 of file pci_regs.h.

#define PCI_EXT_CAP_ID_VNDR   0x0B /* Vendor Specific */

Definition at line 570 of file pci_regs.h.

#define PCI_EXT_CAP_LTR_SIZEOF   8

Definition at line 801 of file pci_regs.h.

#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF   40

Definition at line 590 of file pci_regs.h.

#define PCI_EXT_CAP_NEXT (   header)    ((header >> 20) & 0xffc)

Definition at line 558 of file pci_regs.h.

#define PCI_EXT_CAP_PASID_SIZEOF   8

Definition at line 762 of file pci_regs.h.

#define PCI_EXT_CAP_PRI_SIZEOF   16

Definition at line 752 of file pci_regs.h.

#define PCI_EXT_CAP_PWR_SIZEOF   16

Definition at line 679 of file pci_regs.h.

#define PCI_EXT_CAP_SRIOV_SIZEOF   64

Definition at line 794 of file pci_regs.h.

#define PCI_EXT_CAP_VER (   header)    ((header >> 16) & 0xf)

Definition at line 557 of file pci_regs.h.

#define PCI_HEADER_TYPE   0x0e /* 8 bits */

Definition at line 69 of file pci_regs.h.

#define PCI_HEADER_TYPE_BRIDGE   1

Definition at line 71 of file pci_regs.h.

#define PCI_HEADER_TYPE_CARDBUS   2

Definition at line 72 of file pci_regs.h.

#define PCI_HEADER_TYPE_NORMAL   0

Definition at line 70 of file pci_regs.h.

#define PCI_INTERRUPT_LINE   0x3c /* 8 bits */

Definition at line 114 of file pci_regs.h.

#define PCI_INTERRUPT_PIN   0x3d /* 8 bits */

Definition at line 115 of file pci_regs.h.

#define PCI_IO_1K_RANGE_MASK   (~0x03UL) /* Intel 1K I/O windows */

Definition at line 130 of file pci_regs.h.

#define PCI_IO_BASE   0x1c /* I/O range behind the bridge */

Definition at line 124 of file pci_regs.h.

#define PCI_IO_BASE_UPPER16   0x30 /* Upper half of I/O addresses */

Definition at line 144 of file pci_regs.h.

#define PCI_IO_LIMIT   0x1d

Definition at line 125 of file pci_regs.h.

#define PCI_IO_LIMIT_UPPER16   0x32

Definition at line 145 of file pci_regs.h.

#define PCI_IO_RANGE_MASK   (~0x0fUL) /* Standard 4K I/O windows */

Definition at line 129 of file pci_regs.h.

#define PCI_IO_RANGE_TYPE_16   0x00

Definition at line 127 of file pci_regs.h.

#define PCI_IO_RANGE_TYPE_32   0x01

Definition at line 128 of file pci_regs.h.

#define PCI_IO_RANGE_TYPE_MASK   0x0fUL /* I/O bridging type */

Definition at line 126 of file pci_regs.h.

#define PCI_LATENCY_TIMER   0x0d /* 8 bits */

Definition at line 68 of file pci_regs.h.

#define PCI_LTR_MAX_NOSNOOP_LAT   0x6

Definition at line 797 of file pci_regs.h.

#define PCI_LTR_MAX_SNOOP_LAT   0x4

Definition at line 796 of file pci_regs.h.

#define PCI_LTR_SCALE_MASK   0x00001c00

Definition at line 799 of file pci_regs.h.

#define PCI_LTR_SCALE_SHIFT   10

Definition at line 800 of file pci_regs.h.

#define PCI_LTR_VALUE_MASK   0x000003ff

Definition at line 798 of file pci_regs.h.

#define PCI_MAX_LAT   0x3f /* 8 bits */

Definition at line 117 of file pci_regs.h.

#define PCI_MEMORY_BASE   0x20 /* Memory range behind */

Definition at line 132 of file pci_regs.h.

#define PCI_MEMORY_LIMIT   0x22

Definition at line 133 of file pci_regs.h.

#define PCI_MEMORY_RANGE_MASK   (~0x0fUL)

Definition at line 135 of file pci_regs.h.

#define PCI_MEMORY_RANGE_TYPE_MASK   0x0fUL

Definition at line 134 of file pci_regs.h.

#define PCI_MIN_GNT   0x3e /* 8 bits */

Definition at line 116 of file pci_regs.h.

#define PCI_MSI_ADDRESS_HI   8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */

Definition at line 303 of file pci_regs.h.

#define PCI_MSI_ADDRESS_LO   4 /* Lower 32 bits */

Definition at line 302 of file pci_regs.h.

#define PCI_MSI_DATA_32   8 /* 16 bits of data for 32-bit devices */

Definition at line 304 of file pci_regs.h.

#define PCI_MSI_DATA_64   12 /* 16 bits of data for 64-bit devices */

Definition at line 307 of file pci_regs.h.

#define PCI_MSI_FLAGS   2 /* Various flags */

Definition at line 295 of file pci_regs.h.

#define PCI_MSI_FLAGS_64BIT   0x80 /* 64-bit addresses allowed */

Definition at line 296 of file pci_regs.h.

#define PCI_MSI_FLAGS_ENABLE   0x01 /* MSI feature enabled */

Definition at line 299 of file pci_regs.h.

#define PCI_MSI_FLAGS_MASKBIT   0x100 /* 64-bit mask bits allowed */

Definition at line 300 of file pci_regs.h.

#define PCI_MSI_FLAGS_QMASK   0x0e /* Maximum queue size available */

Definition at line 298 of file pci_regs.h.

#define PCI_MSI_FLAGS_QSIZE   0x70 /* Message queue size configured */

Definition at line 297 of file pci_regs.h.

#define PCI_MSI_MASK_32   12 /* Mask bits register for 32-bit devices */

Definition at line 305 of file pci_regs.h.

#define PCI_MSI_MASK_64   16 /* Mask bits register for 64-bit devices */

Definition at line 308 of file pci_regs.h.

#define PCI_MSI_PENDING_32   16 /* Pending intrs for 32-bit devices */

Definition at line 306 of file pci_regs.h.

#define PCI_MSI_PENDING_64   20 /* Pending intrs for 64-bit devices */

Definition at line 309 of file pci_regs.h.

#define PCI_MSI_RFU   3 /* Rest of capability flags */

Definition at line 301 of file pci_regs.h.

#define PCI_MSIX_ENTRY_CTRL_MASKBIT   1

Definition at line 327 of file pci_regs.h.

#define PCI_MSIX_ENTRY_DATA   8

Definition at line 325 of file pci_regs.h.

#define PCI_MSIX_ENTRY_LOWER_ADDR   0

Definition at line 323 of file pci_regs.h.

#define PCI_MSIX_ENTRY_SIZE   16

Definition at line 322 of file pci_regs.h.

#define PCI_MSIX_ENTRY_UPPER_ADDR   4

Definition at line 324 of file pci_regs.h.

#define PCI_MSIX_ENTRY_VECTOR_CTRL   12

Definition at line 326 of file pci_regs.h.

#define PCI_MSIX_FLAGS   2

Definition at line 312 of file pci_regs.h.

#define PCI_MSIX_FLAGS_BIRMASK   (7 << 0)

Definition at line 318 of file pci_regs.h.

#define PCI_MSIX_FLAGS_ENABLE   (1 << 15)

Definition at line 314 of file pci_regs.h.

#define PCI_MSIX_FLAGS_MASKALL   (1 << 14)

Definition at line 315 of file pci_regs.h.

#define PCI_MSIX_FLAGS_QSIZE   0x7FF

Definition at line 313 of file pci_regs.h.

#define PCI_MSIX_PBA   8

Definition at line 317 of file pci_regs.h.

#define PCI_MSIX_TABLE   4

Definition at line 316 of file pci_regs.h.

#define PCI_PASID_CAP   0x04 /* PASID feature register */

Definition at line 755 of file pci_regs.h.

#define PCI_PASID_CAP_EXEC   0x02 /* Exec permissions Supported */

Definition at line 756 of file pci_regs.h.

#define PCI_PASID_CAP_PRIV   0x04 /* Priviledge Mode Supported */

Definition at line 757 of file pci_regs.h.

#define PCI_PASID_CTRL   0x06 /* PASID control register */

Definition at line 758 of file pci_regs.h.

#define PCI_PASID_CTRL_ENABLE   0x01 /* Enable bit */

Definition at line 759 of file pci_regs.h.

#define PCI_PASID_CTRL_EXEC   0x02 /* Exec permissions Enable */

Definition at line 760 of file pci_regs.h.

#define PCI_PASID_CTRL_PRIV   0x04 /* Priviledge Mode Enable */

Definition at line 761 of file pci_regs.h.

#define PCI_PM_BPCC_ENABLE   0x80 /* Bus power/clock control enable (??) */

Definition at line 251 of file pci_regs.h.

#define PCI_PM_CAP_AUX_POWER   0x01C0 /* Auxiliary power support mask */

Definition at line 231 of file pci_regs.h.

#define PCI_PM_CAP_D1   0x0200 /* D1 power state support */

Definition at line 232 of file pci_regs.h.

#define PCI_PM_CAP_D2   0x0400 /* D2 power state support */

Definition at line 233 of file pci_regs.h.

#define PCI_PM_CAP_DSI   0x0020 /* Device specific initialization */

Definition at line 230 of file pci_regs.h.

#define PCI_PM_CAP_PME   0x0800 /* PME pin supported */

Definition at line 234 of file pci_regs.h.

#define PCI_PM_CAP_PME_CLOCK   0x0008 /* PME clock required */

Definition at line 228 of file pci_regs.h.

#define PCI_PM_CAP_PME_D0   0x0800 /* PME# from D0 */

Definition at line 236 of file pci_regs.h.

#define PCI_PM_CAP_PME_D1   0x1000 /* PME# from D1 */

Definition at line 237 of file pci_regs.h.

#define PCI_PM_CAP_PME_D2   0x2000 /* PME# from D2 */

Definition at line 238 of file pci_regs.h.

#define PCI_PM_CAP_PME_D3   0x4000 /* PME# from D3 (hot) */

Definition at line 239 of file pci_regs.h.

#define PCI_PM_CAP_PME_D3cold   0x8000 /* PME# from D3 (cold) */

Definition at line 240 of file pci_regs.h.

#define PCI_PM_CAP_PME_MASK   0xF800 /* PME Mask of all supported states */

Definition at line 235 of file pci_regs.h.

#define PCI_PM_CAP_PME_SHIFT   11 /* Start of the PME Mask in PMC */

Definition at line 241 of file pci_regs.h.

#define PCI_PM_CAP_RESERVED   0x0010 /* Reserved field */

Definition at line 229 of file pci_regs.h.

#define PCI_PM_CAP_VER_MASK   0x0007 /* Version */

Definition at line 227 of file pci_regs.h.

#define PCI_PM_CTRL   4 /* PM control and status register */

Definition at line 242 of file pci_regs.h.

#define PCI_PM_CTRL_DATA_SCALE_MASK   0x6000 /* Data scale (??) */

Definition at line 247 of file pci_regs.h.

#define PCI_PM_CTRL_DATA_SEL_MASK   0x1e00 /* Data select (??) */

Definition at line 246 of file pci_regs.h.

#define PCI_PM_CTRL_NO_SOFT_RESET   0x0008 /* No reset for D3hot->D0 */

Definition at line 244 of file pci_regs.h.

#define PCI_PM_CTRL_PME_ENABLE   0x0100 /* PME pin enable */

Definition at line 245 of file pci_regs.h.

#define PCI_PM_CTRL_PME_STATUS   0x8000 /* PME pin status */

Definition at line 248 of file pci_regs.h.

#define PCI_PM_CTRL_STATE_MASK   0x0003 /* Current power state (D0 to D3) */

Definition at line 243 of file pci_regs.h.

#define PCI_PM_DATA_REGISTER   7 /* (??) */

Definition at line 252 of file pci_regs.h.

#define PCI_PM_PMC   2 /* PM Capabilities Register */

Definition at line 226 of file pci_regs.h.

#define PCI_PM_PPB_B2_B3   0x40 /* Stop clock when in D3hot (??) */

Definition at line 250 of file pci_regs.h.

#define PCI_PM_PPB_EXTENSIONS   6 /* PPB support extensions (??) */

Definition at line 249 of file pci_regs.h.

#define PCI_PM_SIZEOF   8

Definition at line 253 of file pci_regs.h.

#define PCI_PREF_BASE_UPPER32   0x28 /* Upper half of prefetchable memory range */

Definition at line 142 of file pci_regs.h.

#define PCI_PREF_LIMIT_UPPER32   0x2c

Definition at line 143 of file pci_regs.h.

#define PCI_PREF_MEMORY_BASE   0x24 /* Prefetchable memory range behind */

Definition at line 136 of file pci_regs.h.

#define PCI_PREF_MEMORY_LIMIT   0x26

Definition at line 137 of file pci_regs.h.

#define PCI_PREF_RANGE_MASK   (~0x0fUL)

Definition at line 141 of file pci_regs.h.

#define PCI_PREF_RANGE_TYPE_32   0x00

Definition at line 139 of file pci_regs.h.

#define PCI_PREF_RANGE_TYPE_64   0x01

Definition at line 140 of file pci_regs.h.

#define PCI_PREF_RANGE_TYPE_MASK   0x0fUL

Definition at line 138 of file pci_regs.h.

#define PCI_PRI_ALLOC_REQ   0x0c /* PRI max reqs allowed */

Definition at line 751 of file pci_regs.h.

#define PCI_PRI_CTRL   0x04 /* PRI control register */

Definition at line 743 of file pci_regs.h.

#define PCI_PRI_CTRL_ENABLE   0x01 /* Enable */

Definition at line 744 of file pci_regs.h.

#define PCI_PRI_CTRL_RESET   0x02 /* Reset */

Definition at line 745 of file pci_regs.h.

#define PCI_PRI_MAX_REQ   0x08 /* PRI max reqs supported */

Definition at line 750 of file pci_regs.h.

#define PCI_PRI_STATUS   0x06 /* PRI status register */

Definition at line 746 of file pci_regs.h.

#define PCI_PRI_STATUS_RF   0x001 /* Response Failure */

Definition at line 747 of file pci_regs.h.

#define PCI_PRI_STATUS_STOPPED   0x100 /* PRI Stopped */

Definition at line 749 of file pci_regs.h.

#define PCI_PRI_STATUS_UPRGI   0x002 /* Unexpected PRG index */

Definition at line 748 of file pci_regs.h.

#define PCI_PRIMARY_BUS   0x18 /* Primary bus number */

Definition at line 120 of file pci_regs.h.

#define PCI_PWR_CAP   12 /* Capability */

Definition at line 677 of file pci_regs.h.

#define PCI_PWR_CAP_BUDGET (   x)    ((x) & 1) /* Included in system budget */

Definition at line 678 of file pci_regs.h.

#define PCI_PWR_DATA   8 /* Data Register */

Definition at line 670 of file pci_regs.h.

#define PCI_PWR_DATA_BASE (   x)    ((x) & 0xff) /* Base Power */

Definition at line 671 of file pci_regs.h.

#define PCI_PWR_DATA_PM_STATE (   x)    (((x) >> 13) & 3) /* PM State */

Definition at line 674 of file pci_regs.h.

#define PCI_PWR_DATA_PM_SUB (   x)    (((x) >> 10) & 7) /* PM Sub State */

Definition at line 673 of file pci_regs.h.

#define PCI_PWR_DATA_RAIL (   x)    (((x) >> 18) & 7) /* Power Rail */

Definition at line 676 of file pci_regs.h.

#define PCI_PWR_DATA_SCALE (   x)    (((x) >> 8) & 3) /* Data Scale */

Definition at line 672 of file pci_regs.h.

#define PCI_PWR_DATA_TYPE (   x)    (((x) >> 15) & 7) /* Type */

Definition at line 675 of file pci_regs.h.

#define PCI_PWR_DSR   4 /* Data Select Register */

Definition at line 669 of file pci_regs.h.

#define PCI_REBAR_CTRL   8 /* control register */

Definition at line 827 of file pci_regs.h.

#define PCI_REBAR_CTRL_NBAR_MASK   (7 << 5) /* mask for # bars */

Definition at line 828 of file pci_regs.h.

#define PCI_REBAR_CTRL_NBAR_SHIFT   5 /* shift for # bars */

Definition at line 829 of file pci_regs.h.

#define PCI_REVISION_ID   0x08 /* Revision ID */

Definition at line 63 of file pci_regs.h.

#define PCI_ROM_ADDRESS   0x30 /* Bits 31..11 are address, 10..1 reserved */

Definition at line 107 of file pci_regs.h.

#define PCI_ROM_ADDRESS1   0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */

Definition at line 148 of file pci_regs.h.

#define PCI_ROM_ADDRESS_ENABLE   0x01

Definition at line 108 of file pci_regs.h.

#define PCI_ROM_ADDRESS_MASK   (~0x7ffUL)

Definition at line 109 of file pci_regs.h.

#define PCI_SATA_REGS   4 /* SATA REGs specifier */

Definition at line 820 of file pci_regs.h.

#define PCI_SATA_REGS_INLINE   0xF /* REGS in config space */

Definition at line 822 of file pci_regs.h.

#define PCI_SATA_REGS_MASK   0xF /* location - BAR#/inline */

Definition at line 821 of file pci_regs.h.

#define PCI_SATA_SIZEOF_LONG   16

Definition at line 824 of file pci_regs.h.

#define PCI_SATA_SIZEOF_SHORT   8

Definition at line 823 of file pci_regs.h.

#define PCI_SEC_LATENCY_TIMER   0x1b /* Latency timer for secondary interface */

Definition at line 123 of file pci_regs.h.

#define PCI_SEC_STATUS   0x1e /* Secondary status register, only bit 14 used */

Definition at line 131 of file pci_regs.h.

#define PCI_SECONDARY_BUS   0x19 /* Secondary bus number */

Definition at line 121 of file pci_regs.h.

#define PCI_SID_CHASSIS_NR   3 /* Chassis Number */

Definition at line 291 of file pci_regs.h.

#define PCI_SID_ESR   2 /* Expansion Slot Register */

Definition at line 288 of file pci_regs.h.

#define PCI_SID_ESR_FIC   0x20 /* First In Chassis Flag */

Definition at line 290 of file pci_regs.h.

#define PCI_SID_ESR_NSLOTS   0x1f /* Number of expansion slots available */

Definition at line 289 of file pci_regs.h.

#define PCI_SRIOV_BAR   0x24 /* VF BAR0 */

Definition at line 785 of file pci_regs.h.

#define PCI_SRIOV_CAP   0x04 /* SR-IOV Capabilities */

Definition at line 765 of file pci_regs.h.

#define PCI_SRIOV_CAP_INTR (   x)    ((x) >> 21) /* Interrupt Message Number */

Definition at line 767 of file pci_regs.h.

#define PCI_SRIOV_CAP_VFM   0x01 /* VF Migration Capable */

Definition at line 766 of file pci_regs.h.

#define PCI_SRIOV_CTRL   0x08 /* SR-IOV Control */

Definition at line 768 of file pci_regs.h.

#define PCI_SRIOV_CTRL_ARI   0x10 /* ARI Capable Hierarchy */

Definition at line 773 of file pci_regs.h.

#define PCI_SRIOV_CTRL_INTR   0x04 /* VF Migration Interrupt Enable */

Definition at line 771 of file pci_regs.h.

#define PCI_SRIOV_CTRL_MSE   0x08 /* VF Memory Space Enable */

Definition at line 772 of file pci_regs.h.

#define PCI_SRIOV_CTRL_VFE   0x01 /* VF Enable */

Definition at line 769 of file pci_regs.h.

#define PCI_SRIOV_CTRL_VFM   0x02 /* VF Migration Enable */

Definition at line 770 of file pci_regs.h.

#define PCI_SRIOV_FUNC_LINK   0x12 /* Function Dependency Link */

Definition at line 779 of file pci_regs.h.

#define PCI_SRIOV_INITIAL_VF   0x0c /* Initial VFs */

Definition at line 776 of file pci_regs.h.

#define PCI_SRIOV_NUM_BARS   6 /* Number of VF BARs */

Definition at line 786 of file pci_regs.h.

#define PCI_SRIOV_NUM_VF   0x10 /* Number of VFs */

Definition at line 778 of file pci_regs.h.

#define PCI_SRIOV_STATUS   0x0a /* SR-IOV Status */

Definition at line 774 of file pci_regs.h.

#define PCI_SRIOV_STATUS_VFM   0x01 /* VF Migration Status */

Definition at line 775 of file pci_regs.h.

#define PCI_SRIOV_SUP_PGSIZE   0x1c /* Supported Page Sizes */

Definition at line 783 of file pci_regs.h.

#define PCI_SRIOV_SYS_PGSIZE   0x20 /* System Page Size */

Definition at line 784 of file pci_regs.h.

#define PCI_SRIOV_TOTAL_VF   0x0e /* Total VFs */

Definition at line 777 of file pci_regs.h.

#define PCI_SRIOV_VF_DID   0x1a /* VF Device ID */

Definition at line 782 of file pci_regs.h.

#define PCI_SRIOV_VF_OFFSET   0x14 /* First VF Offset */

Definition at line 780 of file pci_regs.h.

#define PCI_SRIOV_VF_STRIDE   0x16 /* Following VF Stride */

Definition at line 781 of file pci_regs.h.

#define PCI_SRIOV_VFM   0x3c /* VF Migration State Array Offset*/

Definition at line 787 of file pci_regs.h.

#define PCI_SRIOV_VFM_AV   0x3 /* Active.Available */

Definition at line 793 of file pci_regs.h.

#define PCI_SRIOV_VFM_BIR (   x)    ((x) & 7) /* State BIR */

Definition at line 788 of file pci_regs.h.

#define PCI_SRIOV_VFM_MI   0x1 /* Dormant.MigrateIn */

Definition at line 791 of file pci_regs.h.

#define PCI_SRIOV_VFM_MO   0x2 /* Active.MigrateOut */

Definition at line 792 of file pci_regs.h.

#define PCI_SRIOV_VFM_OFFSET (   x)    ((x) & ~7) /* State Offset */

Definition at line 789 of file pci_regs.h.

#define PCI_SRIOV_VFM_UA   0x0 /* Inactive.Unavailable */

Definition at line 790 of file pci_regs.h.

#define PCI_SSVID_DEVICE_ID   6 /* PCI-Bridge subsystem device id register */

Definition at line 395 of file pci_regs.h.

#define PCI_SSVID_VENDOR_ID   4 /* PCI-Bridge subsystem vendor id register */

Definition at line 394 of file pci_regs.h.

#define PCI_STATUS   0x06 /* 16 bits */

Definition at line 45 of file pci_regs.h.

#define PCI_STATUS_66MHZ   0x20 /* Support 66 Mhz PCI 2.1 bus */

Definition at line 48 of file pci_regs.h.

#define PCI_STATUS_CAP_LIST   0x10 /* Support Capability List */

Definition at line 47 of file pci_regs.h.

#define PCI_STATUS_DETECTED_PARITY   0x8000 /* Set on parity error */

Definition at line 60 of file pci_regs.h.

#define PCI_STATUS_DEVSEL_FAST   0x000

Definition at line 53 of file pci_regs.h.

#define PCI_STATUS_DEVSEL_MASK   0x600 /* DEVSEL timing */

Definition at line 52 of file pci_regs.h.

#define PCI_STATUS_DEVSEL_MEDIUM   0x200

Definition at line 54 of file pci_regs.h.

#define PCI_STATUS_DEVSEL_SLOW   0x400

Definition at line 55 of file pci_regs.h.

#define PCI_STATUS_FAST_BACK   0x80 /* Accept fast-back to back */

Definition at line 50 of file pci_regs.h.

#define PCI_STATUS_INTERRUPT   0x08 /* Interrupt status */

Definition at line 46 of file pci_regs.h.

#define PCI_STATUS_PARITY   0x100 /* Detected parity error */

Definition at line 51 of file pci_regs.h.

#define PCI_STATUS_REC_MASTER_ABORT   0x2000 /* Set on master abort */

Definition at line 58 of file pci_regs.h.

#define PCI_STATUS_REC_TARGET_ABORT   0x1000 /* Master ack of " */

Definition at line 57 of file pci_regs.h.

#define PCI_STATUS_SIG_SYSTEM_ERROR   0x4000 /* Set when we drive SERR */

Definition at line 59 of file pci_regs.h.

#define PCI_STATUS_SIG_TARGET_ABORT   0x800 /* Set on target abort */

Definition at line 56 of file pci_regs.h.

#define PCI_STATUS_UDF   0x40 /* Support User Definable Features [obsolete] */

Definition at line 49 of file pci_regs.h.

#define PCI_STD_HEADER_SIZEOF   64

Definition at line 29 of file pci_regs.h.

#define PCI_SUBORDINATE_BUS   0x1a /* Highest bus number behind the bridge */

Definition at line 122 of file pci_regs.h.

#define PCI_SUBSYSTEM_ID   0x2e

Definition at line 106 of file pci_regs.h.

#define PCI_SUBSYSTEM_VENDOR_ID   0x2c

Definition at line 105 of file pci_regs.h.

#define PCI_TPH_BASE_SIZEOF   12 /* size with no st table */

Definition at line 844 of file pci_regs.h.

#define PCI_TPH_CAP   4 /* capability register */

Definition at line 837 of file pci_regs.h.

#define PCI_TPH_CAP_LOC_MASK   0x600 /* location mask */

Definition at line 838 of file pci_regs.h.

#define PCI_TPH_CAP_ST_MASK   0x07FF0000 /* st table mask */

Definition at line 842 of file pci_regs.h.

#define PCI_TPH_CAP_ST_SHIFT   16 /* st table shift */

Definition at line 843 of file pci_regs.h.

#define PCI_TPH_LOC_CAP   0x200 /* in capability */

Definition at line 840 of file pci_regs.h.

#define PCI_TPH_LOC_MSIX   0x400 /* in MSI-X */

Definition at line 841 of file pci_regs.h.

#define PCI_TPH_LOC_NONE   0x000 /* no location */

Definition at line 839 of file pci_regs.h.

#define PCI_VC_PORT_CTRL   12

Definition at line 660 of file pci_regs.h.

#define PCI_VC_PORT_REG1   4

Definition at line 654 of file pci_regs.h.

#define PCI_VC_PORT_REG2   8

Definition at line 656 of file pci_regs.h.

#define PCI_VC_PORT_STATUS   14

Definition at line 661 of file pci_regs.h.

#define PCI_VC_REG1_EVCC   0x7 /* extended vc count */

Definition at line 655 of file pci_regs.h.

#define PCI_VC_REG2_128_PHASE   0x8

Definition at line 659 of file pci_regs.h.

#define PCI_VC_REG2_32_PHASE   0x2

Definition at line 657 of file pci_regs.h.

#define PCI_VC_REG2_64_PHASE   0x4

Definition at line 658 of file pci_regs.h.

#define PCI_VC_RES_CAP   16

Definition at line 662 of file pci_regs.h.

#define PCI_VC_RES_CTRL   20

Definition at line 663 of file pci_regs.h.

#define PCI_VC_RES_STATUS   26

Definition at line 664 of file pci_regs.h.

#define PCI_VENDOR_ID   0x00 /* 16 bits */

Definition at line 30 of file pci_regs.h.

#define PCI_VNDR_HEADER   4 /* Vendor-Specific Header */

Definition at line 682 of file pci_regs.h.

#define PCI_VNDR_HEADER_ID (   x)    ((x) & 0xffff)

Definition at line 683 of file pci_regs.h.

#define PCI_VNDR_HEADER_LEN (   x)    (((x) >> 20) & 0xfff)

Definition at line 685 of file pci_regs.h.

#define PCI_VNDR_HEADER_REV (   x)    (((x) >> 16) & 0xf)

Definition at line 684 of file pci_regs.h.

#define PCI_VPD_ADDR   2 /* Address to access (15 bits!) */

Definition at line 280 of file pci_regs.h.

#define PCI_VPD_ADDR_F   0x8000 /* Write 0, 1 indicates completion */

Definition at line 282 of file pci_regs.h.

#define PCI_VPD_ADDR_MASK   0x7fff /* Address mask */

Definition at line 281 of file pci_regs.h.

#define PCI_VPD_DATA   4 /* 32-bits of data returned here */

Definition at line 283 of file pci_regs.h.

#define PCI_VSEC_HDR   4 /* extended cap - vendor specific */

Definition at line 816 of file pci_regs.h.

#define PCI_VSEC_HDR_LEN_SHIFT   20 /* shift for length field */

Definition at line 817 of file pci_regs.h.

#define PCI_X_CMD   2 /* Modes & Features */

Definition at line 354 of file pci_regs.h.

#define PCI_X_CMD_DPERR_E   0x0001 /* Data Parity Error Recovery Enable */

Definition at line 355 of file pci_regs.h.

#define PCI_X_CMD_ERO   0x0002 /* Enable Relaxed Ordering */

Definition at line 356 of file pci_regs.h.

#define PCI_X_CMD_MAX_READ   0x000c /* Max Memory Read Byte Count */

Definition at line 361 of file pci_regs.h.

#define PCI_X_CMD_MAX_SPLIT   0x0070 /* Max Outstanding Split Transactions */

Definition at line 371 of file pci_regs.h.

#define PCI_X_CMD_READ_1K   0x0004 /* 1Kbyte maximum read byte count */

Definition at line 358 of file pci_regs.h.

#define PCI_X_CMD_READ_2K   0x0008 /* 2Kbyte maximum read byte count */

Definition at line 359 of file pci_regs.h.

#define PCI_X_CMD_READ_4K   0x000c /* 4Kbyte maximum read byte count */

Definition at line 360 of file pci_regs.h.

#define PCI_X_CMD_READ_512   0x0000 /* 512 byte maximum read byte count */

Definition at line 357 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_1   0x0000 /* Max 1 */

Definition at line 363 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_12   0x0050 /* Max 12 */

Definition at line 368 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_16   0x0060 /* Max 16 */

Definition at line 369 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_2   0x0010 /* Max 2 */

Definition at line 364 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_3   0x0020 /* Max 3 */

Definition at line 365 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_32   0x0070 /* Max 32 */

Definition at line 370 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_4   0x0030 /* Max 4 */

Definition at line 366 of file pci_regs.h.

#define PCI_X_CMD_SPLIT_8   0x0040 /* Max 8 */

Definition at line 367 of file pci_regs.h.

#define PCI_X_CMD_VERSION (   x)    (((x) >> 12) & 3) /* Version */

Definition at line 372 of file pci_regs.h.

#define PCI_X_ECC_CSR   8 /* ECC control and status */

Definition at line 387 of file pci_regs.h.

#define PCI_X_STATUS   4 /* PCI-X capabilities */

Definition at line 373 of file pci_regs.h.

#define PCI_X_STATUS_133MHZ   0x00020000 /* 133 MHz capable */

Definition at line 377 of file pci_regs.h.

#define PCI_X_STATUS_266MHZ   0x40000000 /* 266 MHz capable */

Definition at line 385 of file pci_regs.h.

#define PCI_X_STATUS_533MHZ   0x80000000 /* 533 MHz capable */

Definition at line 386 of file pci_regs.h.

#define PCI_X_STATUS_64BIT   0x00010000 /* 64-bit device */

Definition at line 376 of file pci_regs.h.

#define PCI_X_STATUS_BUS   0x0000ff00 /* A copy of bus nr */

Definition at line 375 of file pci_regs.h.

#define PCI_X_STATUS_COMPLEX   0x00100000 /* Device Complexity */

Definition at line 380 of file pci_regs.h.

#define PCI_X_STATUS_DEVFN   0x000000ff /* A copy of devfn */

Definition at line 374 of file pci_regs.h.

#define PCI_X_STATUS_MAX_CUM   0x1c000000 /* Designed Max Cumulative Read Size */

Definition at line 383 of file pci_regs.h.

#define PCI_X_STATUS_MAX_READ   0x00600000 /* Designed Max Memory Read Count */

Definition at line 381 of file pci_regs.h.

#define PCI_X_STATUS_MAX_SPLIT   0x03800000 /* Designed Max Outstanding Split Transactions */

Definition at line 382 of file pci_regs.h.

#define PCI_X_STATUS_SPL_DISC   0x00040000 /* Split Completion Discarded */

Definition at line 378 of file pci_regs.h.

#define PCI_X_STATUS_SPL_ERR   0x20000000 /* Rcvd Split Completion Error Msg */

Definition at line 384 of file pci_regs.h.

#define PCI_X_STATUS_UNX_SPL   0x00080000 /* Unexpected Split Completion */

Definition at line 379 of file pci_regs.h.

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