at91_dbgu.h File Reference

Go to the source code of this file.

Macros
#define	dbgu_readl(dbgu, field)   __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
#define	AT91_DBGU_CR   (0x00) /* Control Register */
#define	AT91_DBGU_MR   (0x04) /* Mode Register */
#define	AT91_DBGU_IER   (0x08) /* Interrupt Enable Register */
#define	AT91_DBGU_TXRDY   (1 << 1) /* Transmitter Ready */
#define	AT91_DBGU_TXEMPTY   (1 << 9) /* Transmitter Empty */
#define	AT91_DBGU_IDR   (0x0c) /* Interrupt Disable Register */
#define	AT91_DBGU_IMR   (0x10) /* Interrupt Mask Register */
#define	AT91_DBGU_SR   (0x14) /* Status Register */
#define	AT91_DBGU_RHR   (0x18) /* Receiver Holding Register */
#define	AT91_DBGU_THR   (0x1c) /* Transmitter Holding Register */
#define	AT91_DBGU_BRGR   (0x20) /* Baud Rate Generator Register */
#define	AT91_DBGU_CIDR   (0x40) /* Chip ID Register */
#define	AT91_DBGU_EXID   (0x44) /* Chip ID Extension Register */
#define	AT91_DBGU_FNR   (0x48) /* Force NTRST Register [SAM9 only] */
#define	AT91_DBGU_FNTRST   (1 << 0) /* Force NTRST */
#define	AT91_CIDR_VERSION   (0x1f << 0) /* Version of the Device */
#define	AT91_CIDR_EPROC   (7 << 5) /* Embedded Processor */
#define	AT91_CIDR_NVPSIZ   (0xf << 8) /* Nonvolatile Program Memory Size */
#define	AT91_CIDR_NVPSIZ2   (0xf << 12) /* Second Nonvolatile Program Memory Size */
#define	AT91_CIDR_SRAMSIZ   (0xf << 16) /* Internal SRAM Size */
#define	AT91_CIDR_SRAMSIZ_1K   (1 << 16)
#define	AT91_CIDR_SRAMSIZ_2K   (2 << 16)
#define	AT91_CIDR_SRAMSIZ_112K   (4 << 16)
#define	AT91_CIDR_SRAMSIZ_4K   (5 << 16)
#define	AT91_CIDR_SRAMSIZ_80K   (6 << 16)
#define	AT91_CIDR_SRAMSIZ_160K   (7 << 16)
#define	AT91_CIDR_SRAMSIZ_8K   (8 << 16)
#define	AT91_CIDR_SRAMSIZ_16K   (9 << 16)
#define	AT91_CIDR_SRAMSIZ_32K   (10 << 16)
#define	AT91_CIDR_SRAMSIZ_64K   (11 << 16)
#define	AT91_CIDR_SRAMSIZ_128K   (12 << 16)
#define	AT91_CIDR_SRAMSIZ_256K   (13 << 16)
#define	AT91_CIDR_SRAMSIZ_96K   (14 << 16)
#define	AT91_CIDR_SRAMSIZ_512K   (15 << 16)
#define	AT91_CIDR_ARCH   (0xff << 20) /* Architecture Identifier */
#define	AT91_CIDR_NVPTYP   (7 << 28) /* Nonvolatile Program Memory Type */
#define	AT91_CIDR_EXT   (1 << 31) /* Extension Flag */

Macro Definition Documentation

#define AT91_CIDR_ARCH   (0xff << 20) /* Architecture Identifier */

Definition at line 65 of file at91_dbgu.h.

#define AT91_CIDR_EPROC   (7 << 5) /* Embedded Processor */

Definition at line 47 of file at91_dbgu.h.

#define AT91_CIDR_EXT   (1 << 31) /* Extension Flag */

Definition at line 67 of file at91_dbgu.h.

#define AT91_CIDR_NVPSIZ   (0xf << 8) /* Nonvolatile Program Memory Size */

Definition at line 48 of file at91_dbgu.h.

#define AT91_CIDR_NVPSIZ2   (0xf << 12) /* Second Nonvolatile Program Memory Size */

Definition at line 49 of file at91_dbgu.h.

#define AT91_CIDR_NVPTYP   (7 << 28) /* Nonvolatile Program Memory Type */

Definition at line 66 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ   (0xf << 16) /* Internal SRAM Size */

Definition at line 50 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_112K   (4 << 16)

Definition at line 53 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_128K   (12 << 16)

Definition at line 61 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_160K   (7 << 16)

Definition at line 56 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_16K   (9 << 16)

Definition at line 58 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_1K   (1 << 16)

Definition at line 51 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_256K   (13 << 16)

Definition at line 62 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_2K   (2 << 16)

Definition at line 52 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_32K   (10 << 16)

Definition at line 59 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_4K   (5 << 16)

Definition at line 54 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_512K   (15 << 16)

Definition at line 64 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_64K   (11 << 16)

Definition at line 60 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_80K   (6 << 16)

Definition at line 55 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_8K   (8 << 16)

Definition at line 57 of file at91_dbgu.h.

#define AT91_CIDR_SRAMSIZ_96K   (14 << 16)

Definition at line 63 of file at91_dbgu.h.

#define AT91_CIDR_VERSION   (0x1f << 0) /* Version of the Device */

Definition at line 46 of file at91_dbgu.h.

#define AT91_DBGU_BRGR   (0x20) /* Baud Rate Generator Register */

Definition at line 33 of file at91_dbgu.h.

#define AT91_DBGU_CIDR   (0x40) /* Chip ID Register */

Definition at line 35 of file at91_dbgu.h.

#define AT91_DBGU_CR   (0x00) /* Control Register */

Definition at line 23 of file at91_dbgu.h.

#define AT91_DBGU_EXID   (0x44) /* Chip ID Extension Register */

Definition at line 36 of file at91_dbgu.h.

#define AT91_DBGU_FNR   (0x48) /* Force NTRST Register [SAM9 only] */

Definition at line 37 of file at91_dbgu.h.

#define AT91_DBGU_FNTRST   (1 << 0) /* Force NTRST */

Definition at line 38 of file at91_dbgu.h.

#define AT91_DBGU_IDR   (0x0c) /* Interrupt Disable Register */

Definition at line 28 of file at91_dbgu.h.

#define AT91_DBGU_IER   (0x08) /* Interrupt Enable Register */

Definition at line 25 of file at91_dbgu.h.

#define AT91_DBGU_IMR   (0x10) /* Interrupt Mask Register */

Definition at line 29 of file at91_dbgu.h.

#define AT91_DBGU_MR   (0x04) /* Mode Register */

Definition at line 24 of file at91_dbgu.h.

#define AT91_DBGU_RHR   (0x18) /* Receiver Holding Register */

Definition at line 31 of file at91_dbgu.h.

#define AT91_DBGU_SR   (0x14) /* Status Register */

Definition at line 30 of file at91_dbgu.h.

#define AT91_DBGU_THR   (0x1c) /* Transmitter Holding Register */

Definition at line 32 of file at91_dbgu.h.

#define AT91_DBGU_TXEMPTY   (1 << 9) /* Transmitter Empty */

Definition at line 27 of file at91_dbgu.h.

#define AT91_DBGU_TXRDY   (1 << 1) /* Transmitter Ready */

Definition at line 26 of file at91_dbgu.h.

#define dbgu_readl	(		dbgu,
			field
	)		__raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)

Definition at line 19 of file at91_dbgu.h.