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at91rm9200.c
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1 /*
2  * arch/arm/mach-at91/at91rm9200.c
3  *
4  * Copyright (C) 2005 SAN People
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  */
12 
13 #include <linux/module.h>
14 
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <asm/system_misc.h>
19 #include <mach/at91rm9200.h>
20 #include <mach/at91_aic.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_st.h>
23 #include <mach/cpu.h>
24 
25 #include "soc.h"
26 #include "generic.h"
27 #include "clock.h"
28 #include "sam9_smc.h"
29 
30 /* --------------------------------------------------------------------
31  * Clocks
32  * -------------------------------------------------------------------- */
33 
34 /*
35  * The peripheral clocks.
36  */
37 static struct clk udc_clk = {
38  .name = "udc_clk",
39  .pmc_mask = 1 << AT91RM9200_ID_UDP,
40  .type = CLK_TYPE_PERIPHERAL,
41 };
42 static struct clk ohci_clk = {
43  .name = "ohci_clk",
44  .pmc_mask = 1 << AT91RM9200_ID_UHP,
45  .type = CLK_TYPE_PERIPHERAL,
46 };
47 static struct clk ether_clk = {
48  .name = "ether_clk",
49  .pmc_mask = 1 << AT91RM9200_ID_EMAC,
50  .type = CLK_TYPE_PERIPHERAL,
51 };
52 static struct clk mmc_clk = {
53  .name = "mci_clk",
54  .pmc_mask = 1 << AT91RM9200_ID_MCI,
55  .type = CLK_TYPE_PERIPHERAL,
56 };
57 static struct clk twi_clk = {
58  .name = "twi_clk",
59  .pmc_mask = 1 << AT91RM9200_ID_TWI,
60  .type = CLK_TYPE_PERIPHERAL,
61 };
62 static struct clk usart0_clk = {
63  .name = "usart0_clk",
64  .pmc_mask = 1 << AT91RM9200_ID_US0,
65  .type = CLK_TYPE_PERIPHERAL,
66 };
67 static struct clk usart1_clk = {
68  .name = "usart1_clk",
69  .pmc_mask = 1 << AT91RM9200_ID_US1,
70  .type = CLK_TYPE_PERIPHERAL,
71 };
72 static struct clk usart2_clk = {
73  .name = "usart2_clk",
74  .pmc_mask = 1 << AT91RM9200_ID_US2,
75  .type = CLK_TYPE_PERIPHERAL,
76 };
77 static struct clk usart3_clk = {
78  .name = "usart3_clk",
79  .pmc_mask = 1 << AT91RM9200_ID_US3,
80  .type = CLK_TYPE_PERIPHERAL,
81 };
82 static struct clk spi_clk = {
83  .name = "spi_clk",
84  .pmc_mask = 1 << AT91RM9200_ID_SPI,
85  .type = CLK_TYPE_PERIPHERAL,
86 };
87 static struct clk pioA_clk = {
88  .name = "pioA_clk",
89  .pmc_mask = 1 << AT91RM9200_ID_PIOA,
90  .type = CLK_TYPE_PERIPHERAL,
91 };
92 static struct clk pioB_clk = {
93  .name = "pioB_clk",
94  .pmc_mask = 1 << AT91RM9200_ID_PIOB,
95  .type = CLK_TYPE_PERIPHERAL,
96 };
97 static struct clk pioC_clk = {
98  .name = "pioC_clk",
99  .pmc_mask = 1 << AT91RM9200_ID_PIOC,
100  .type = CLK_TYPE_PERIPHERAL,
101 };
102 static struct clk pioD_clk = {
103  .name = "pioD_clk",
104  .pmc_mask = 1 << AT91RM9200_ID_PIOD,
105  .type = CLK_TYPE_PERIPHERAL,
106 };
107 static struct clk ssc0_clk = {
108  .name = "ssc0_clk",
109  .pmc_mask = 1 << AT91RM9200_ID_SSC0,
110  .type = CLK_TYPE_PERIPHERAL,
111 };
112 static struct clk ssc1_clk = {
113  .name = "ssc1_clk",
114  .pmc_mask = 1 << AT91RM9200_ID_SSC1,
115  .type = CLK_TYPE_PERIPHERAL,
116 };
117 static struct clk ssc2_clk = {
118  .name = "ssc2_clk",
119  .pmc_mask = 1 << AT91RM9200_ID_SSC2,
120  .type = CLK_TYPE_PERIPHERAL,
121 };
122 static struct clk tc0_clk = {
123  .name = "tc0_clk",
124  .pmc_mask = 1 << AT91RM9200_ID_TC0,
125  .type = CLK_TYPE_PERIPHERAL,
126 };
127 static struct clk tc1_clk = {
128  .name = "tc1_clk",
129  .pmc_mask = 1 << AT91RM9200_ID_TC1,
130  .type = CLK_TYPE_PERIPHERAL,
131 };
132 static struct clk tc2_clk = {
133  .name = "tc2_clk",
134  .pmc_mask = 1 << AT91RM9200_ID_TC2,
135  .type = CLK_TYPE_PERIPHERAL,
136 };
137 static struct clk tc3_clk = {
138  .name = "tc3_clk",
139  .pmc_mask = 1 << AT91RM9200_ID_TC3,
140  .type = CLK_TYPE_PERIPHERAL,
141 };
142 static struct clk tc4_clk = {
143  .name = "tc4_clk",
144  .pmc_mask = 1 << AT91RM9200_ID_TC4,
145  .type = CLK_TYPE_PERIPHERAL,
146 };
147 static struct clk tc5_clk = {
148  .name = "tc5_clk",
149  .pmc_mask = 1 << AT91RM9200_ID_TC5,
150  .type = CLK_TYPE_PERIPHERAL,
151 };
152 
153 static struct clk *periph_clocks[] __initdata = {
154  &pioA_clk,
155  &pioB_clk,
156  &pioC_clk,
157  &pioD_clk,
158  &usart0_clk,
159  &usart1_clk,
160  &usart2_clk,
161  &usart3_clk,
162  &mmc_clk,
163  &udc_clk,
164  &twi_clk,
165  &spi_clk,
166  &ssc0_clk,
167  &ssc1_clk,
168  &ssc2_clk,
169  &tc0_clk,
170  &tc1_clk,
171  &tc2_clk,
172  &tc3_clk,
173  &tc4_clk,
174  &tc5_clk,
175  &ohci_clk,
176  &ether_clk,
177  // irq0 .. irq6
178 };
179 
180 static struct clk_lookup periph_clocks_lookups[] = {
181  CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
182  CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
183  CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
184  CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
185  CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
186  CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
187  CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
188  CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
189  CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
190  CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
191  /* fake hclk clock */
192  CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
193  CLKDEV_CON_ID("pioA", &pioA_clk),
194  CLKDEV_CON_ID("pioB", &pioB_clk),
195  CLKDEV_CON_ID("pioC", &pioC_clk),
196  CLKDEV_CON_ID("pioD", &pioD_clk),
197 };
198 
199 static struct clk_lookup usart_clocks_lookups[] = {
200  CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
201  CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
202  CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
203  CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
204  CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
205 };
206 
207 /*
208  * The four programmable clocks.
209  * You must configure pin multiplexing to bring these signals out.
210  */
211 static struct clk pck0 = {
212  .name = "pck0",
213  .pmc_mask = AT91_PMC_PCK0,
214  .type = CLK_TYPE_PROGRAMMABLE,
215  .id = 0,
216 };
217 static struct clk pck1 = {
218  .name = "pck1",
219  .pmc_mask = AT91_PMC_PCK1,
220  .type = CLK_TYPE_PROGRAMMABLE,
221  .id = 1,
222 };
223 static struct clk pck2 = {
224  .name = "pck2",
225  .pmc_mask = AT91_PMC_PCK2,
226  .type = CLK_TYPE_PROGRAMMABLE,
227  .id = 2,
228 };
229 static struct clk pck3 = {
230  .name = "pck3",
231  .pmc_mask = AT91_PMC_PCK3,
232  .type = CLK_TYPE_PROGRAMMABLE,
233  .id = 3,
234 };
235 
236 static void __init at91rm9200_register_clocks(void)
237 {
238  int i;
239 
240  for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
241  clk_register(periph_clocks[i]);
242 
243  clkdev_add_table(periph_clocks_lookups,
244  ARRAY_SIZE(periph_clocks_lookups));
245  clkdev_add_table(usart_clocks_lookups,
246  ARRAY_SIZE(usart_clocks_lookups));
247 
248  clk_register(&pck0);
249  clk_register(&pck1);
250  clk_register(&pck2);
251  clk_register(&pck3);
252 }
253 
254 /* --------------------------------------------------------------------
255  * GPIO
256  * -------------------------------------------------------------------- */
257 
258 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
259  {
260  .id = AT91RM9200_ID_PIOA,
261  .regbase = AT91RM9200_BASE_PIOA,
262  }, {
263  .id = AT91RM9200_ID_PIOB,
264  .regbase = AT91RM9200_BASE_PIOB,
265  }, {
266  .id = AT91RM9200_ID_PIOC,
267  .regbase = AT91RM9200_BASE_PIOC,
268  }, {
269  .id = AT91RM9200_ID_PIOD,
270  .regbase = AT91RM9200_BASE_PIOD,
271  }
272 };
273 
274 static void at91rm9200_idle(void)
275 {
276  /*
277  * Disable the processor clock. The processor will be automatically
278  * re-enabled by an interrupt or by a reset.
279  */
280  at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
281 }
282 
283 static void at91rm9200_restart(char mode, const char *cmd)
284 {
285  /*
286  * Perform a hardware reset with the use of the Watchdog timer.
287  */
288  at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
289  at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
290 }
291 
292 /* --------------------------------------------------------------------
293  * AT91RM9200 processor initialization
294  * -------------------------------------------------------------------- */
295 static void __init at91rm9200_map_io(void)
296 {
297  /* Map peripherals */
298  at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
299 }
300 
301 static void __init at91rm9200_ioremap_registers(void)
302 {
303  at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
304  at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
305 }
306 
307 static void __init at91rm9200_initialize(void)
308 {
309  arm_pm_idle = at91rm9200_idle;
310  arm_pm_restart = at91rm9200_restart;
311  at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
312  | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
313  | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
314  | (1 << AT91RM9200_ID_IRQ6);
315 
316  /* Initialize GPIO subsystem */
317  at91_gpio_init(at91rm9200_gpio,
318  cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
319 }
320 
321 
322 /* --------------------------------------------------------------------
323  * Interrupt initialization
324  * -------------------------------------------------------------------- */
325 
326 /*
327  * The default interrupt priority levels (0 = lowest, 7 = highest).
328  */
329 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
330  7, /* Advanced Interrupt Controller (FIQ) */
331  7, /* System Peripherals */
332  1, /* Parallel IO Controller A */
333  1, /* Parallel IO Controller B */
334  1, /* Parallel IO Controller C */
335  1, /* Parallel IO Controller D */
336  5, /* USART 0 */
337  5, /* USART 1 */
338  5, /* USART 2 */
339  5, /* USART 3 */
340  0, /* Multimedia Card Interface */
341  2, /* USB Device Port */
342  6, /* Two-Wire Interface */
343  5, /* Serial Peripheral Interface */
344  4, /* Serial Synchronous Controller 0 */
345  4, /* Serial Synchronous Controller 1 */
346  4, /* Serial Synchronous Controller 2 */
347  0, /* Timer Counter 0 */
348  0, /* Timer Counter 1 */
349  0, /* Timer Counter 2 */
350  0, /* Timer Counter 3 */
351  0, /* Timer Counter 4 */
352  0, /* Timer Counter 5 */
353  2, /* USB Host port */
354  3, /* Ethernet MAC */
355  0, /* Advanced Interrupt Controller (IRQ0) */
356  0, /* Advanced Interrupt Controller (IRQ1) */
357  0, /* Advanced Interrupt Controller (IRQ2) */
358  0, /* Advanced Interrupt Controller (IRQ3) */
359  0, /* Advanced Interrupt Controller (IRQ4) */
360  0, /* Advanced Interrupt Controller (IRQ5) */
361  0 /* Advanced Interrupt Controller (IRQ6) */
362 };
363 
364 struct at91_init_soc __initdata at91rm9200_soc = {
365  .map_io = at91rm9200_map_io,
366  .default_irq_priority = at91rm9200_default_irq_priority,
367  .ioremap_registers = at91rm9200_ioremap_registers,
368  .register_clocks = at91rm9200_register_clocks,
369  .init = at91rm9200_initialize,
370 };
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