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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ |
| #define | AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ |
| #define | AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ |
| #define | AT91SAM9261_ID_US0 6 /* USART 0 */ |
| #define | AT91SAM9261_ID_US1 7 /* USART 1 */ |
| #define | AT91SAM9261_ID_US2 8 /* USART 2 */ |
| #define | AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ |
| #define | AT91SAM9261_ID_UDP 10 /* USB Device Port */ |
| #define | AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ |
| #define | AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ |
| #define | AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ |
| #define | AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
| #define | AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
| #define | AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ |
| #define | AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ |
| #define | AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ |
| #define | AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ |
| #define | AT91SAM9261_ID_UHP 20 /* USB Host port */ |
| #define | AT91SAM9261_ID_LCDC 21 /* LDC Controller */ |
| #define | AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ |
| #define | AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ |
| #define | AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ |
| #define | AT91SAM9261_BASE_TCB0 0xfffa0000 |
| #define | AT91SAM9261_BASE_TC0 0xfffa0000 |
| #define | AT91SAM9261_BASE_TC1 0xfffa0040 |
| #define | AT91SAM9261_BASE_TC2 0xfffa0080 |
| #define | AT91SAM9261_BASE_UDP 0xfffa4000 |
| #define | AT91SAM9261_BASE_MCI 0xfffa8000 |
| #define | AT91SAM9261_BASE_TWI 0xfffac000 |
| #define | AT91SAM9261_BASE_US0 0xfffb0000 |
| #define | AT91SAM9261_BASE_US1 0xfffb4000 |
| #define | AT91SAM9261_BASE_US2 0xfffb8000 |
| #define | AT91SAM9261_BASE_SSC0 0xfffbc000 |
| #define | AT91SAM9261_BASE_SSC1 0xfffc0000 |
| #define | AT91SAM9261_BASE_SSC2 0xfffc4000 |
| #define | AT91SAM9261_BASE_SPI0 0xfffc8000 |
| #define | AT91SAM9261_BASE_SPI1 0xfffcc000 |
| #define | AT91SAM9261_BASE_SMC 0xffffec00 |
| #define | AT91SAM9261_BASE_MATRIX 0xffffee00 |
| #define | AT91SAM9261_BASE_SDRAMC 0xffffea00 |
| #define | AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 |
| #define | AT91SAM9261_BASE_PIOA 0xfffff400 |
| #define | AT91SAM9261_BASE_PIOB 0xfffff600 |
| #define | AT91SAM9261_BASE_PIOC 0xfffff800 |
| #define | AT91SAM9261_BASE_RSTC 0xfffffd00 |
| #define | AT91SAM9261_BASE_SHDWC 0xfffffd10 |
| #define | AT91SAM9261_BASE_RTT 0xfffffd20 |
| #define | AT91SAM9261_BASE_PIT 0xfffffd30 |
| #define | AT91SAM9261_BASE_WDT 0xfffffd40 |
| #define | AT91SAM9261_BASE_GPBR 0xfffffd50 |
| #define | AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
| #define | AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ |
| #define | AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */ |
| #define | AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */ |
| #define | AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ |
| #define | AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ |
| #define | AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ |
| #define | AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ |
| #define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 |
Definition at line 71 of file at91sam9261.h.
| #define AT91SAM9261_BASE_GPBR 0xfffffd50 |
Definition at line 80 of file at91sam9261.h.
| #define AT91SAM9261_BASE_MATRIX 0xffffee00 |
Definition at line 69 of file at91sam9261.h.
| #define AT91SAM9261_BASE_MCI 0xfffa8000 |
Definition at line 53 of file at91sam9261.h.
| #define AT91SAM9261_BASE_PIOA 0xfffff400 |
Definition at line 72 of file at91sam9261.h.
| #define AT91SAM9261_BASE_PIOB 0xfffff600 |
Definition at line 73 of file at91sam9261.h.
| #define AT91SAM9261_BASE_PIOC 0xfffff800 |
Definition at line 74 of file at91sam9261.h.
| #define AT91SAM9261_BASE_PIT 0xfffffd30 |
Definition at line 78 of file at91sam9261.h.
| #define AT91SAM9261_BASE_RSTC 0xfffffd00 |
Definition at line 75 of file at91sam9261.h.
| #define AT91SAM9261_BASE_RTT 0xfffffd20 |
Definition at line 77 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SDRAMC 0xffffea00 |
Definition at line 70 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SHDWC 0xfffffd10 |
Definition at line 76 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SMC 0xffffec00 |
Definition at line 68 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SPI0 0xfffc8000 |
Definition at line 61 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SPI1 0xfffcc000 |
Definition at line 62 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SSC0 0xfffbc000 |
Definition at line 58 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SSC1 0xfffc0000 |
Definition at line 59 of file at91sam9261.h.
| #define AT91SAM9261_BASE_SSC2 0xfffc4000 |
Definition at line 60 of file at91sam9261.h.
| #define AT91SAM9261_BASE_TC0 0xfffa0000 |
Definition at line 49 of file at91sam9261.h.
| #define AT91SAM9261_BASE_TC1 0xfffa0040 |
Definition at line 50 of file at91sam9261.h.
| #define AT91SAM9261_BASE_TC2 0xfffa0080 |
Definition at line 51 of file at91sam9261.h.
| #define AT91SAM9261_BASE_TCB0 0xfffa0000 |
Definition at line 48 of file at91sam9261.h.
| #define AT91SAM9261_BASE_TWI 0xfffac000 |
Definition at line 54 of file at91sam9261.h.
| #define AT91SAM9261_BASE_UDP 0xfffa4000 |
Definition at line 52 of file at91sam9261.h.
| #define AT91SAM9261_BASE_US0 0xfffb0000 |
Definition at line 55 of file at91sam9261.h.
| #define AT91SAM9261_BASE_US1 0xfffb4000 |
Definition at line 56 of file at91sam9261.h.
| #define AT91SAM9261_BASE_US2 0xfffb8000 |
Definition at line 57 of file at91sam9261.h.
| #define AT91SAM9261_BASE_WDT 0xfffffd40 |
Definition at line 79 of file at91sam9261.h.
| #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ |
Definition at line 40 of file at91sam9261.h.
| #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ |
Definition at line 41 of file at91sam9261.h.
| #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ |
Definition at line 42 of file at91sam9261.h.
| #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ |
Definition at line 39 of file at91sam9261.h.
| #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ |
Definition at line 27 of file at91sam9261.h.
| #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ |
Definition at line 21 of file at91sam9261.h.
| #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ |
Definition at line 22 of file at91sam9261.h.
| #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ |
Definition at line 23 of file at91sam9261.h.
| #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ |
Definition at line 30 of file at91sam9261.h.
| #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ |
Definition at line 31 of file at91sam9261.h.
| #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
Definition at line 32 of file at91sam9261.h.
| #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
Definition at line 33 of file at91sam9261.h.
| #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ |
Definition at line 34 of file at91sam9261.h.
Definition at line 35 of file at91sam9261.h.
Definition at line 36 of file at91sam9261.h.
Definition at line 37 of file at91sam9261.h.
| #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ |
Definition at line 29 of file at91sam9261.h.
Definition at line 28 of file at91sam9261.h.
Definition at line 38 of file at91sam9261.h.
| #define AT91SAM9261_ID_US0 6 /* USART 0 */ |
Definition at line 24 of file at91sam9261.h.
| #define AT91SAM9261_ID_US1 7 /* USART 1 */ |
Definition at line 25 of file at91sam9261.h.
| #define AT91SAM9261_ID_US2 8 /* USART 2 */ |
Definition at line 26 of file at91sam9261.h.
| #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ |
Definition at line 96 of file at91sam9261.h.
| #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ |
Definition at line 92 of file at91sam9261.h.
Definition at line 93 of file at91sam9261.h.
| #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
Definition at line 86 of file at91sam9261.h.
| #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ |
Definition at line 87 of file at91sam9261.h.
| #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ |
Definition at line 95 of file at91sam9261.h.
| #define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */ |
Definition at line 89 of file at91sam9261.h.
| #define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */ |
Definition at line 90 of file at91sam9261.h.
1.8.2