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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */ |
| #define | AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
| #define | AT91_MATRIX_EBI_CS1A_SMC (0 << 1) |
| #define | AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) |
| #define | AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
| #define | AT91_MATRIX_EBI_CS3A_SMC (0 << 3) |
| #define | AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) |
| #define | AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
| #define | AT91_MATRIX_EBI_DBPU_ON (0 << 8) |
| #define | AT91_MATRIX_EBI_DBPU_OFF (1 << 8) |
| #define | AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
| #define | AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) |
| #define | AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) |
| #define | AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ |
| #define | AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) |
| #define | AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) |
| #define | AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ |
| #define | AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) |
| #define | AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) |
| #define | AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ |
| #define | AT91_MATRIX_NFD0_ON_D0 (0 << 24) |
| #define | AT91_MATRIX_NFD0_ON_D16 (1 << 24) |
| #define | AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ |
| #define | AT91_MATRIX_MP_OFF (0 << 25) |
| #define | AT91_MATRIX_MP_ON (1 << 25) |
| #define | AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ |
| #define | AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ |
| #define | AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) |
| #define | AT91_MATRIX_WPMR_WP_WPEN (1 << 0) |
| #define | AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ |
| #define | AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ |
| #define | AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ |
| #define | AT91_MATRIX_WPSR_NO_WPV (0 << 0) |
| #define | AT91_MATRIX_WPSR_WPV (1 << 0) |
| #define | AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ |
Definition at line 37 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
Definition at line 16 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) |
Definition at line 18 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) |
Definition at line 17 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
Definition at line 19 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) |
Definition at line 20 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) |
Definition at line 21 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) |
Definition at line 24 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) |
Definition at line 23 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
Definition at line 22 of file at91sam9n12_matrix.h.
Definition at line 31 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) |
Definition at line 33 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) |
Definition at line 32 of file at91sam9n12_matrix.h.
Definition at line 28 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) |
Definition at line 30 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) |
Definition at line 29 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
Definition at line 25 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) |
Definition at line 26 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) |
Definition at line 27 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */ |
Definition at line 15 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_MP_OFF (0 << 25) |
Definition at line 38 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_MP_ON (1 << 25) |
Definition at line 39 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_NFD0_ON_D0 (0 << 24) |
Definition at line 35 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_NFD0_ON_D16 (1 << 24) |
Definition at line 36 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ |
Definition at line 34 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ |
Definition at line 41 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) |
Definition at line 43 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) |
Definition at line 44 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ |
Definition at line 42 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ |
Definition at line 45 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ |
Definition at line 47 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPSR_NO_WPV (0 << 0) |
Definition at line 49 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPSR_WPV (1 << 0) |
Definition at line 50 of file at91sam9n12_matrix.h.
Definition at line 48 of file at91sam9n12_matrix.h.
| #define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ |
Definition at line 51 of file at91sam9n12_matrix.h.
1.8.2