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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ |
| #define | AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ |
| #define | AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ |
| #define | AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ |
| #define | AT91SAM9RL_ID_US0 6 /* USART 0 */ |
| #define | AT91SAM9RL_ID_US1 7 /* USART 1 */ |
| #define | AT91SAM9RL_ID_US2 8 /* USART 2 */ |
| #define | AT91SAM9RL_ID_US3 9 /* USART 3 */ |
| #define | AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ |
| #define | AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ |
| #define | AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ |
| #define | AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ |
| #define | AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
| #define | AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
| #define | AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ |
| #define | AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ |
| #define | AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ |
| #define | AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
| #define | AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ |
| #define | AT91SAM9RL_ID_DMA 21 /* DMA Controller */ |
| #define | AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ |
| #define | AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ |
| #define | AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ |
| #define | AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ |
| #define | AT91SAM9RL_BASE_TCB0 0xfffa0000 |
| #define | AT91SAM9RL_BASE_TC0 0xfffa0000 |
| #define | AT91SAM9RL_BASE_TC1 0xfffa0040 |
| #define | AT91SAM9RL_BASE_TC2 0xfffa0080 |
| #define | AT91SAM9RL_BASE_MCI 0xfffa4000 |
| #define | AT91SAM9RL_BASE_TWI0 0xfffa8000 |
| #define | AT91SAM9RL_BASE_TWI1 0xfffac000 |
| #define | AT91SAM9RL_BASE_US0 0xfffb0000 |
| #define | AT91SAM9RL_BASE_US1 0xfffb4000 |
| #define | AT91SAM9RL_BASE_US2 0xfffb8000 |
| #define | AT91SAM9RL_BASE_US3 0xfffbc000 |
| #define | AT91SAM9RL_BASE_SSC0 0xfffc0000 |
| #define | AT91SAM9RL_BASE_SSC1 0xfffc4000 |
| #define | AT91SAM9RL_BASE_PWMC 0xfffc8000 |
| #define | AT91SAM9RL_BASE_SPI 0xfffcc000 |
| #define | AT91SAM9RL_BASE_TSC 0xfffd0000 |
| #define | AT91SAM9RL_BASE_UDPHS 0xfffd4000 |
| #define | AT91SAM9RL_BASE_AC97C 0xfffd8000 |
| #define | AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
| #define | AT91SAM9RL_BASE_DMA 0xffffe600 |
| #define | AT91SAM9RL_BASE_ECC 0xffffe800 |
| #define | AT91SAM9RL_BASE_SDRAMC 0xffffea00 |
| #define | AT91SAM9RL_BASE_SMC 0xffffec00 |
| #define | AT91SAM9RL_BASE_MATRIX 0xffffee00 |
| #define | AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 |
| #define | AT91SAM9RL_BASE_PIOA 0xfffff400 |
| #define | AT91SAM9RL_BASE_PIOB 0xfffff600 |
| #define | AT91SAM9RL_BASE_PIOC 0xfffff800 |
| #define | AT91SAM9RL_BASE_PIOD 0xfffffa00 |
| #define | AT91SAM9RL_BASE_RSTC 0xfffffd00 |
| #define | AT91SAM9RL_BASE_SHDWC 0xfffffd10 |
| #define | AT91SAM9RL_BASE_RTT 0xfffffd20 |
| #define | AT91SAM9RL_BASE_PIT 0xfffffd30 |
| #define | AT91SAM9RL_BASE_WDT 0xfffffd40 |
| #define | AT91SAM9RL_BASE_GPBR 0xfffffd60 |
| #define | AT91SAM9RL_BASE_RTC 0xfffffe00 |
| #define | AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
| #define | AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ |
| #define | AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ |
| #define | AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ |
| #define | AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ |
| #define | AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ |
| #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
Definition at line 72 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_AC97C 0xfffd8000 |
Definition at line 66 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 |
Definition at line 79 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_DMA 0xffffe600 |
Definition at line 74 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_ECC 0xffffe800 |
Definition at line 75 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_GPBR 0xfffffd60 |
Definition at line 89 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_MATRIX 0xffffee00 |
Definition at line 78 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_MCI 0xfffa4000 |
Definition at line 53 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_PIOA 0xfffff400 |
Definition at line 80 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_PIOB 0xfffff600 |
Definition at line 81 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_PIOC 0xfffff800 |
Definition at line 82 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_PIOD 0xfffffa00 |
Definition at line 83 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_PIT 0xfffffd30 |
Definition at line 87 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_PWMC 0xfffc8000 |
Definition at line 62 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_RSTC 0xfffffd00 |
Definition at line 84 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_RTC 0xfffffe00 |
Definition at line 90 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_RTT 0xfffffd20 |
Definition at line 86 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_SDRAMC 0xffffea00 |
Definition at line 76 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 |
Definition at line 85 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_SMC 0xffffec00 |
Definition at line 77 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_SPI 0xfffcc000 |
Definition at line 63 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_SSC0 0xfffc0000 |
Definition at line 60 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_SSC1 0xfffc4000 |
Definition at line 61 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_TC0 0xfffa0000 |
Definition at line 50 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_TC1 0xfffa0040 |
Definition at line 51 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_TC2 0xfffa0080 |
Definition at line 52 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_TCB0 0xfffa0000 |
Definition at line 49 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_TSC 0xfffd0000 |
Definition at line 64 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_TWI0 0xfffa8000 |
Definition at line 54 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_TWI1 0xfffac000 |
Definition at line 55 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_UDPHS 0xfffd4000 |
Definition at line 65 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_US0 0xfffb0000 |
Definition at line 56 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_US1 0xfffb4000 |
Definition at line 57 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_US2 0xfffb8000 |
Definition at line 58 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_US3 0xfffbc000 |
Definition at line 59 of file at91sam9rl.h.
| #define AT91SAM9RL_BASE_WDT 0xfffffd40 |
Definition at line 88 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ |
Definition at line 42 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ |
Definition at line 39 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ |
Definition at line 43 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ |
Definition at line 41 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ |
Definition at line 28 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ |
Definition at line 20 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ |
Definition at line 21 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ |
Definition at line 22 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ |
Definition at line 23 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
Definition at line 37 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ |
Definition at line 31 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
Definition at line 32 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
Definition at line 33 of file at91sam9rl.h.
Definition at line 34 of file at91sam9rl.h.
Definition at line 35 of file at91sam9rl.h.
Definition at line 36 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ |
Definition at line 38 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ |
Definition at line 29 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ |
Definition at line 30 of file at91sam9rl.h.
Definition at line 40 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_US0 6 /* USART 0 */ |
Definition at line 24 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_US1 7 /* USART 1 */ |
Definition at line 25 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_US2 8 /* USART 2 */ |
Definition at line 26 of file at91sam9rl.h.
| #define AT91SAM9RL_ID_US3 9 /* USART 3 */ |
Definition at line 27 of file at91sam9rl.h.
| #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ |
Definition at line 102 of file at91sam9rl.h.
| #define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ |
Definition at line 99 of file at91sam9rl.h.
Definition at line 100 of file at91sam9rl.h.
| #define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
Definition at line 96 of file at91sam9rl.h.
Definition at line 97 of file at91sam9rl.h.
| #define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ |
Definition at line 103 of file at91sam9rl.h.
1.8.2