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| #define | PCI_REG_COMMAND 0x04 /* PCI Command Register */ |
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| #define | CMD_IO_SPACE 0x0001 |
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| #define | CMD_MEMORY_SPACE 0x0002 |
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| #define | CMD_BUS_MASTER 0x0004 |
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| #define | BAR_0 0 |
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| #define | BAR_1 1 |
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| #define | BAR_5 5 |
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| #define | AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
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| #define | AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
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| #define | AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
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| #define | AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ |
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| #define | AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
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| #define | SPEED_0 0xffff |
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| #define | HALF_DUPLEX 1 |
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| #define | FULL_DUPLEX 2 |
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| #define | AT_ERR_EEPROM 1 |
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| #define | AT_ERR_PHY 2 |
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| #define | AT_ERR_CONFIG 3 |
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| #define | AT_ERR_PARAM 4 |
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| #define | AT_ERR_MAC_TYPE 5 |
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| #define | AT_ERR_PHY_TYPE 6 |
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| #define | AT_ERR_PHY_SPEED 7 |
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| #define | AT_ERR_PHY_RES 8 |
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| #define | AT_ERR_TIMEOUT 9 |
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| #define | MAX_JUMBO_FRAME_SIZE 0x2000 |
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| #define | AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd) |
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| #define | AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan) |
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| #define | AT_MAX_RECEIVE_QUEUE 4 |
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| #define | AT_PAGE_NUM_PER_QUEUE 2 |
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| #define | AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL |
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| #define | AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL |
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| #define | AT_TX_WATCHDOG (5 * HZ) |
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| #define | AT_MAX_INT_WORK 10 |
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| #define | AT_TWSI_EEPROM_TIMEOUT 100 |
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| #define | AT_HW_MAX_IDLE_DELAY 10 |
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| #define | AT_SUSPEND_LINK_TIMEOUT 28 |
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| #define | AT_REGS_LEN 75 |
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| #define | AT_EEPROM_LEN 512 |
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| #define | AT_ADV_MASK |
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| #define | TPD_BUFLEN_MASK 0x3FFF |
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| #define | TPD_BUFLEN_SHIFT 0 |
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| #define | TPD_DMAINT_MASK 0x0001 |
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| #define | TPD_DMAINT_SHIFT 14 |
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| #define | TPD_PKTNT_MASK 0x0001 |
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| #define | TPD_PKTINT_SHIFT 15 |
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| #define | TPD_VLANTAG_MASK 0xFFFF |
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| #define | TPD_VLAN_SHIFT 16 |
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| #define | TPD_EOP_MASK 0x0001 |
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| #define | TPD_EOP_SHIFT 0 |
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| #define | TPD_IP_VERSION_MASK 0x0001 |
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| #define | TPD_IP_VERSION_SHIFT 1 /* 0 : IPV4, 1 : IPV6 */ |
| |
| #define | TPD_INS_VL_TAG_MASK 0x0001 |
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| #define | TPD_INS_VL_TAG_SHIFT 2 |
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| #define | TPD_CC_SEGMENT_EN_MASK 0x0001 |
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| #define | TPD_CC_SEGMENT_EN_SHIFT 3 |
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| #define | TPD_SEGMENT_EN_MASK 0x0001 |
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| #define | TPD_SEGMENT_EN_SHIFT 4 |
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| #define | TPD_IP_CSUM_MASK 0x0001 |
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| #define | TPD_IP_CSUM_SHIFT 5 |
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| #define | TPD_TCP_CSUM_MASK 0x0001 |
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| #define | TPD_TCP_CSUM_SHIFT 6 |
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| #define | TPD_UDP_CSUM_MASK 0x0001 |
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| #define | TPD_UDP_CSUM_SHIFT 7 |
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| #define | TPD_V6_IPHLLO_MASK 0x0007 |
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| #define | TPD_V6_IPHLLO_SHIFT 7 |
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| #define | TPD_VL_TAGGED_MASK 0x0001 |
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| #define | TPD_VL_TAGGED_SHIFT 8 |
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| #define | TPD_ETHTYPE_MASK 0x0001 |
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| #define | TPD_ETHTYPE_SHIFT 9 |
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| #define | TDP_V4_IPHL_MASK 0x000F |
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| #define | TPD_V4_IPHL_SHIFT 10 |
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| #define | TPD_V6_IPHLHI_MASK 0x000F |
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| #define | TPD_V6_IPHLHI_SHIFT 10 |
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| #define | TPD_TCPHDRLEN_MASK 0x000F |
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| #define | TPD_TCPHDRLEN_SHIFT 14 |
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| #define | TPD_HDRFLAG_MASK 0x0001 |
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| #define | TPD_HDRFLAG_SHIFT 18 |
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| #define | TPD_MSS_MASK 0x1FFF |
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| #define | TPD_MSS_SHIFT 19 |
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| #define | TPD_PLOADOFFSET_MASK 0x00FF |
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| #define | TPD_PLOADOFFSET_SHIFT 16 |
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| #define | TPD_CCSUMOFFSET_MASK 0x00FF |
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| #define | TPD_CCSUMOFFSET_SHIFT 24 |
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| #define | MAX_TX_BUF_LEN 0x2000 |
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| #define | MAX_TX_BUF_SHIFT 13 |
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| #define | RRS_RX_CSUM_MASK 0xFFFF |
| |
| #define | RRS_RX_CSUM_SHIFT 0 |
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| #define | RRS_PKT_SIZE_MASK 0x3FFF |
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| #define | RRS_PKT_SIZE_SHIFT 16 |
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| #define | RRS_CPU_NUM_MASK 0x0003 |
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| #define | RRS_CPU_NUM_SHIFT 30 |
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| #define | RRS_IS_RSS_IPV4 0x0001 |
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| #define | RRS_IS_RSS_IPV4_TCP 0x0002 |
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| #define | RRS_IS_RSS_IPV6 0x0004 |
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| #define | RRS_IS_RSS_IPV6_TCP 0x0008 |
| |
| #define | RRS_IS_IPV6 0x0010 |
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| #define | RRS_IS_IP_FRAG 0x0020 |
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| #define | RRS_IS_IP_DF 0x0040 |
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| #define | RRS_IS_802_3 0x0080 |
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| #define | RRS_IS_VLAN_TAG 0x0100 |
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| #define | RRS_IS_ERR_FRAME 0x0200 |
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| #define | RRS_IS_IPV4 0x0400 |
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| #define | RRS_IS_UDP 0x0800 |
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| #define | RRS_IS_TCP 0x1000 |
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| #define | RRS_IS_BCAST 0x2000 |
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| #define | RRS_IS_MCAST 0x4000 |
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| #define | RRS_IS_PAUSE 0x8000 |
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| #define | RRS_ERR_BAD_CRC 0x0001 |
| |
| #define | RRS_ERR_CODE 0x0002 |
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| #define | RRS_ERR_DRIBBLE 0x0004 |
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| #define | RRS_ERR_RUNT 0x0008 |
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| #define | RRS_ERR_RX_OVERFLOW 0x0010 |
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| #define | RRS_ERR_TRUNC 0x0020 |
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| #define | RRS_ERR_IP_CSUM 0x0040 |
| |
| #define | RRS_ERR_L4_CSUM 0x0080 |
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| #define | RRS_ERR_LENGTH 0x0100 |
| |
| #define | RRS_ERR_DES_ADDR 0x0200 |
| |
| #define | MEDIA_TYPE_AUTO_SENSOR 0 |
| |
| #define | MEDIA_TYPE_100M_FULL 1 |
| |
| #define | MEDIA_TYPE_100M_HALF 2 |
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| #define | MEDIA_TYPE_10M_FULL 3 |
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| #define | MEDIA_TYPE_10M_HALF 4 |
| |
| #define | ADVERTISE_10_HALF 0x0001 |
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| #define | ADVERTISE_10_FULL 0x0002 |
| |
| #define | ADVERTISE_100_HALF 0x0004 |
| |
| #define | ADVERTISE_100_FULL 0x0008 |
| |
| #define | ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ |
| |
| #define | ADVERTISE_1000_FULL 0x0020 |
| |
| #define | ATL1E_TX_PCIMAP_SINGLE 0x0001 |
| |
| #define | ATL1E_TX_PCIMAP_PAGE 0x0002 |
| |
| #define | ATL1E_TX_PCIMAP_TYPE_MASK 0x0003 |
| |
| #define | ATL1E_SET_PCIMAP_TYPE(tx_buff, type) |
| |
| #define | __AT_TESTING 0x0001 |
| |
| #define | __AT_RESETTING 0x0002 |
| |
| #define | __AT_DOWN 0x0003 |
| |
| #define | AT_WRITE_REG(a, reg, value) |
| |
| #define | AT_WRITE_FLUSH(a) |
| |
| #define | AT_READ_REG(a, reg) |
| |
| #define | AT_WRITE_REGB(a, reg, value) |
| |
| #define | AT_READ_REGB(a, reg) |
| |
| #define | AT_WRITE_REGW(a, reg, value) |
| |
| #define | AT_READ_REGW(a, reg) |
| |
| #define | AT_WRITE_REG_ARRAY(a, reg, offset, value) |
| |
| #define | AT_READ_REG_ARRAY(a, reg, offset) |
| |
1.8.2