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| #define | _ATL2_HW_H_ |
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| #define | _ATL2_OSDEP_H_ |
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| #define | PCI_COMMAND_REGISTER PCI_COMMAND |
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| #define | CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE |
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| #define | ATL2_WRITE_REG(a, reg, value) |
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| #define | ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr)) |
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| #define | ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg))) |
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| #define | ATL2_WRITE_REGB(a, reg, value) |
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| #define | ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg))) |
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| #define | ATL2_WRITE_REGW(a, reg, value) |
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| #define | ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg))) |
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| #define | ATL2_WRITE_REG_ARRAY(a, reg, offset, value) (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2)))) |
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| #define | ATL2_READ_REG_ARRAY(a, reg, offset) (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2))) |
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| #define | IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */ |
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| #define | IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */ |
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| #define | IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */ |
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| #define | IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */ |
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| #define | MDIO_WAIT_TIMES 10 |
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| #define | MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */ |
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| #define | MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */ |
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| #define | MAC_CTRL_HALF_LEFT_BUF_SHIFT 28 |
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| #define | MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */ |
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| #define | REG_SRAM_TXRAM_END |
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| #define | REG_SRAM_RXRAM_END |
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| #define | REG_TXD_BASE_ADDR_LO |
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| #define | REG_TXD_MEM_SIZE |
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| #define | REG_TXS_BASE_ADDR_LO |
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| #define | REG_TXS_MEM_SIZE |
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| #define | REG_RXD_BASE_ADDR_LO |
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| #define | REG_RXD_BUF_NUM |
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| #define | REG_DMAR 0x1580 |
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| #define | DMAR_EN 0x1 /* 1: Enable DMAR */ |
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| #define | REG_TX_CUT_THRESH |
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| #define | REG_DMAW 0x15A0 |
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| #define | DMAW_EN 0x1 |
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| #define | REG_PAUSE_ON_TH |
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| #define | REG_PAUSE_OFF_TH |
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| #define | REG_MB_TXD_WR_IDX 0x15f0 /* double word align */ |
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| #define | REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */ |
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| #define | ISR_TIMER 1 /* Interrupt when Timer counts down to zero */ |
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| #define | ISR_MANUAL |
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| #define | ISR_RXF_OV 4 /* RXF overflow interrupt */ |
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| #define | ISR_TXF_UR 8 /* TXF underrun interrupt */ |
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| #define | ISR_TXS_OV |
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| #define | ISR_RXS_OV |
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| #define | ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */ |
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| #define | ISR_HOST_TXD_UR 0x80 |
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| #define | ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */ |
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| #define | ISR_DMAR_TO_RST |
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| #define | ISR_DMAW_TO_RST 0x400 |
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| #define | ISR_PHY 0x800 /* phy interrupt */ |
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| #define | ISR_TS_UPDATE |
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| #define | ISR_RS_UPDATE |
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| #define | ISR_TX_EARLY |
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| #define | ISR_TX_EVENT |
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| #define | ISR_RX_EVENT |
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| #define | IMR_NORMAL_MASK |
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| #define | REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */ |
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| #define | REG_STS_RXD_OV |
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| #define | REG_STS_RXS_OV |
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| #define | REG_STS_RX_FILTER |
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| #define | MII_SMARTSPEED 0x14 |
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| #define | MII_DBG_ADDR 0x1D |
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| #define | MII_DBG_DATA 0x1E |
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| #define | PCI_REG_COMMAND 0x04 |
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| #define | CMD_IO_SPACE 0x0001 |
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| #define | CMD_MEMORY_SPACE 0x0002 |
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| #define | CMD_BUS_MASTER 0x0004 |
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| #define | MEDIA_TYPE_100M_FULL 1 |
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| #define | MEDIA_TYPE_100M_HALF 2 |
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| #define | MEDIA_TYPE_10M_FULL 3 |
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| #define | MEDIA_TYPE_10M_HALF 4 |
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| #define | AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */ |
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| #define | ENET_HEADER_SIZE 14 |
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| #define | MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */ |
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| #define | MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */ |
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| #define | ETHERNET_FCS_SIZE 4 |
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| #define | MAX_JUMBO_FRAME_SIZE 0x2000 |
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| #define | VLAN_SIZE 4 |
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| #define | TX_PKT_HEADER_SIZE_MASK 0x7FF |
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| #define | TX_PKT_HEADER_SIZE_SHIFT 0 |
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| #define | TX_PKT_HEADER_INS_VLAN_MASK 0x1 |
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| #define | TX_PKT_HEADER_INS_VLAN_SHIFT 15 |
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| #define | TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF |
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| #define | TX_PKT_HEADER_VLAN_TAG_SHIFT 16 |
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| #define | TX_PKT_STATUS_SIZE_MASK 0x7FF |
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| #define | TX_PKT_STATUS_SIZE_SHIFT 0 |
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| #define | TX_PKT_STATUS_OK_MASK 0x1 |
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| #define | TX_PKT_STATUS_OK_SHIFT 16 |
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| #define | TX_PKT_STATUS_BCAST_MASK 0x1 |
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| #define | TX_PKT_STATUS_BCAST_SHIFT 17 |
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| #define | TX_PKT_STATUS_MCAST_MASK 0x1 |
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| #define | TX_PKT_STATUS_MCAST_SHIFT 18 |
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| #define | TX_PKT_STATUS_PAUSE_MASK 0x1 |
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| #define | TX_PKT_STATUS_PAUSE_SHIFT 19 |
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| #define | TX_PKT_STATUS_CTRL_MASK 0x1 |
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| #define | TX_PKT_STATUS_CTRL_SHIFT 20 |
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| #define | TX_PKT_STATUS_DEFER_MASK 0x1 |
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| #define | TX_PKT_STATUS_DEFER_SHIFT 21 |
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| #define | TX_PKT_STATUS_EXC_DEFER_MASK 0x1 |
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| #define | TX_PKT_STATUS_EXC_DEFER_SHIFT 22 |
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| #define | TX_PKT_STATUS_SINGLE_COL_MASK 0x1 |
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| #define | TX_PKT_STATUS_SINGLE_COL_SHIFT 23 |
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| #define | TX_PKT_STATUS_MULTI_COL_MASK 0x1 |
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| #define | TX_PKT_STATUS_MULTI_COL_SHIFT 24 |
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| #define | TX_PKT_STATUS_LATE_COL_MASK 0x1 |
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| #define | TX_PKT_STATUS_LATE_COL_SHIFT 25 |
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| #define | TX_PKT_STATUS_ABORT_COL_MASK 0x1 |
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| #define | TX_PKT_STATUS_ABORT_COL_SHIFT 26 |
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| #define | TX_PKT_STATUS_UNDERRUN_MASK 0x1 |
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| #define | TX_PKT_STATUS_UNDERRUN_SHIFT 27 |
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| #define | TX_PKT_STATUS_UPDATE_MASK 0x1 |
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| #define | TX_PKT_STATUS_UPDATE_SHIFT 31 |
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| #define | RX_PKT_STATUS_SIZE_MASK 0x7FF |
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| #define | RX_PKT_STATUS_SIZE_SHIFT 0 |
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| #define | RX_PKT_STATUS_OK_MASK 0x1 |
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| #define | RX_PKT_STATUS_OK_SHIFT 16 |
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| #define | RX_PKT_STATUS_BCAST_MASK 0x1 |
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| #define | RX_PKT_STATUS_BCAST_SHIFT 17 |
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| #define | RX_PKT_STATUS_MCAST_MASK 0x1 |
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| #define | RX_PKT_STATUS_MCAST_SHIFT 18 |
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| #define | RX_PKT_STATUS_PAUSE_MASK 0x1 |
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| #define | RX_PKT_STATUS_PAUSE_SHIFT 19 |
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| #define | RX_PKT_STATUS_CTRL_MASK 0x1 |
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| #define | RX_PKT_STATUS_CTRL_SHIFT 20 |
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| #define | RX_PKT_STATUS_CRC_MASK 0x1 |
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| #define | RX_PKT_STATUS_CRC_SHIFT 21 |
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| #define | RX_PKT_STATUS_CODE_MASK 0x1 |
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| #define | RX_PKT_STATUS_CODE_SHIFT 22 |
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| #define | RX_PKT_STATUS_RUNT_MASK 0x1 |
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| #define | RX_PKT_STATUS_RUNT_SHIFT 23 |
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| #define | RX_PKT_STATUS_FRAG_MASK 0x1 |
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| #define | RX_PKT_STATUS_FRAG_SHIFT 24 |
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| #define | RX_PKT_STATUS_TRUNK_MASK 0x1 |
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| #define | RX_PKT_STATUS_TRUNK_SHIFT 25 |
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| #define | RX_PKT_STATUS_ALIGN_MASK 0x1 |
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| #define | RX_PKT_STATUS_ALIGN_SHIFT 26 |
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| #define | RX_PKT_STATUS_VLAN_MASK 0x1 |
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| #define | RX_PKT_STATUS_VLAN_SHIFT 27 |
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| #define | RX_PKT_STATUS_UPDATE_MASK 0x1 |
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| #define | RX_PKT_STATUS_UPDATE_SHIFT 31 |
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| #define | RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF |
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| #define | RX_PKT_STATUS_VLAN_TAG_SHIFT 32 |
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1.8.2