#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/hw_random.h>
#include <linux/bcma/bcma.h>
#include <linux/ssb/ssb.h>
#include <net/mac80211.h>
#include "debugfs.h"
#include "leds.h"
#include "rfkill.h"
#include "bus.h"
#include "lo.h"
#include "phy_common.h"

Data Structures
struct	b43_fw_header

struct	b43_iv

struct	b43_dma

struct	b43_pio

struct	b43_noise_calculation

struct	b43_stats

struct	b43_key

struct	b43_qos_params

struct	b43_request_fw_context

struct	b43_firmware_file

struct	b43_firmware

struct	b43_wldev

struct	b43_wl

Macros
#define	B43_DEBUG 0

#define	B43_MMIO_DMA0_REASON 0x20

#define	B43_MMIO_DMA0_IRQ_MASK 0x24

#define	B43_MMIO_DMA1_REASON 0x28

#define	B43_MMIO_DMA1_IRQ_MASK 0x2C

#define	B43_MMIO_DMA2_REASON 0x30

#define	B43_MMIO_DMA2_IRQ_MASK 0x34

#define	B43_MMIO_DMA3_REASON 0x38

#define	B43_MMIO_DMA3_IRQ_MASK 0x3C

#define	B43_MMIO_DMA4_REASON 0x40

#define	B43_MMIO_DMA4_IRQ_MASK 0x44

#define	B43_MMIO_DMA5_REASON 0x48

#define	B43_MMIO_DMA5_IRQ_MASK 0x4C

#define	B43_MMIO_MACCTL 0x120 /* MAC control */

#define	B43_MMIO_MACCMD 0x124 /* MAC command */

#define	B43_MMIO_GEN_IRQ_REASON 0x128

#define	B43_MMIO_GEN_IRQ_MASK 0x12C

#define	B43_MMIO_RAM_CONTROL 0x130

#define	B43_MMIO_RAM_DATA 0x134

#define	B43_MMIO_PS_STATUS 0x140

#define	B43_MMIO_RADIO_HWENABLED_HI 0x158

#define	B43_MMIO_SHM_CONTROL 0x160

#define	B43_MMIO_SHM_DATA 0x164

#define	B43_MMIO_SHM_DATA_UNALIGNED 0x166

#define	B43_MMIO_XMITSTAT_0 0x170

#define	B43_MMIO_XMITSTAT_1 0x174

#define	B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */

#define	B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */

#define	B43_MMIO_TSF_CFP_REP 0x188

#define	B43_MMIO_TSF_CFP_START 0x18C

#define	B43_MMIO_TSF_CFP_MAXDUR 0x190

#define	B43_MMIO_DMA32_BASE0 0x200

#define	B43_MMIO_DMA32_BASE1 0x220

#define	B43_MMIO_DMA32_BASE2 0x240

#define	B43_MMIO_DMA32_BASE3 0x260

#define	B43_MMIO_DMA32_BASE4 0x280

#define	B43_MMIO_DMA32_BASE5 0x2A0

#define	B43_MMIO_DMA64_BASE0 0x200

#define	B43_MMIO_DMA64_BASE1 0x240

#define	B43_MMIO_DMA64_BASE2 0x280

#define	B43_MMIO_DMA64_BASE3 0x2C0

#define	B43_MMIO_DMA64_BASE4 0x300

#define	B43_MMIO_DMA64_BASE5 0x340

#define	B43_MMIO_PIO_BASE0 0x300

#define	B43_MMIO_PIO_BASE1 0x310

#define	B43_MMIO_PIO_BASE2 0x320

#define	B43_MMIO_PIO_BASE3 0x330

#define	B43_MMIO_PIO_BASE4 0x340

#define	B43_MMIO_PIO_BASE5 0x350

#define	B43_MMIO_PIO_BASE6 0x360

#define	B43_MMIO_PIO_BASE7 0x370

#define	B43_MMIO_PIO11_BASE0 0x200

#define	B43_MMIO_PIO11_BASE1 0x240

#define	B43_MMIO_PIO11_BASE2 0x280

#define	B43_MMIO_PIO11_BASE3 0x2C0

#define	B43_MMIO_PIO11_BASE4 0x300

#define	B43_MMIO_PIO11_BASE5 0x340

#define	B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */

#define	B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */

#define	B43_MMIO_PHY_VER 0x3E0

#define	B43_MMIO_PHY_RADIO 0x3E2

#define	B43_MMIO_PHY0 0x3E6

#define	B43_MMIO_ANTENNA 0x3E8

#define	B43_MMIO_CHANNEL 0x3F0

#define	B43_MMIO_CHANNEL_EXT 0x3F4

#define	B43_MMIO_RADIO_CONTROL 0x3F6

#define	B43_MMIO_RADIO_DATA_HIGH 0x3F8

#define	B43_MMIO_RADIO_DATA_LOW 0x3FA

#define	B43_MMIO_PHY_CONTROL 0x3FC

#define	B43_MMIO_PHY_DATA 0x3FE

#define	B43_MMIO_MACFILTER_CONTROL 0x420

#define	B43_MMIO_MACFILTER_DATA 0x422

#define	B43_MMIO_RCMTA_COUNT 0x43C

#define	B43_MMIO_PSM_PHY_HDR 0x492

#define	B43_MMIO_RADIO_HWENABLED_LO 0x49A

#define	B43_MMIO_GPIO_CONTROL 0x49C

#define	B43_MMIO_GPIO_MASK 0x49E

#define	B43_MMIO_TXE0_CTL 0x500

#define	B43_MMIO_TXE0_AUX 0x502

#define	B43_MMIO_TXE0_TS_LOC 0x504

#define	B43_MMIO_TXE0_TIME_OUT 0x506

#define	B43_MMIO_TXE0_WM_0 0x508

#define	B43_MMIO_TXE0_WM_1 0x50A

#define	B43_MMIO_TXE0_PHYCTL 0x50C

#define	B43_MMIO_TXE0_STATUS 0x50E

#define	B43_MMIO_TXE0_MMPLCP0 0x510

#define	B43_MMIO_TXE0_MMPLCP1 0x512

#define	B43_MMIO_TXE0_PHYCTL1 0x514

#define	B43_MMIO_XMTFIFODEF 0x520

#define	B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */

#define	B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */

#define	B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */

#define	B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */

#define	B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */

#define	B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */

#define	B43_MMIO_XMTFIFOCMD 0x540

#define	B43_MMIO_XMTFIFOFLUSH 0x542

#define	B43_MMIO_XMTFIFOTHRESH 0x544

#define	B43_MMIO_XMTFIFORDY 0x546

#define	B43_MMIO_XMTFIFOPRIRDY 0x548

#define	B43_MMIO_XMTFIFORQPRI 0x54A

#define	B43_MMIO_XMTTPLATETXPTR 0x54C

#define	B43_MMIO_XMTTPLATEPTR 0x550

#define	B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */

#define	B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */

#define	B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */

#define	B43_MMIO_XMTTPLATEDATALO 0x560

#define	B43_MMIO_XMTTPLATEDATAHI 0x562

#define	B43_MMIO_XMTSEL 0x568

#define	B43_MMIO_XMTTXCNT 0x56A

#define	B43_MMIO_XMTTXSHMADDR 0x56C

#define	B43_MMIO_TSF_CFP_START_LOW 0x604

#define	B43_MMIO_TSF_CFP_START_HIGH 0x606

#define	B43_MMIO_TSF_CFP_PRETBTT 0x612

#define	B43_MMIO_TSF_CLK_FRAC_LOW 0x62E

#define	B43_MMIO_TSF_CLK_FRAC_HIGH 0x630

#define	B43_MMIO_TSF_0 0x632 /* core rev < 3 only */

#define	B43_MMIO_TSF_1 0x634 /* core rev < 3 only */

#define	B43_MMIO_TSF_2 0x636 /* core rev < 3 only */

#define	B43_MMIO_TSF_3 0x638 /* core rev < 3 only */

#define	B43_MMIO_RNG 0x65A

#define	B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */

#define	B43_MMIO_IFSCTL 0x688 /* Interframe space control */

#define	B43_MMIO_IFSSTAT 0x690

#define	B43_MMIO_IFSMEDBUSYCTL 0x692

#define	B43_MMIO_IFTXDUR 0x694

#define	B43_MMIO_IFSCTL_USE_EDCF 0x0004

#define	B43_MMIO_POWERUP_DELAY 0x6A8

#define	B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */

#define	B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */

#define	B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */

#define	B43_MMIO_WEPCTL 0x7C0

#define	B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */

#define	B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */

#define	B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */

#define	B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */

#define	B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */

#define	B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */

#define	B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */

#define	B43_BFL_ENETADM 0x0080 /* has ADMtek switch */

#define	B43_BFL_ENETVLAN 0x0100 /* can do vlan */

#define	B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */

#define	B43_BFL_NOPCI 0x0400 /* leaves PCI floating */

#define	B43_BFL_FEM 0x0800 /* supports the Front End Module */

#define	B43_BFL_EXTLNA 0x1000 /* has an external LNA */

#define	B43_BFL_HGPA 0x2000 /* had high gain PA */

#define	B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */

#define	B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */

#define	B43_BFH_NOPA 0x0001 /* has no PA */

#define	B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */

#define	B43_BFH_PAREF 0x0004 /* uses the PARef LDO */

#define	B43_BFH_3TSWITCH

#define	B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */

#define	B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */

#define	B43_BFH_FEM_BT

#define	B43_BFH_NOCBUCK 0x0080

#define	B43_BFH_PALDO 0x0200

#define	B43_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */

#define	B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */

#define	B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */

#define	B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */

#define	B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */

#define	B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */

#define	B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */

#define	B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */

#define	B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */

#define	B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */

#define	B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */

#define	B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */

#define	B43_BFL2_SINGLEANT_CCK 0x1000

#define	B43_BFL2_2G_SPUR_WAR 0x2000

#define	B43_BFH2_GPLL_WAR2 0x0001

#define	B43_BFH2_IPALVLSHIFT_3P3 0x0002

#define	B43_BFH2_INTERNDET_TXIQCAL 0x0004

#define	B43_BFH2_XTALBUFOUTEN 0x0008

#define	B43_GPIO_CONTROL 0x6c

#define	B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */

#define	B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */

#define	B43_SHM_AUTOINC_RW

#define	B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */

#define	B43_SHM_SH_PCTLWDPOS 0x0008

#define	B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */

#define	B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */

#define	B43_SHM_SH_PHYVER 0x0050 /* PHY version */

#define	B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */

#define	B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */

#define	B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */

#define	B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */

#define	B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */

#define	B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */

#define	B43_SHM_SH_RADAR 0x0066 /* Radar register */

#define	B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */

#define	B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */

#define	B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */

#define	B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */

#define	B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */

#define	B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */

#define	B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */

#define	B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */

#define	B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */

#define	B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */

#define	B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */

#define	B43_TSSI_MAX 0x7F /* Max value for one TSSI value */

#define	B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */

#define	B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */

#define	B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */

#define	B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */

#define	B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */

#define	B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */

#define	B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */

#define	B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */

#define	B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */

#define	B43_SHM_SH_KTP 0x0056 /* Key table pointer */

#define	B43_SHM_SH_TKIPTSCTTAK 0x0318

#define	B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */

#define	B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */

#define	B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */

#define	B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */

#define	B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */

#define	B43_SHM_SH_SLOTT 0x0010 /* Slot time */

#define	B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */

#define	B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */

#define	B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */

#define	B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */

#define	B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */

#define	B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */

#define	B43_SHM_SH_DTIMP 0x0012 /* DTIP period */

#define	B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */

#define	B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */

#define	B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */

#define	B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */

#define	B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */

#define	B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */

#define	B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */

#define	B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */

#define	B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */

#define	B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */

#define	B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */

#define	B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */

#define	B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */

#define	B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */

#define	B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */

#define	B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */

#define	B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */

#define	B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */

#define	B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */

#define	B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */

#define	B43_SHM_SH_UCODESTAT_INVALID 0

#define	B43_SHM_SH_UCODESTAT_INIT 1

#define	B43_SHM_SH_UCODESTAT_ACTIVE 2

#define	B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */

#define	B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */

#define	B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */

#define	B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */

#define	B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */

#define	B43_SHM_SH_NPHY_TXIQW0 0x0700

#define	B43_SHM_SH_NPHY_TXIQW1 0x0702

#define	B43_SHM_SH_NPHY_TXIQW2 0x0704

#define	B43_SHM_SH_NPHY_TXIQW3 0x0706

#define	B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708

#define	B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E

#define	B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */

#define	B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */

#define	B43_SHM_SC_CURCONT 0x0005 /* Current contention window */

#define	B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */

#define	B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */

#define	B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */

#define	B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */

#define	B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */

#define	B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */

#define	B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */

#define	B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)

#define	B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)

#define	B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */

#define	B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */

#define	B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */

#define	B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */

#define	B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */

#define	B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */

#define	B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */

#define	B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */

#define	B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */

#define	B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */

#define	B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */

#define	B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */

#define	B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */

#define	B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */

#define	B43_HF_RADARW 0x000000002000ULL /* Radar workaround */

#define	B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */

#define	B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */

#define	B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */

#define	B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */

#define	B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */

#define	B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */

#define	B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */

#define	B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */

#define	B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */

#define	B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */

#define	B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */

#define	B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */

#define	B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */

#define	B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */

#define	B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */

#define	B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */

#define	B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */

#define	B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */

#define	B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */

#define	B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */

#define	B43_FWCAPA_HWCRYPTO 0x0001

#define	B43_FWCAPA_QOS 0x0002

#define	B43_MACFILTER_SELF 0x0000

#define	B43_MACFILTER_BSSID 0x0003

#define	B43_PCTL_IN 0xB0

#define	B43_PCTL_OUT 0xB4

#define	B43_PCTL_OUTENABLE 0xB8

#define	B43_PCTL_XTAL_POWERUP 0x40

#define	B43_PCTL_PLL_POWERDOWN 0x80

#define	B43_PCTL_CLK_FAST 0x00

#define	B43_PCTL_CLK_SLOW 0x01

#define	B43_PCTL_CLK_DYNAMIC 0x02

#define	B43_PCTL_FORCE_SLOW 0x0800

#define	B43_PCTL_FORCE_PLL 0x1000

#define	B43_PCTL_DYN_XTAL 0x2000

#define	B43_PHYTYPE_A 0x00

#define	B43_PHYTYPE_B 0x01

#define	B43_PHYTYPE_G 0x02

#define	B43_PHYTYPE_N 0x04

#define	B43_PHYTYPE_LP 0x05

#define	B43_PHYTYPE_SSLPN 0x06

#define	B43_PHYTYPE_HT 0x07

#define	B43_PHYTYPE_LCN 0x08

#define	B43_PHYTYPE_LCNXN 0x09

#define	B43_PHYTYPE_LCN40 0x0a

#define	B43_PHYTYPE_AC 0x0b

#define	B43_PHY_ILT_A_CTRL 0x0072

#define	B43_PHY_ILT_A_DATA1 0x0073

#define	B43_PHY_ILT_A_DATA2 0x0074

#define	B43_PHY_G_LO_CONTROL 0x0810

#define	B43_PHY_ILT_G_CTRL 0x0472

#define	B43_PHY_ILT_G_DATA1 0x0473

#define	B43_PHY_ILT_G_DATA2 0x0474

#define	B43_PHY_A_PCTL 0x007B

#define	B43_PHY_G_PCTL 0x0029

#define	B43_PHY_A_CRS 0x0029

#define	B43_PHY_RADIO_BITFIELD 0x0401

#define	B43_PHY_G_CRS 0x0429

#define	B43_PHY_NRSSILT_CTRL 0x0803

#define	B43_PHY_NRSSILT_DATA 0x0804

#define	B43_RADIOCTL_ID 0x01

#define	B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */

#define	B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */

#define	B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */

#define	B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */

#define	B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */

#define	B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */

#define	B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */

#define	B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */

#define	B43_MACCTL_BE 0x00010000 /* Big Endian mode */

#define	B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */

#define	B43_MACCTL_AP 0x00040000 /* AccessPoint mode */

#define	B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */

#define	B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */

#define	B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */

#define	B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */

#define	B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */

#define	B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */

#define	B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */

#define	B43_MACCTL_AWAKE 0x04000000 /* Device is awake */

#define	B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */

#define	B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */

#define	B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */

#define	B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */

#define	B43_MACCTL_GMODE 0x80000000 /* G Mode */

#define	B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */

#define	B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */

#define	B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */

#define	B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */

#define	B43_MACCMD_BGNOISE 0x00000010 /* Background noise */

#define	B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */

#define	B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */

#define	B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */

#define	B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */

#define	B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */

#define	B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */

#define	B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */

#define	B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */

#define	B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */

#define	B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */

#define	B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */

#define	B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */

#define	B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */

#define	B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */

#define	B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */

#define	B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */

#define	B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */

#define	B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */

#define	B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */

#define	B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */

#define	B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */

#define	B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */

#define	B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */

#define	B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */

#define	B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */

#define	B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */

#define	B43_IRQ_MAC_SUSPENDED 0x00000001

#define	B43_IRQ_BEACON 0x00000002

#define	B43_IRQ_TBTT_INDI 0x00000004

#define	B43_IRQ_BEACON_TX_OK 0x00000008

#define	B43_IRQ_BEACON_CANCEL 0x00000010

#define	B43_IRQ_ATIM_END 0x00000020

#define	B43_IRQ_PMQ 0x00000040

#define	B43_IRQ_PIO_WORKAROUND 0x00000100

#define	B43_IRQ_MAC_TXERR 0x00000200

#define	B43_IRQ_PHY_TXERR 0x00000800

#define	B43_IRQ_PMEVENT 0x00001000

#define	B43_IRQ_TIMER0 0x00002000

#define	B43_IRQ_TIMER1 0x00004000

#define	B43_IRQ_DMA 0x00008000

#define	B43_IRQ_TXFIFO_FLUSH_OK 0x00010000

#define	B43_IRQ_CCA_MEASURE_OK 0x00020000

#define	B43_IRQ_NOISESAMPLE_OK 0x00040000

#define	B43_IRQ_UCODE_DEBUG 0x08000000

#define	B43_IRQ_RFKILL 0x10000000

#define	B43_IRQ_TX_OK 0x20000000

#define	B43_IRQ_PHY_G_CHANGED 0x40000000

#define	B43_IRQ_TIMEOUT 0x80000000

#define	B43_IRQ_ALL 0xFFFFFFFF

#define	B43_IRQ_MASKTEMPLATE

#define	B43_DEBUGIRQ_REASON_REG 63

#define	B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */

#define	B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */

#define	B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */

#define	B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */

#define	B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */

#define	B43_MARKER_ID_REG 2

#define	B43_MARKER_LINE_REG 3

#define	B43_FWPANIC_REASON_REG 3

#define	B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */

#define	B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */

#define	B43_WATCHDOG_REG 1

#define	B43_CCK_RATE_1MB 0x02

#define	B43_CCK_RATE_2MB 0x04

#define	B43_CCK_RATE_5MB 0x0B

#define	B43_CCK_RATE_11MB 0x16

#define	B43_OFDM_RATE_6MB 0x0C

#define	B43_OFDM_RATE_9MB 0x12

#define	B43_OFDM_RATE_12MB 0x18

#define	B43_OFDM_RATE_18MB 0x24

#define	B43_OFDM_RATE_24MB 0x30

#define	B43_OFDM_RATE_36MB 0x48

#define	B43_OFDM_RATE_48MB 0x60

#define	B43_OFDM_RATE_54MB 0x6C

#define	B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)

#define	B43_DEFAULT_SHORT_RETRY_LIMIT 7

#define	B43_DEFAULT_LONG_RETRY_LIMIT 4

#define	B43_PHY_TX_BADNESS_LIMIT 1000

#define	B43_SEC_KEYSIZE 16

#define	B43_NR_GROUP_KEYS 4

#define	B43_NR_PAIRWISE_KEYS 50

#define	B43_FW_TYPE_UCODE 'u'

#define	B43_FW_TYPE_PCM 'p'

#define	B43_FW_TYPE_IV 'i'

#define	B43_IV_OFFSET_MASK 0x7FFF

#define	B43_IV_32BIT 0x8000

#define	B43_QOS_QUEUE_NUM 4

#define	B43_QOS_PARAMS(queue)

#define	B43_QOS_BACKGROUND B43_QOS_PARAMS(0)

#define	B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)

#define	B43_QOS_VIDEO B43_QOS_PARAMS(2)

#define	B43_QOS_VOICE B43_QOS_PARAMS(3)

#define	B43_NR_QOSPARAMS 16

#define	b43_status(wldev) atomic_read(&(wldev)->__init_status)

#define	b43_set_status(wldev, stat)

#define	B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))

#define	INT_TO_Q52(i) ((i) << 2)

#define	Q52_TO_INT(q52) ((q52) >> 2)

#define	Q52_FMT "%u.%u"

#define	Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)

Enumerations
enum	{ B43_SHM_UCODE, B43_SHM_SHARED, B43_SHM_SCRATCH, B43_SHM_HW, B43_SHM_RCMTA }

enum	{ B43_SEC_ALGO_NONE = 0, B43_SEC_ALGO_WEP40, B43_SEC_ALGO_TKIP, B43_SEC_ALGO_AES, B43_SEC_ALGO_WEP104, B43_SEC_ALGO_AES_LEGACY }

enum	{ B43_QOSPARAM_TXOP = 0, B43_QOSPARAM_CWMIN, B43_QOSPARAM_CWMAX, B43_QOSPARAM_CWCUR, B43_QOSPARAM_AIFS, B43_QOSPARAM_BSLOTS, B43_QOSPARAM_REGGAP, B43_QOSPARAM_STATUS }

enum	b43_firmware_file_type { B43_FWTYPE_PROPRIETARY, B43_FWTYPE_OPENSOURCE, B43_NR_FWTYPES }

enum	b43_firmware_hdr_format { B43_FW_HDR_598, B43_FW_HDR_410, B43_FW_HDR_351 }

enum	{ B43_STAT_UNINIT = 0, B43_STAT_INITIALIZED = 1, B43_STAT_STARTED = 2 }

Functions
	__printf (2, 3) void b43info(struct b43_wl *wl

Variables
struct b43_fw_header	__packed

const char *	fmt

Macro Definition Documentation

#define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */

Definition at line 482 of file b43.h.

#define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */

Definition at line 476 of file b43.h.

#define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */

Definition at line 478 of file b43.h.

#define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */

Definition at line 479 of file b43.h.

#define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */

Definition at line 480 of file b43.h.

#define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */

Definition at line 481 of file b43.h.

#define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */

Definition at line 474 of file b43.h.

#define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */

Definition at line 475 of file b43.h.

#define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */

Definition at line 477 of file b43.h.

#define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */

Definition at line 485 of file b43.h.

#define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */

Definition at line 486 of file b43.h.

#define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */

Definition at line 488 of file b43.h.

#define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */

Definition at line 487 of file b43.h.

#define B43_BFH2_GPLL_WAR2 0x0001

Definition at line 212 of file b43.h.

#define B43_BFH2_INTERNDET_TXIQCAL 0x0004

Definition at line 214 of file b43.h.

#define B43_BFH2_IPALVLSHIFT_3P3 0x0002

Definition at line 213 of file b43.h.

#define B43_BFH2_XTALBUFOUTEN 0x0008

Definition at line 215 of file b43.h.

#define B43_BFH_3TSWITCH

Value:

0x0008 /* uses a triple throw switch shared

* with bluetooth */

Definition at line 188 of file b43.h.

#define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */

Definition at line 190 of file b43.h.

#define B43_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */

Definition at line 194 of file b43.h.

#define B43_BFH_FEM_BT

Value:

0x0040 /* has FEM and switch to share antenna

* with bluetooth */

Definition at line 191 of file b43.h.

#define B43_BFH_NOCBUCK 0x0080

Definition at line 192 of file b43.h.

#define B43_BFH_NOPA 0x0001 /* has no PA */

Definition at line 185 of file b43.h.

#define B43_BFH_PALDO 0x0200

Definition at line 193 of file b43.h.

#define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */

Definition at line 187 of file b43.h.

#define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */

Definition at line 189 of file b43.h.

#define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */

Definition at line 186 of file b43.h.

#define B43_BFL2_2G_SPUR_WAR 0x2000

Definition at line 209 of file b43.h.

#define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */

Definition at line 200 of file b43.h.

#define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */

Definition at line 201 of file b43.h.

#define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */

Definition at line 198 of file b43.h.

#define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */

Definition at line 204 of file b43.h.

#define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */

Definition at line 203 of file b43.h.

#define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */

Definition at line 207 of file b43.h.

#define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */

Definition at line 202 of file b43.h.

#define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */

Definition at line 197 of file b43.h.

#define B43_BFL2_SINGLEANT_CCK 0x1000

Definition at line 208 of file b43.h.

#define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */

Definition at line 205 of file b43.h.

#define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */

Definition at line 206 of file b43.h.

#define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */

Definition at line 199 of file b43.h.

#define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */

Definition at line 176 of file b43.h.

#define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */

Definition at line 169 of file b43.h.

#define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */

Definition at line 182 of file b43.h.

#define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */

Definition at line 181 of file b43.h.

#define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */

Definition at line 167 of file b43.h.

#define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */

Definition at line 173 of file b43.h.

#define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */

Definition at line 174 of file b43.h.

#define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */

Definition at line 171 of file b43.h.

#define B43_BFL_ENETVLAN 0x0100 /* can do vlan */

Definition at line 175 of file b43.h.

#define B43_BFL_EXTLNA 0x1000 /* has an external LNA */

Definition at line 179 of file b43.h.

#define B43_BFL_FEM 0x0800 /* supports the Front End Module */

Definition at line 178 of file b43.h.

#define B43_BFL_HGPA 0x2000 /* had high gain PA */

Definition at line 180 of file b43.h.

#define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */

Definition at line 177 of file b43.h.

#define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */

Definition at line 168 of file b43.h.

#define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */

Definition at line 170 of file b43.h.

#define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */

Definition at line 172 of file b43.h.

#define B43_CCK_RATE_11MB 0x16

Definition at line 572 of file b43.h.

#define B43_CCK_RATE_1MB 0x02

Definition at line 569 of file b43.h.

#define B43_CCK_RATE_2MB 0x04

Definition at line 570 of file b43.h.

#define B43_CCK_RATE_5MB 0x0B

Definition at line 571 of file b43.h.

#define B43_DEBUG 0

Definition at line 23 of file b43.h.

#define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */

Definition at line 551 of file b43.h.

#define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */

Definition at line 549 of file b43.h.

#define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */

Definition at line 548 of file b43.h.

#define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */

Definition at line 550 of file b43.h.

#define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */

Definition at line 547 of file b43.h.

#define B43_DEBUGIRQ_REASON_REG 63

Definition at line 545 of file b43.h.

#define B43_DEFAULT_LONG_RETRY_LIMIT 4

Definition at line 585 of file b43.h.

#define B43_DEFAULT_SHORT_RETRY_LIMIT 7

Definition at line 584 of file b43.h.

#define B43_FW_TYPE_IV 'i'

Definition at line 610 of file b43.h.

#define B43_FW_TYPE_PCM 'p'

Definition at line 609 of file b43.h.

#define B43_FW_TYPE_UCODE 'u'

Definition at line 608 of file b43.h.

#define B43_FWCAPA_HWCRYPTO 0x0001

Definition at line 385 of file b43.h.

#define B43_FWCAPA_QOS 0x0002

Definition at line 386 of file b43.h.

#define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */

Definition at line 560 of file b43.h.

#define B43_FWPANIC_REASON_REG 3

Definition at line 558 of file b43.h.

#define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */

Definition at line 561 of file b43.h.

#define B43_GPIO_CONTROL 0x6c

Definition at line 218 of file b43.h.

#define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */

Definition at line 361 of file b43.h.

#define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */

Definition at line 358 of file b43.h.

#define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */

Definition at line 369 of file b43.h.

#define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */

Definition at line 360 of file b43.h.

#define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */

Definition at line 355 of file b43.h.

#define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */

Definition at line 364 of file b43.h.

#define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */

Definition at line 348 of file b43.h.

#define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */

Definition at line 376 of file b43.h.

#define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */

Definition at line 379 of file b43.h.

#define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */

Definition at line 380 of file b43.h.

#define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */

Definition at line 377 of file b43.h.

#define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */

Definition at line 365 of file b43.h.

#define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */

Definition at line 378 of file b43.h.

#define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */

Definition at line 352 of file b43.h.

#define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */

Definition at line 372 of file b43.h.

#define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */

Definition at line 351 of file b43.h.

#define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */

Definition at line 359 of file b43.h.

#define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */

Definition at line 356 of file b43.h.

#define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */

Definition at line 370 of file b43.h.

#define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */

Definition at line 366 of file b43.h.

#define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */

Definition at line 353 of file b43.h.

#define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */

Definition at line 371 of file b43.h.

#define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */

Definition at line 381 of file b43.h.

#define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */

Definition at line 375 of file b43.h.

#define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */

Definition at line 354 of file b43.h.

#define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */

Definition at line 368 of file b43.h.

#define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */

Definition at line 382 of file b43.h.

#define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */

Definition at line 362 of file b43.h.

#define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */

Definition at line 350 of file b43.h.

#define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */

Definition at line 374 of file b43.h.

#define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */

Definition at line 349 of file b43.h.

#define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */

Definition at line 357 of file b43.h.

#define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */

Definition at line 373 of file b43.h.

#define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */

Definition at line 363 of file b43.h.

#define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */

Definition at line 367 of file b43.h.

#define B43_IRQ_ALL 0xFFFFFFFF

Definition at line 531 of file b43.h.

#define B43_IRQ_ATIM_END 0x00000020

Definition at line 513 of file b43.h.

#define B43_IRQ_BEACON 0x00000002

Definition at line 509 of file b43.h.

#define B43_IRQ_BEACON_CANCEL 0x00000010

Definition at line 512 of file b43.h.

#define B43_IRQ_BEACON_TX_OK 0x00000008

Definition at line 511 of file b43.h.

#define B43_IRQ_CCA_MEASURE_OK 0x00020000

Definition at line 523 of file b43.h.

#define B43_IRQ_DMA 0x00008000

Definition at line 521 of file b43.h.

#define B43_IRQ_MAC_SUSPENDED 0x00000001

Definition at line 508 of file b43.h.

#define B43_IRQ_MAC_TXERR 0x00000200

Definition at line 516 of file b43.h.

#define B43_IRQ_MASKTEMPLATE

Value:

(B43_IRQ_TBTT_INDI | \
                     B43_IRQ_ATIM_END | \
                     B43_IRQ_PMQ | \
                     B43_IRQ_MAC_TXERR | \
                     B43_IRQ_PHY_TXERR | \
                     B43_IRQ_DMA | \
                     B43_IRQ_TXFIFO_FLUSH_OK | \
                     B43_IRQ_NOISESAMPLE_OK | \
                     B43_IRQ_UCODE_DEBUG | \
                     B43_IRQ_RFKILL | \
                     B43_IRQ_TX_OK)

Definition at line 532 of file b43.h.

#define B43_IRQ_NOISESAMPLE_OK 0x00040000

Definition at line 524 of file b43.h.

#define B43_IRQ_PHY_G_CHANGED 0x40000000

Definition at line 528 of file b43.h.

#define B43_IRQ_PHY_TXERR 0x00000800

Definition at line 517 of file b43.h.

#define B43_IRQ_PIO_WORKAROUND 0x00000100

Definition at line 515 of file b43.h.

#define B43_IRQ_PMEVENT 0x00001000

Definition at line 518 of file b43.h.

#define B43_IRQ_PMQ 0x00000040

Definition at line 514 of file b43.h.

#define B43_IRQ_RFKILL 0x10000000

Definition at line 526 of file b43.h.

#define B43_IRQ_TBTT_INDI 0x00000004

Definition at line 510 of file b43.h.

#define B43_IRQ_TIMEOUT 0x80000000

Definition at line 529 of file b43.h.

#define B43_IRQ_TIMER0 0x00002000

Definition at line 519 of file b43.h.

#define B43_IRQ_TIMER1 0x00004000

Definition at line 520 of file b43.h.

#define B43_IRQ_TX_OK 0x20000000

Definition at line 527 of file b43.h.

#define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000

Definition at line 522 of file b43.h.

#define B43_IRQ_UCODE_DEBUG 0x08000000

Definition at line 525 of file b43.h.

#define B43_IV_32BIT 0x8000

Definition at line 624 of file b43.h.

#define B43_IV_OFFSET_MASK 0x7FFF

Definition at line 623 of file b43.h.

#define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */

Definition at line 467 of file b43.h.

#define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */

Definition at line 468 of file b43.h.

#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */

Definition at line 471 of file b43.h.

#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */

Definition at line 470 of file b43.h.

#define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */

Definition at line 469 of file b43.h.

#define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */

Definition at line 451 of file b43.h.

#define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */

Definition at line 459 of file b43.h.

#define B43_MACCTL_BE 0x00010000 /* Big Endian mode */

Definition at line 449 of file b43.h.

#define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */

Definition at line 453 of file b43.h.

#define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */

Definition at line 460 of file b43.h.

#define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */

Definition at line 463 of file b43.h.

#define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */

Definition at line 462 of file b43.h.

#define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */

Definition at line 441 of file b43.h.

#define B43_MACCTL_GMODE 0x80000000 /* G Mode */

Definition at line 464 of file b43.h.

#define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */

Definition at line 448 of file b43.h.

#define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */

Definition at line 458 of file b43.h.

#define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */

Definition at line 446 of file b43.h.

#define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */

Definition at line 450 of file b43.h.

#define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */

Definition at line 456 of file b43.h.

#define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */

Definition at line 454 of file b43.h.

#define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */

Definition at line 455 of file b43.h.

#define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */

Definition at line 457 of file b43.h.

#define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */

Definition at line 447 of file b43.h.

#define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */

Definition at line 443 of file b43.h.

#define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */

Definition at line 442 of file b43.h.

#define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */

Definition at line 452 of file b43.h.

#define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */

Definition at line 444 of file b43.h.

#define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */

Definition at line 445 of file b43.h.

#define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */

Definition at line 461 of file b43.h.

#define B43_MACFILTER_BSSID 0x0003

Definition at line 390 of file b43.h.

#define B43_MACFILTER_SELF 0x0000

Definition at line 389 of file b43.h.

#define B43_MARKER_ID_REG 2

Definition at line 554 of file b43.h.

#define B43_MARKER_LINE_REG 3

Definition at line 555 of file b43.h.

#define B43_MMIO_ANTENNA 0x3E8

Definition at line 95 of file b43.h.

#define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */

Definition at line 161 of file b43.h.

#define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */

Definition at line 162 of file b43.h.

#define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */

Definition at line 163 of file b43.h.

#define B43_MMIO_CHANNEL 0x3F0

Definition at line 96 of file b43.h.

#define B43_MMIO_CHANNEL_EXT 0x3F4

Definition at line 97 of file b43.h.

#define B43_MMIO_DMA0_IRQ_MASK 0x24

Definition at line 28 of file b43.h.

#define B43_MMIO_DMA0_REASON 0x20

Definition at line 27 of file b43.h.

#define B43_MMIO_DMA1_IRQ_MASK 0x2C

Definition at line 30 of file b43.h.

#define B43_MMIO_DMA1_REASON 0x28

Definition at line 29 of file b43.h.

#define B43_MMIO_DMA2_IRQ_MASK 0x34

Definition at line 32 of file b43.h.

#define B43_MMIO_DMA2_REASON 0x30

Definition at line 31 of file b43.h.

#define B43_MMIO_DMA32_BASE0 0x200

Definition at line 59 of file b43.h.

#define B43_MMIO_DMA32_BASE1 0x220

Definition at line 60 of file b43.h.

#define B43_MMIO_DMA32_BASE2 0x240

Definition at line 61 of file b43.h.

#define B43_MMIO_DMA32_BASE3 0x260

Definition at line 62 of file b43.h.

#define B43_MMIO_DMA32_BASE4 0x280

Definition at line 63 of file b43.h.

#define B43_MMIO_DMA32_BASE5 0x2A0

Definition at line 64 of file b43.h.

#define B43_MMIO_DMA3_IRQ_MASK 0x3C

Definition at line 34 of file b43.h.

#define B43_MMIO_DMA3_REASON 0x38

Definition at line 33 of file b43.h.

#define B43_MMIO_DMA4_IRQ_MASK 0x44

Definition at line 36 of file b43.h.

#define B43_MMIO_DMA4_REASON 0x40

Definition at line 35 of file b43.h.

#define B43_MMIO_DMA5_IRQ_MASK 0x4C

Definition at line 38 of file b43.h.

#define B43_MMIO_DMA5_REASON 0x48

Definition at line 37 of file b43.h.

#define B43_MMIO_DMA64_BASE0 0x200

Definition at line 66 of file b43.h.

#define B43_MMIO_DMA64_BASE1 0x240

Definition at line 67 of file b43.h.

#define B43_MMIO_DMA64_BASE2 0x280

Definition at line 68 of file b43.h.

#define B43_MMIO_DMA64_BASE3 0x2C0

Definition at line 69 of file b43.h.

#define B43_MMIO_DMA64_BASE4 0x300

Definition at line 70 of file b43.h.

#define B43_MMIO_DMA64_BASE5 0x340

Definition at line 71 of file b43.h.

#define B43_MMIO_GEN_IRQ_MASK 0x12C

Definition at line 42 of file b43.h.

#define B43_MMIO_GEN_IRQ_REASON 0x128

Definition at line 41 of file b43.h.

#define B43_MMIO_GPIO_CONTROL 0x49C

Definition at line 108 of file b43.h.

#define B43_MMIO_GPIO_MASK 0x49E

Definition at line 109 of file b43.h.

#define B43_MMIO_IFSCTL 0x688 /* Interframe space control */

Definition at line 155 of file b43.h.

#define B43_MMIO_IFSCTL_USE_EDCF 0x0004

Definition at line 159 of file b43.h.

#define B43_MMIO_IFSMEDBUSYCTL 0x692

Definition at line 157 of file b43.h.

#define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */

Definition at line 154 of file b43.h.

#define B43_MMIO_IFSSTAT 0x690

Definition at line 156 of file b43.h.

#define B43_MMIO_IFTXDUR 0x694

Definition at line 158 of file b43.h.

#define B43_MMIO_MACCMD 0x124 /* MAC command */

Definition at line 40 of file b43.h.

#define B43_MMIO_MACCTL 0x120 /* MAC control */

Definition at line 39 of file b43.h.

#define B43_MMIO_MACFILTER_CONTROL 0x420

Definition at line 103 of file b43.h.

#define B43_MMIO_MACFILTER_DATA 0x422

Definition at line 104 of file b43.h.

#define B43_MMIO_PHY0 0x3E6

Definition at line 94 of file b43.h.

#define B43_MMIO_PHY_CONTROL 0x3FC

Definition at line 101 of file b43.h.

#define B43_MMIO_PHY_DATA 0x3FE

Definition at line 102 of file b43.h.

#define B43_MMIO_PHY_RADIO 0x3E2

Definition at line 93 of file b43.h.

#define B43_MMIO_PHY_VER 0x3E0

Definition at line 92 of file b43.h.

#define B43_MMIO_PIO11_BASE0 0x200

Definition at line 83 of file b43.h.

#define B43_MMIO_PIO11_BASE1 0x240

Definition at line 84 of file b43.h.

#define B43_MMIO_PIO11_BASE2 0x280

Definition at line 85 of file b43.h.

#define B43_MMIO_PIO11_BASE3 0x2C0

Definition at line 86 of file b43.h.

#define B43_MMIO_PIO11_BASE4 0x300

Definition at line 87 of file b43.h.

#define B43_MMIO_PIO11_BASE5 0x340

Definition at line 88 of file b43.h.

#define B43_MMIO_PIO_BASE0 0x300

Definition at line 74 of file b43.h.

#define B43_MMIO_PIO_BASE1 0x310

Definition at line 75 of file b43.h.

#define B43_MMIO_PIO_BASE2 0x320

Definition at line 76 of file b43.h.

#define B43_MMIO_PIO_BASE3 0x330

Definition at line 77 of file b43.h.

#define B43_MMIO_PIO_BASE4 0x340

Definition at line 78 of file b43.h.

#define B43_MMIO_PIO_BASE5 0x350

Definition at line 79 of file b43.h.

#define B43_MMIO_PIO_BASE6 0x360

Definition at line 80 of file b43.h.

#define B43_MMIO_PIO_BASE7 0x370

Definition at line 81 of file b43.h.

#define B43_MMIO_POWERUP_DELAY 0x6A8

Definition at line 160 of file b43.h.

#define B43_MMIO_PS_STATUS 0x140

Definition at line 45 of file b43.h.

#define B43_MMIO_PSM_PHY_HDR 0x492

Definition at line 106 of file b43.h.

#define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */

Definition at line 90 of file b43.h.

#define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */

Definition at line 91 of file b43.h.

#define B43_MMIO_RADIO_CONTROL 0x3F6

Definition at line 98 of file b43.h.

#define B43_MMIO_RADIO_DATA_HIGH 0x3F8

Definition at line 99 of file b43.h.

#define B43_MMIO_RADIO_DATA_LOW 0x3FA

Definition at line 100 of file b43.h.

#define B43_MMIO_RADIO_HWENABLED_HI 0x158

Definition at line 46 of file b43.h.

#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)

Definition at line 344 of file b43.h.

#define B43_MMIO_RADIO_HWENABLED_LO 0x49A

Definition at line 107 of file b43.h.

#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)

Definition at line 345 of file b43.h.

#define B43_MMIO_RAM_CONTROL 0x130

Definition at line 43 of file b43.h.

#define B43_MMIO_RAM_DATA 0x134

Definition at line 44 of file b43.h.

#define B43_MMIO_RCMTA_COUNT 0x43C

Definition at line 105 of file b43.h.

#define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */

Definition at line 53 of file b43.h.

#define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */

Definition at line 52 of file b43.h.

#define B43_MMIO_RNG 0x65A

Definition at line 153 of file b43.h.

#define B43_MMIO_SHM_CONTROL 0x160

Definition at line 47 of file b43.h.

#define B43_MMIO_SHM_DATA 0x164

Definition at line 48 of file b43.h.

#define B43_MMIO_SHM_DATA_UNALIGNED 0x166

Definition at line 49 of file b43.h.

#define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */

Definition at line 138 of file b43.h.

#define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */

Definition at line 137 of file b43.h.

#define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */

Definition at line 136 of file b43.h.

#define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */

Definition at line 149 of file b43.h.

#define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */

Definition at line 150 of file b43.h.

#define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */

Definition at line 151 of file b43.h.

#define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */

Definition at line 152 of file b43.h.

#define B43_MMIO_TSF_CFP_MAXDUR 0x190

Definition at line 56 of file b43.h.

#define B43_MMIO_TSF_CFP_PRETBTT 0x612

Definition at line 146 of file b43.h.

#define B43_MMIO_TSF_CFP_REP 0x188

Definition at line 54 of file b43.h.

#define B43_MMIO_TSF_CFP_START 0x18C

Definition at line 55 of file b43.h.

#define B43_MMIO_TSF_CFP_START_HIGH 0x606

Definition at line 145 of file b43.h.

#define B43_MMIO_TSF_CFP_START_LOW 0x604

Definition at line 144 of file b43.h.

#define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630

Definition at line 148 of file b43.h.

#define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E

Definition at line 147 of file b43.h.

#define B43_MMIO_TXE0_AUX 0x502

Definition at line 111 of file b43.h.

#define B43_MMIO_TXE0_CTL 0x500

Definition at line 110 of file b43.h.

#define B43_MMIO_TXE0_MMPLCP0 0x510

Definition at line 118 of file b43.h.

#define B43_MMIO_TXE0_MMPLCP1 0x512

Definition at line 119 of file b43.h.

#define B43_MMIO_TXE0_PHYCTL 0x50C

Definition at line 116 of file b43.h.

#define B43_MMIO_TXE0_PHYCTL1 0x514

Definition at line 120 of file b43.h.

#define B43_MMIO_TXE0_STATUS 0x50E

Definition at line 117 of file b43.h.

#define B43_MMIO_TXE0_TIME_OUT 0x506

Definition at line 113 of file b43.h.

#define B43_MMIO_TXE0_TS_LOC 0x504

Definition at line 112 of file b43.h.

#define B43_MMIO_TXE0_WM_0 0x508

Definition at line 114 of file b43.h.

#define B43_MMIO_TXE0_WM_1 0x50A

Definition at line 115 of file b43.h.

#define B43_MMIO_WEPCTL 0x7C0

Definition at line 164 of file b43.h.

#define B43_MMIO_XMITSTAT_0 0x170

Definition at line 50 of file b43.h.

#define B43_MMIO_XMITSTAT_1 0x174

Definition at line 51 of file b43.h.

#define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */

Definition at line 123 of file b43.h.

#define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */

Definition at line 122 of file b43.h.

#define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */

Definition at line 124 of file b43.h.

#define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */

Definition at line 125 of file b43.h.

#define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */

Definition at line 126 of file b43.h.

#define B43_MMIO_XMTFIFOCMD 0x540

Definition at line 128 of file b43.h.

#define B43_MMIO_XMTFIFODEF 0x520

Definition at line 121 of file b43.h.

#define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */

Definition at line 127 of file b43.h.

#define B43_MMIO_XMTFIFOFLUSH 0x542

Definition at line 129 of file b43.h.

#define B43_MMIO_XMTFIFOPRIRDY 0x548

Definition at line 132 of file b43.h.

#define B43_MMIO_XMTFIFORDY 0x546

Definition at line 131 of file b43.h.

#define B43_MMIO_XMTFIFORQPRI 0x54A

Definition at line 133 of file b43.h.

#define B43_MMIO_XMTFIFOTHRESH 0x544

Definition at line 130 of file b43.h.

#define B43_MMIO_XMTSEL 0x568

Definition at line 141 of file b43.h.

#define B43_MMIO_XMTTPLATEDATAHI 0x562

Definition at line 140 of file b43.h.

#define B43_MMIO_XMTTPLATEDATALO 0x560

Definition at line 139 of file b43.h.

#define B43_MMIO_XMTTPLATEPTR 0x550

Definition at line 135 of file b43.h.

#define B43_MMIO_XMTTPLATETXPTR 0x54C

Definition at line 134 of file b43.h.

#define B43_MMIO_XMTTXCNT 0x56A

Definition at line 142 of file b43.h.

#define B43_MMIO_XMTTXSHMADDR 0x56C

Definition at line 143 of file b43.h.

#define B43_NR_GROUP_KEYS 4

Definition at line 592 of file b43.h.

#define B43_NR_PAIRWISE_KEYS 50

Definition at line 594 of file b43.h.

#define B43_NR_QOSPARAMS 16

Definition at line 692 of file b43.h.

#define B43_OFDM_RATE_12MB 0x18

Definition at line 575 of file b43.h.

#define B43_OFDM_RATE_18MB 0x24

Definition at line 576 of file b43.h.

#define B43_OFDM_RATE_24MB 0x30

Definition at line 577 of file b43.h.

#define B43_OFDM_RATE_36MB 0x48

Definition at line 578 of file b43.h.

#define B43_OFDM_RATE_48MB 0x60

Definition at line 579 of file b43.h.

#define B43_OFDM_RATE_54MB 0x6C

Definition at line 580 of file b43.h.

#define B43_OFDM_RATE_6MB 0x0C

Definition at line 573 of file b43.h.

#define B43_OFDM_RATE_9MB 0x12

Definition at line 574 of file b43.h.

#define B43_PCTL_CLK_DYNAMIC 0x02

Definition at line 402 of file b43.h.

#define B43_PCTL_CLK_FAST 0x00

Definition at line 400 of file b43.h.

#define B43_PCTL_CLK_SLOW 0x01

Definition at line 401 of file b43.h.

#define B43_PCTL_DYN_XTAL 0x2000

Definition at line 406 of file b43.h.

#define B43_PCTL_FORCE_PLL 0x1000

Definition at line 405 of file b43.h.

#define B43_PCTL_FORCE_SLOW 0x0800

Definition at line 404 of file b43.h.

#define B43_PCTL_IN 0xB0

Definition at line 393 of file b43.h.

#define B43_PCTL_OUT 0xB4

Definition at line 394 of file b43.h.

#define B43_PCTL_OUTENABLE 0xB8

Definition at line 395 of file b43.h.

#define B43_PCTL_PLL_POWERDOWN 0x80

Definition at line 397 of file b43.h.

#define B43_PCTL_XTAL_POWERUP 0x40

Definition at line 396 of file b43.h.

#define B43_PHY_A_CRS 0x0029

Definition at line 431 of file b43.h.

#define B43_PHY_A_PCTL 0x007B

Definition at line 429 of file b43.h.

#define B43_PHY_G_CRS 0x0429

Definition at line 433 of file b43.h.

#define B43_PHY_G_LO_CONTROL 0x0810

Definition at line 425 of file b43.h.

#define B43_PHY_G_PCTL 0x0029

Definition at line 430 of file b43.h.

#define B43_PHY_ILT_A_CTRL 0x0072

Definition at line 422 of file b43.h.

#define B43_PHY_ILT_A_DATA1 0x0073

Definition at line 423 of file b43.h.

#define B43_PHY_ILT_A_DATA2 0x0074

Definition at line 424 of file b43.h.

#define B43_PHY_ILT_G_CTRL 0x0472

Definition at line 426 of file b43.h.

#define B43_PHY_ILT_G_DATA1 0x0473

Definition at line 427 of file b43.h.

#define B43_PHY_ILT_G_DATA2 0x0474

Definition at line 428 of file b43.h.

#define B43_PHY_NRSSILT_CTRL 0x0803

Definition at line 434 of file b43.h.

#define B43_PHY_NRSSILT_DATA 0x0804

Definition at line 435 of file b43.h.

#define B43_PHY_RADIO_BITFIELD 0x0401

Definition at line 432 of file b43.h.

#define B43_PHY_TX_BADNESS_LIMIT 1000

Definition at line 587 of file b43.h.

#define B43_PHYTYPE_A 0x00

Definition at line 409 of file b43.h.

#define B43_PHYTYPE_AC 0x0b

Definition at line 419 of file b43.h.

#define B43_PHYTYPE_B 0x01

Definition at line 410 of file b43.h.

#define B43_PHYTYPE_G 0x02

Definition at line 411 of file b43.h.

#define B43_PHYTYPE_HT 0x07

Definition at line 415 of file b43.h.

#define B43_PHYTYPE_LCN 0x08

Definition at line 416 of file b43.h.

#define B43_PHYTYPE_LCN40 0x0a

Definition at line 418 of file b43.h.

#define B43_PHYTYPE_LCNXN 0x09

Definition at line 417 of file b43.h.

#define B43_PHYTYPE_LP 0x05

Definition at line 413 of file b43.h.

#define B43_PHYTYPE_N 0x04

Definition at line 412 of file b43.h.

#define B43_PHYTYPE_SSLPN 0x06

Definition at line 414 of file b43.h.

#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)

Definition at line 686 of file b43.h.

#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)

Definition at line 687 of file b43.h.

#define B43_QOS_PARAMS ( queue )

Value:

(B43_SHM_SH_EDCFQ + \

(B43_NR_QOSPARAMS * sizeof(u16) * (queue)))

Definition at line 684 of file b43.h.

#define B43_QOS_QUEUE_NUM 4

Definition at line 683 of file b43.h.

#define B43_QOS_VIDEO B43_QOS_PARAMS(2)

Definition at line 688 of file b43.h.

#define B43_QOS_VOICE B43_QOS_PARAMS(3)

Definition at line 689 of file b43.h.

#define B43_RADIOCTL_ID 0x01

Definition at line 438 of file b43.h.

#define B43_RATE_TO_BASE100KBPS ( rate ) (((rate) * 10) / 2)

Definition at line 582 of file b43.h.

#define B43_SEC_KEYSIZE 16

Definition at line 590 of file b43.h.

#define b43_set_status	(	wldev,
		stat
	)

Value:

do {            \
        atomic_set(&(wldev)->__init_status, (stat));    \
        smp_wmb();                  \
                    } while (0)

Definition at line 788 of file b43.h.

#define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */

Definition at line 229 of file b43.h.

#define B43_SHM_AUTOINC_RW

Value:

(B43_SHM_AUTOINC_R | \

B43_SHM_AUTOINC_W)

Definition at line 231 of file b43.h.

#define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */

Definition at line 230 of file b43.h.

#define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */

Definition at line 338 of file b43.h.

#define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */

Definition at line 339 of file b43.h.

#define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */

Definition at line 334 of file b43.h.

#define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */

Definition at line 337 of file b43.h.

#define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */

Definition at line 341 of file b43.h.

#define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */

Definition at line 336 of file b43.h.

#define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */

Definition at line 333 of file b43.h.

#define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */

Definition at line 332 of file b43.h.

#define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */

Definition at line 340 of file b43.h.

#define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */

Definition at line 335 of file b43.h.

#define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */

Definition at line 296 of file b43.h.

#define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */

Definition at line 241 of file b43.h.

#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */

Definition at line 254 of file b43.h.

#define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */

Definition at line 293 of file b43.h.

#define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */

Definition at line 285 of file b43.h.

#define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */

Definition at line 286 of file b43.h.

#define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */

Definition at line 287 of file b43.h.

#define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */

Definition at line 307 of file b43.h.

#define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */

Definition at line 306 of file b43.h.

#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */

Definition at line 250 of file b43.h.

#define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */

Definition at line 252 of file b43.h.

#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */

Definition at line 251 of file b43.h.

#define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */

Definition at line 270 of file b43.h.

#define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */

Definition at line 289 of file b43.h.

#define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */

Definition at line 282 of file b43.h.

#define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */

Definition at line 279 of file b43.h.

#define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */

Definition at line 277 of file b43.h.

#define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */

Definition at line 294 of file b43.h.

#define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */

Definition at line 238 of file b43.h.

#define B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */

Definition at line 242 of file b43.h.

#define B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */

Definition at line 243 of file b43.h.

#define B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */

Definition at line 244 of file b43.h.

#define B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */

Definition at line 249 of file b43.h.

#define B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */

Definition at line 253 of file b43.h.

#define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */

Definition at line 266 of file b43.h.

#define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */

Definition at line 267 of file b43.h.

#define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */

Definition at line 268 of file b43.h.

#define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */

Definition at line 274 of file b43.h.

#define B43_SHM_SH_KTP 0x0056 /* Key table pointer */

Definition at line 272 of file b43.h.

#define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */

Definition at line 292 of file b43.h.

#define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */

Definition at line 319 of file b43.h.

#define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */

Definition at line 290 of file b43.h.

#define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */

Definition at line 283 of file b43.h.

#define B43_SHM_SH_NPHY_TXIQW0 0x0700

Definition at line 323 of file b43.h.

#define B43_SHM_SH_NPHY_TXIQW1 0x0702

Definition at line 324 of file b43.h.

#define B43_SHM_SH_NPHY_TXIQW2 0x0704

Definition at line 325 of file b43.h.

#define B43_SHM_SH_NPHY_TXIQW3 0x0706

Definition at line 326 of file b43.h.

#define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708

Definition at line 328 of file b43.h.

#define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E

Definition at line 329 of file b43.h.

#define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */

Definition at line 271 of file b43.h.

#define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */

Definition at line 305 of file b43.h.

#define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */

Definition at line 304 of file b43.h.

#define B43_SHM_SH_PCTLWDPOS 0x0008

Definition at line 236 of file b43.h.

#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */

Definition at line 247 of file b43.h.

#define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */

Definition at line 240 of file b43.h.

#define B43_SHM_SH_PHYVER 0x0050 /* PHY version */

Definition at line 239 of file b43.h.

#define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */

Definition at line 321 of file b43.h.

#define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */

Definition at line 301 of file b43.h.

#define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */

Definition at line 302 of file b43.h.

#define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */

Definition at line 298 of file b43.h.

#define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */

Definition at line 299 of file b43.h.

#define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */

Definition at line 300 of file b43.h.

#define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */

Definition at line 275 of file b43.h.

#define B43_SHM_SH_RADAR 0x0066 /* Radar register */

Definition at line 246 of file b43.h.

#define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */

Definition at line 245 of file b43.h.

#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */

Definition at line 248 of file b43.h.

#define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */

Definition at line 237 of file b43.h.

#define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */

Definition at line 291 of file b43.h.

#define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */

Definition at line 261 of file b43.h.

#define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */

Definition at line 262 of file b43.h.

#define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */

Definition at line 263 of file b43.h.

#define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */

Definition at line 264 of file b43.h.

#define B43_SHM_SH_SLOTT 0x0010 /* Slot time */

Definition at line 281 of file b43.h.

#define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */

Definition at line 320 of file b43.h.

#define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */

Definition at line 288 of file b43.h.

#define B43_SHM_SH_TKIPTSCTTAK 0x0318

Definition at line 273 of file b43.h.

#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */

Definition at line 256 of file b43.h.

#define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */

Definition at line 257 of file b43.h.

#define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */

Definition at line 258 of file b43.h.

#define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */

Definition at line 278 of file b43.h.

#define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */

Definition at line 311 of file b43.h.

#define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */

Definition at line 310 of file b43.h.

#define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */

Definition at line 309 of file b43.h.

#define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */

Definition at line 313 of file b43.h.

#define B43_SHM_SH_UCODESTAT_ACTIVE 2

Definition at line 316 of file b43.h.

#define B43_SHM_SH_UCODESTAT_INIT 1

Definition at line 315 of file b43.h.

#define B43_SHM_SH_UCODESTAT_INVALID 0

Definition at line 314 of file b43.h.

#define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */

Definition at line 318 of file b43.h.

#define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */

Definition at line 317 of file b43.h.

#define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */

Definition at line 312 of file b43.h.

#define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */

Definition at line 235 of file b43.h.

#define b43_status ( wldev ) atomic_read(&(wldev)->__init_status)

Definition at line 787 of file b43.h.

#define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */

Definition at line 502 of file b43.h.

#define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */

Definition at line 503 of file b43.h.

#define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */

Definition at line 505 of file b43.h.

#define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */

Definition at line 504 of file b43.h.

#define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */

Definition at line 491 of file b43.h.

#define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */

Definition at line 497 of file b43.h.

#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */

Definition at line 492 of file b43.h.

#define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */

Definition at line 493 of file b43.h.

#define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */

Definition at line 494 of file b43.h.

#define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */

Definition at line 495 of file b43.h.

#define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */

Definition at line 499 of file b43.h.

#define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */

Definition at line 498 of file b43.h.

#define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */

Definition at line 496 of file b43.h.

#define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */

Definition at line 259 of file b43.h.

#define B43_WARN_ON ( x ) __b43_warn_on_dummy(unlikely(!!(x)))

Definition at line 1056 of file b43.h.

#define B43_WATCHDOG_REG 1

Definition at line 564 of file b43.h.

#define INT_TO_Q52 ( i ) ((i) << 2)

Definition at line 1060 of file b43.h.

#define Q52_ARG ( q52 ) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)

Definition at line 1065 of file b43.h.

#define Q52_FMT "%u.%u"

Definition at line 1064 of file b43.h.

#define Q52_TO_INT ( q52 ) ((q52) >> 2)

Definition at line 1062 of file b43.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

B43_SHM_UCODE
B43_SHM_SHARED
B43_SHM_SCRATCH
B43_SHM_HW
B43_SHM_RCMTA

Definition at line 221 of file b43.h.

anonymous enum

Enumerator:

B43_SEC_ALGO_NONE
B43_SEC_ALGO_WEP40
B43_SEC_ALGO_TKIP
B43_SEC_ALGO_AES
B43_SEC_ALGO_WEP104
B43_SEC_ALGO_AES_LEGACY

Definition at line 596 of file b43.h.

anonymous enum

Enumerator:

B43_QOSPARAM_TXOP
B43_QOSPARAM_CWMIN
B43_QOSPARAM_CWMAX
B43_QOSPARAM_CWCUR
B43_QOSPARAM_AIFS
B43_QOSPARAM_BSLOTS
B43_QOSPARAM_REGGAP
B43_QOSPARAM_STATUS