Macros
#define	OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */

#define	OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */

#define	OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */

#define	OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */

#define	OFFSET_TX 0x10 /* Transmit Data Register */

#define	OFFSET_RX 0x18 /* Receive Data Register */

#define	OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */

#define	OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */

#define	OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */

#define	OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */

#define	OFFSET_STAT 0x30 /* Status Register */

#define	SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))

#define	SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))

#define	SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))

#define	SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))

#define	SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))

#define	SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))

#define	SPORT_GET_RX32(sport)

#define	SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))

#define	SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))

#define	SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))

#define	SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))

#define	SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))

#define	SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)

#define	SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)

#define	SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)

#define	SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)

#define	SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)

#define	SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)

#define	SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)

#define	SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)

#define	SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)

#define	SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)

#define	SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)

#define	SPORT_TX_FIFO_SIZE 8

#define	SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin)

#define	SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)

#define	SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)

Macro Definition Documentation

#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */

Definition at line 30 of file bfin_sport_uart.h.

#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */

Definition at line 28 of file bfin_sport_uart.h.

#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */

Definition at line 29 of file bfin_sport_uart.h.

#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */

Definition at line 31 of file bfin_sport_uart.h.

#define OFFSET_RX 0x18 /* Receive Data Register */

Definition at line 27 of file bfin_sport_uart.h.

#define OFFSET_STAT 0x30 /* Status Register */

Definition at line 32 of file bfin_sport_uart.h.

#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */

Definition at line 24 of file bfin_sport_uart.h.

#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */

Definition at line 22 of file bfin_sport_uart.h.

#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */

Definition at line 23 of file bfin_sport_uart.h.

#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */

Definition at line 25 of file bfin_sport_uart.h.

#define OFFSET_TX 0x10 /* Transmit Data Register */

Definition at line 26 of file bfin_sport_uart.h.

#define SPORT_GET_RCLKDIV ( sport ) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))

Definition at line 58 of file bfin_sport_uart.h.

#define SPORT_GET_RCR1 ( sport ) bfin_read16(((sport)->port.membase + OFFSET_RCR1))

Definition at line 56 of file bfin_sport_uart.h.

#define SPORT_GET_RCR2 ( sport ) bfin_read16(((sport)->port.membase + OFFSET_RCR2))

Definition at line 57 of file bfin_sport_uart.h.

#define SPORT_GET_RFSDIV ( sport ) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))

Definition at line 59 of file bfin_sport_uart.h.

#define SPORT_GET_RX ( sport ) bfin_read16(((sport)->port.membase + OFFSET_RX))

Definition at line 39 of file bfin_sport_uart.h.

#define SPORT_GET_RX32 ( sport )

Value:

({ \
    unsigned int __ret; \
    unsigned long flags; \
    if (ANOMALY_05000473) \
        local_irq_save(flags); \
    __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
    if (ANOMALY_05000473) \
        local_irq_restore(flags); \
    __ret; \
})

Definition at line 45 of file bfin_sport_uart.h.

#define SPORT_GET_STAT ( sport ) bfin_read16(((sport)->port.membase + OFFSET_STAT))

Definition at line 60 of file bfin_sport_uart.h.

#define SPORT_GET_TCLKDIV ( sport ) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))

Definition at line 36 of file bfin_sport_uart.h.

#define SPORT_GET_TCR1 ( sport ) bfin_read16(((sport)->port.membase + OFFSET_TCR1))

Definition at line 34 of file bfin_sport_uart.h.

#define SPORT_GET_TCR2 ( sport ) bfin_read16(((sport)->port.membase + OFFSET_TCR2))

Definition at line 35 of file bfin_sport_uart.h.

#define SPORT_GET_TFSDIV ( sport ) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))

Definition at line 37 of file bfin_sport_uart.h.

#define SPORT_GET_TX ( sport ) bfin_read16(((sport)->port.membase + OFFSET_TX))

Definition at line 38 of file bfin_sport_uart.h.

#define SPORT_PUT_RCLKDIV	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)

Definition at line 70 of file bfin_sport_uart.h.

#define SPORT_PUT_RCR1	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)

Definition at line 68 of file bfin_sport_uart.h.

#define SPORT_PUT_RCR2	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)

Definition at line 69 of file bfin_sport_uart.h.

#define SPORT_PUT_RFSDIV	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)

Definition at line 71 of file bfin_sport_uart.h.

#define SPORT_PUT_RX	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_RX), v)

Definition at line 67 of file bfin_sport_uart.h.

#define SPORT_PUT_STAT	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_STAT), v)

Definition at line 72 of file bfin_sport_uart.h.

#define SPORT_PUT_TCLKDIV	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)

Definition at line 64 of file bfin_sport_uart.h.

#define SPORT_PUT_TCR1	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)

Definition at line 62 of file bfin_sport_uart.h.

#define SPORT_PUT_TCR2	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)

Definition at line 63 of file bfin_sport_uart.h.

#define SPORT_PUT_TFSDIV	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)

Definition at line 65 of file bfin_sport_uart.h.

#define SPORT_PUT_TX	(	sport,
		v
	)	bfin_write16(((sport)->port.membase + OFFSET_TX), v)

Definition at line 66 of file bfin_sport_uart.h.

#define SPORT_TX_FIFO_SIZE 8

Definition at line 74 of file bfin_sport_uart.h.

#define SPORT_UART_DISABLE_RTS ( x ) gpio_set_value(x->rts_pin, 1)

Definition at line 77 of file bfin_sport_uart.h.

#define SPORT_UART_ENABLE_RTS ( x ) gpio_set_value(x->rts_pin, 0)

Definition at line 78 of file bfin_sport_uart.h.

#define SPORT_UART_GET_CTS ( x ) gpio_get_value(x->cts_pin)

Definition at line 76 of file bfin_sport_uart.h.

Macros

Macro Definition Documentation