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Data Structures | Macros
bna_hw_defs.h File Reference
#include "bfi_reg.h"

Go to the source code of this file.

Data Structures

struct  bna_reg_offset
 
struct  bna_bit_defn
 
struct  bna_reg
 
struct  bna_dma_addr
 
struct  bna_txq_wi_vector
 
struct  bna_txq_entry
 
struct  bna_rxq_entry
 
struct  bna_cq_entry
 

Macros

#define BFI_ENET_DEF_TXQ   1
 
#define BFI_ENET_DEF_RXP   1
 
#define BFI_ENET_DEF_UCAM   1
 
#define BFI_ENET_DEF_RITSZ   1
 
#define BFI_ENET_MAX_MCAM   256
 
#define BFI_INVALID_RID   -1
 
#define BFI_IBIDX_SIZE   4
 
#define BFI_VLAN_WORD_SHIFT   5 /* 32 bits */
 
#define BFI_VLAN_WORD_MASK   0x1F
 
#define BFI_VLAN_BLOCK_SHIFT   9 /* 512 bits */
 
#define BFI_VLAN_BMASK_ALL   0xFF
 
#define BFI_COALESCING_TIMER_UNIT   5 /* 5us */
 
#define BFI_MAX_COALESCING_TIMEO   0xFF /* in 5us units */
 
#define BFI_MAX_INTERPKT_COUNT   0xFF
 
#define BFI_MAX_INTERPKT_TIMEO   0xF /* in 0.5us units */
 
#define BFI_TX_COALESCING_TIMEO   20 /* 20 * 5 = 100us */
 
#define BFI_TX_INTERPKT_COUNT   32
 
#define BFI_RX_COALESCING_TIMEO   12 /* 12 * 5 = 60us */
 
#define BFI_RX_INTERPKT_COUNT   6 /* Pkt Cnt = 6 */
 
#define BFI_RX_INTERPKT_TIMEO   3 /* 3 * 0.5 = 1.5us */
 
#define BFI_TXQ_WI_SIZE   64 /* bytes */
 
#define BFI_RXQ_WI_SIZE   8 /* bytes */
 
#define BFI_CQ_WI_SIZE   16 /* bytes */
 
#define BFI_TX_MAX_WRR_QUOTA   0xFFF
 
#define BFI_TX_MAX_VECTORS_PER_WI   4
 
#define BFI_TX_MAX_VECTORS_PER_PKT   0xFF
 
#define BFI_TX_MAX_DATA_PER_VECTOR   0xFFFF
 
#define BFI_TX_MAX_DATA_PER_PKT   0xFFFFFF
 
#define BFI_SMALL_RXBUF_SIZE   128
 
#define BFI_TX_MAX_PRIO   8
 
#define BFI_TX_PRIO_MAP_ALL   0xFF
 
#define BNA_PCI_REG_CT_ADDRSZ   (0x40000)
 
#define ct_reg_addr_init(_bna, _pcidev)
 
#define ct_bit_defn_init(_bna, _pcidev)
 
#define ct2_reg_addr_init(_bna, _pcidev)
 
#define ct2_bit_defn_init(_bna, _pcidev)
 
#define bna_reg_addr_init(_bna, _pcidev)
 
#define bna_port_id_get(_bna)   ((_bna)->ioceth.ioc.port_id)
 
#define IB_STATUS_BITS   0x0000ffff
 
#define BNA_IS_MBOX_INTR(_bna, _intr_status)   ((_intr_status) & (_bna)->bits.mbox_status_bits)
 
#define BNA_IS_HALT_INTR(_bna, _intr_status)   ((_intr_status) & (_bna)->bits.halt_status_bits)
 
#define BNA_IS_ERR_INTR(_bna, _intr_status)   ((_intr_status) & (_bna)->bits.error_status_bits)
 
#define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status)
 
#define BNA_IS_INTX_DATA_INTR(_intr_status)   ((_intr_status) & IB_STATUS_BITS)
 
#define bna_halt_clear(_bna)
 
#define bna_intx_disable(_bna, _cur_mask)
 
#define bna_intx_enable(bna, new_mask)   writel((new_mask), (bna)->regs.fn_int_mask)
 
#define bna_mbox_intr_disable(bna)
 
#define bna_mbox_intr_enable(bna)
 
#define bna_intr_status_get(_bna, _status)
 
#define BNA_IB_MAX_ACK_EVENTS   (1 << 15)
 
#define BNA_DOORBELL_Q_PRD_IDX(_pi)   (0x80000000 | (_pi))
 
#define BNA_DOORBELL_Q_STOP   (0x40000000)
 
#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events)   (0x80000000 | ((_timeout) << 16) | (_events))
 
#define BNA_DOORBELL_IB_INT_DISABLE   (0x40000000)
 
#define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer)   ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0));
 
#define bna_ib_ack_disable_irq(_i_dbell, _events)
 
#define bna_ib_ack(_i_dbell, _events)
 
#define bna_ib_start(_bna, _ib, _is_regular)
 
#define bna_ib_stop(_bna, _ib)
 
#define bna_txq_prod_indx_doorbell(_tcb)
 
#define bna_rxq_prod_indx_doorbell(_rcb)
 
#define BNA_TXQ_WI_SEND   (0x402) /* Single Frame Transmission */
 
#define BNA_TXQ_WI_SEND_LSO   (0x403) /* Multi-Frame Transmission */
 
#define BNA_TXQ_WI_EXTENSION   (0x104) /* Extension WI */
 
#define BNA_TXQ_WI_CF_FCOE_CRC   (1 << 8)
 
#define BNA_TXQ_WI_CF_IPID_MODE   (1 << 5)
 
#define BNA_TXQ_WI_CF_INS_PRIO   (1 << 4)
 
#define BNA_TXQ_WI_CF_INS_VLAN   (1 << 3)
 
#define BNA_TXQ_WI_CF_UDP_CKSUM   (1 << 2)
 
#define BNA_TXQ_WI_CF_TCP_CKSUM   (1 << 1)
 
#define BNA_TXQ_WI_CF_IP_CKSUM   (1 << 0)
 
#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset)   (((_hdr_size) << 10) | ((_offset) & 0x3FF))
 
#define BNA_CQ_EF_MAC_ERROR   (1 << 0)
 
#define BNA_CQ_EF_FCS_ERROR   (1 << 1)
 
#define BNA_CQ_EF_TOO_LONG   (1 << 2)
 
#define BNA_CQ_EF_FC_CRC_OK   (1 << 3)
 
#define BNA_CQ_EF_RSVD1   (1 << 4)
 
#define BNA_CQ_EF_L4_CKSUM_OK   (1 << 5)
 
#define BNA_CQ_EF_L3_CKSUM_OK   (1 << 6)
 
#define BNA_CQ_EF_HDS_HEADER   (1 << 7)
 
#define BNA_CQ_EF_UDP   (1 << 8)
 
#define BNA_CQ_EF_TCP   (1 << 9)
 
#define BNA_CQ_EF_IP_OPTIONS   (1 << 10)
 
#define BNA_CQ_EF_IPV6   (1 << 11)
 
#define BNA_CQ_EF_IPV4   (1 << 12)
 
#define BNA_CQ_EF_VLAN   (1 << 13)
 
#define BNA_CQ_EF_RSS   (1 << 14)
 
#define BNA_CQ_EF_RSVD2   (1 << 15)
 
#define BNA_CQ_EF_MCAST_MATCH   (1 << 16)
 
#define BNA_CQ_EF_MCAST   (1 << 17)
 
#define BNA_CQ_EF_BCAST   (1 << 18)
 
#define BNA_CQ_EF_REMOTE   (1 << 19)
 
#define BNA_CQ_EF_LOCAL   (1 << 20)
 

Macro Definition Documentation

#define BFI_COALESCING_TIMER_UNIT   5 /* 5us */

Definition at line 44 of file bna_hw_defs.h.

#define BFI_CQ_WI_SIZE   16 /* bytes */

Definition at line 56 of file bna_hw_defs.h.

#define BFI_ENET_DEF_RITSZ   1

Definition at line 31 of file bna_hw_defs.h.

#define BFI_ENET_DEF_RXP   1

Definition at line 29 of file bna_hw_defs.h.

#define BFI_ENET_DEF_TXQ   1

Definition at line 28 of file bna_hw_defs.h.

#define BFI_ENET_DEF_UCAM   1

Definition at line 30 of file bna_hw_defs.h.

#define BFI_ENET_MAX_MCAM   256

Definition at line 33 of file bna_hw_defs.h.

#define BFI_IBIDX_SIZE   4

Definition at line 37 of file bna_hw_defs.h.

#define BFI_INVALID_RID   -1

Definition at line 35 of file bna_hw_defs.h.

#define BFI_MAX_COALESCING_TIMEO   0xFF /* in 5us units */

Definition at line 45 of file bna_hw_defs.h.

#define BFI_MAX_INTERPKT_COUNT   0xFF

Definition at line 46 of file bna_hw_defs.h.

#define BFI_MAX_INTERPKT_TIMEO   0xF /* in 0.5us units */

Definition at line 47 of file bna_hw_defs.h.

#define BFI_RX_COALESCING_TIMEO   12 /* 12 * 5 = 60us */

Definition at line 50 of file bna_hw_defs.h.

#define BFI_RX_INTERPKT_COUNT   6 /* Pkt Cnt = 6 */

Definition at line 51 of file bna_hw_defs.h.

#define BFI_RX_INTERPKT_TIMEO   3 /* 3 * 0.5 = 1.5us */

Definition at line 52 of file bna_hw_defs.h.

#define BFI_RXQ_WI_SIZE   8 /* bytes */

Definition at line 55 of file bna_hw_defs.h.

#define BFI_SMALL_RXBUF_SIZE   128

Definition at line 65 of file bna_hw_defs.h.

#define BFI_TX_COALESCING_TIMEO   20 /* 20 * 5 = 100us */

Definition at line 48 of file bna_hw_defs.h.

#define BFI_TX_INTERPKT_COUNT   32

Definition at line 49 of file bna_hw_defs.h.

#define BFI_TX_MAX_DATA_PER_PKT   0xFFFFFF

Definition at line 62 of file bna_hw_defs.h.

#define BFI_TX_MAX_DATA_PER_VECTOR   0xFFFF

Definition at line 61 of file bna_hw_defs.h.

#define BFI_TX_MAX_PRIO   8

Definition at line 67 of file bna_hw_defs.h.

#define BFI_TX_MAX_VECTORS_PER_PKT   0xFF

Definition at line 60 of file bna_hw_defs.h.

#define BFI_TX_MAX_VECTORS_PER_WI   4

Definition at line 59 of file bna_hw_defs.h.

#define BFI_TX_MAX_WRR_QUOTA   0xFFF

Definition at line 57 of file bna_hw_defs.h.

#define BFI_TX_PRIO_MAP_ALL   0xFF

Definition at line 68 of file bna_hw_defs.h.

#define BFI_TXQ_WI_SIZE   64 /* bytes */

Definition at line 54 of file bna_hw_defs.h.

#define BFI_VLAN_BLOCK_SHIFT   9 /* 512 bits */

Definition at line 41 of file bna_hw_defs.h.

#define BFI_VLAN_BMASK_ALL   0xFF

Definition at line 42 of file bna_hw_defs.h.

#define BFI_VLAN_WORD_MASK   0x1F

Definition at line 40 of file bna_hw_defs.h.

#define BFI_VLAN_WORD_SHIFT   5 /* 32 bits */

Definition at line 39 of file bna_hw_defs.h.

#define BNA_CQ_EF_BCAST   (1 << 18)

Definition at line 320 of file bna_hw_defs.h.

#define BNA_CQ_EF_FC_CRC_OK   (1 << 3)

Definition at line 301 of file bna_hw_defs.h.

#define BNA_CQ_EF_FCS_ERROR   (1 << 1)

Definition at line 299 of file bna_hw_defs.h.

#define BNA_CQ_EF_HDS_HEADER   (1 << 7)

Definition at line 306 of file bna_hw_defs.h.

#define BNA_CQ_EF_IP_OPTIONS   (1 << 10)

Definition at line 310 of file bna_hw_defs.h.

#define BNA_CQ_EF_IPV4   (1 << 12)

Definition at line 313 of file bna_hw_defs.h.

#define BNA_CQ_EF_IPV6   (1 << 11)

Definition at line 311 of file bna_hw_defs.h.

#define BNA_CQ_EF_L3_CKSUM_OK   (1 << 6)

Definition at line 305 of file bna_hw_defs.h.

#define BNA_CQ_EF_L4_CKSUM_OK   (1 << 5)

Definition at line 304 of file bna_hw_defs.h.

#define BNA_CQ_EF_LOCAL   (1 << 20)

Definition at line 323 of file bna_hw_defs.h.

#define BNA_CQ_EF_MAC_ERROR   (1 << 0)

Definition at line 298 of file bna_hw_defs.h.

#define BNA_CQ_EF_MCAST   (1 << 17)

Definition at line 319 of file bna_hw_defs.h.

#define BNA_CQ_EF_MCAST_MATCH   (1 << 16)

Definition at line 318 of file bna_hw_defs.h.

#define BNA_CQ_EF_REMOTE   (1 << 19)

Definition at line 321 of file bna_hw_defs.h.

#define BNA_CQ_EF_RSS   (1 << 14)

Definition at line 315 of file bna_hw_defs.h.

#define BNA_CQ_EF_RSVD1   (1 << 4)

Definition at line 303 of file bna_hw_defs.h.

#define BNA_CQ_EF_RSVD2   (1 << 15)

Definition at line 316 of file bna_hw_defs.h.

#define BNA_CQ_EF_TCP   (1 << 9)

Definition at line 309 of file bna_hw_defs.h.

#define BNA_CQ_EF_TOO_LONG   (1 << 2)

Definition at line 300 of file bna_hw_defs.h.

#define BNA_CQ_EF_UDP   (1 << 8)

Definition at line 308 of file bna_hw_defs.h.

#define BNA_CQ_EF_VLAN   (1 << 13)

Definition at line 314 of file bna_hw_defs.h.

#define BNA_DOORBELL_IB_INT_ACK (   _timeout,
  _events 
)    (0x80000000 | ((_timeout) << 16) | (_events))

Definition at line 221 of file bna_hw_defs.h.

#define BNA_DOORBELL_IB_INT_DISABLE   (0x40000000)

Definition at line 223 of file bna_hw_defs.h.

#define BNA_DOORBELL_Q_PRD_IDX (   _pi)    (0x80000000 | (_pi))

Definition at line 217 of file bna_hw_defs.h.

#define BNA_DOORBELL_Q_STOP   (0x40000000)

Definition at line 218 of file bna_hw_defs.h.

#define bna_halt_clear (   _bna)
Value:
do { \
u32 init_halt; \
init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
init_halt &= ~__FW_INIT_HALT_P; \
writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \
init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
} while (0)

Definition at line 160 of file bna_hw_defs.h.

#define bna_ib_ack (   _i_dbell,
  _events 
)
Value:
(writel(((_i_dbell)->doorbell_ack | (_events)), \
(_i_dbell)->doorbell_addr));

Definition at line 235 of file bna_hw_defs.h.

#define bna_ib_ack_disable_irq (   _i_dbell,
  _events 
)
Value:
(writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \
(_i_dbell)->doorbell_addr));

Definition at line 230 of file bna_hw_defs.h.

#define bna_ib_coalescing_timer_set (   _i_dbell,
  _cls_timer 
)    ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0));

Definition at line 226 of file bna_hw_defs.h.

#define BNA_IB_MAX_ACK_EVENTS   (1 << 15)

Definition at line 214 of file bna_hw_defs.h.

#define bna_ib_start (   _bna,
  _ib,
  _is_regular 
)
Value:
{ \
u32 intx_mask; \
struct bna_ib *ib = _ib; \
if ((ib->intr_type == BNA_INTR_T_INTX)) { \
bna_intx_disable((_bna), intx_mask); \
intx_mask &= ~(ib->intr_vector); \
bna_intx_enable((_bna), intx_mask); \
} \
bna_ib_coalescing_timer_set(&ib->door_bell, \
ib->coalescing_timeo); \
if (_is_regular) \
bna_ib_ack(&ib->door_bell, 0); \
}

Definition at line 239 of file bna_hw_defs.h.

#define bna_ib_stop (   _bna,
  _ib 
)
Value:
{ \
u32 intx_mask; \
struct bna_ib *ib = _ib; \
writel(BNA_DOORBELL_IB_INT_DISABLE, \
ib->door_bell.doorbell_addr); \
if (ib->intr_type == BNA_INTR_T_INTX) { \
bna_intx_disable((_bna), intx_mask); \
intx_mask |= ib->intr_vector; \
bna_intx_enable((_bna), intx_mask); \
} \
}

Definition at line 254 of file bna_hw_defs.h.

#define bna_intr_status_get (   _bna,
  _status 
)
Value:
{ \
(_status) = readl((_bna)->regs.fn_int_status); \
if (_status) { \
writel(((_status) & ~(_bna)->bits.mbox_status_bits), \
(_bna)->regs.fn_int_status); \
} \
}

Definition at line 195 of file bna_hw_defs.h.

#define bna_intx_disable (   _bna,
  _cur_mask 
)
Value:
{ \
(_cur_mask) = readl((_bna)->regs.fn_int_mask); \
writel(0xffffffff, (_bna)->regs.fn_int_mask); \
}

Definition at line 169 of file bna_hw_defs.h.

#define bna_intx_enable (   bna,
  new_mask 
)    writel((new_mask), (bna)->regs.fn_int_mask)

Definition at line 175 of file bna_hw_defs.h.

#define BNA_IS_ERR_INTR (   _bna,
  _intr_status 
)    ((_intr_status) & (_bna)->bits.error_status_bits)

Definition at line 150 of file bna_hw_defs.h.

#define BNA_IS_HALT_INTR (   _bna,
  _intr_status 
)    ((_intr_status) & (_bna)->bits.halt_status_bits)

Definition at line 147 of file bna_hw_defs.h.

#define BNA_IS_INTX_DATA_INTR (   _intr_status)    ((_intr_status) & IB_STATUS_BITS)

Definition at line 157 of file bna_hw_defs.h.

#define BNA_IS_MBOX_ERR_INTR (   _bna,
  _intr_status 
)
Value:
(BNA_IS_MBOX_INTR(_bna, _intr_status) | \
BNA_IS_ERR_INTR(_bna, _intr_status))

Definition at line 153 of file bna_hw_defs.h.

#define BNA_IS_MBOX_INTR (   _bna,
  _intr_status 
)    ((_intr_status) & (_bna)->bits.mbox_status_bits)

Definition at line 144 of file bna_hw_defs.h.

#define bna_mbox_intr_disable (   bna)
Value:
do { \
u32 mask; \
mask = readl((bna)->regs.fn_int_mask); \
writel((mask | (bna)->bits.mbox_mask_bits | \
(bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \
mask = readl((bna)->regs.fn_int_mask); \
} while (0)

Definition at line 177 of file bna_hw_defs.h.

#define bna_mbox_intr_enable (   bna)
Value:
do { \
u32 mask; \
mask = readl((bna)->regs.fn_int_mask); \
writel((mask & ~((bna)->bits.mbox_mask_bits | \
(bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\
mask = readl((bna)->regs.fn_int_mask); \
} while (0)

Definition at line 186 of file bna_hw_defs.h.

#define BNA_PCI_REG_CT_ADDRSZ   (0x40000)

Definition at line 76 of file bna_hw_defs.h.

#define bna_port_id_get (   _bna)    ((_bna)->ioceth.ioc.port_id)

Definition at line 138 of file bna_hw_defs.h.

#define bna_reg_addr_init (   _bna,
  _pcidev 
)
Value:
{ \
switch ((_pcidev)->device_id) { \
case PCI_DEVICE_ID_BROCADE_CT: \
ct_reg_addr_init((_bna), (_pcidev)); \
ct_bit_defn_init((_bna), (_pcidev)); \
break; \
case BFA_PCI_DEVICE_ID_CT2: \
ct2_reg_addr_init((_bna), (_pcidev)); \
ct2_bit_defn_init((_bna), (_pcidev)); \
break; \
} \
}

Definition at line 124 of file bna_hw_defs.h.

#define bna_rxq_prod_indx_doorbell (   _rcb)
Value:
(writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \
(_rcb)->q_dbell));

Definition at line 271 of file bna_hw_defs.h.

#define bna_txq_prod_indx_doorbell (   _tcb)
Value:
(writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
(_tcb)->q_dbell));

Definition at line 267 of file bna_hw_defs.h.

#define BNA_TXQ_WI_CF_FCOE_CRC   (1 << 8)

Definition at line 283 of file bna_hw_defs.h.

#define BNA_TXQ_WI_CF_INS_PRIO   (1 << 4)

Definition at line 285 of file bna_hw_defs.h.

#define BNA_TXQ_WI_CF_INS_VLAN   (1 << 3)

Definition at line 286 of file bna_hw_defs.h.

#define BNA_TXQ_WI_CF_IP_CKSUM   (1 << 0)

Definition at line 289 of file bna_hw_defs.h.

#define BNA_TXQ_WI_CF_IPID_MODE   (1 << 5)

Definition at line 284 of file bna_hw_defs.h.

#define BNA_TXQ_WI_CF_TCP_CKSUM   (1 << 1)

Definition at line 288 of file bna_hw_defs.h.

#define BNA_TXQ_WI_CF_UDP_CKSUM   (1 << 2)

Definition at line 287 of file bna_hw_defs.h.

#define BNA_TXQ_WI_EXTENSION   (0x104) /* Extension WI */

Definition at line 280 of file bna_hw_defs.h.

#define BNA_TXQ_WI_L4_HDR_N_OFFSET (   _hdr_size,
  _offset 
)    (((_hdr_size) << 10) | ((_offset) & 0x3FF))

Definition at line 291 of file bna_hw_defs.h.

#define BNA_TXQ_WI_SEND   (0x402) /* Single Frame Transmission */

Definition at line 278 of file bna_hw_defs.h.

#define BNA_TXQ_WI_SEND_LSO   (0x403) /* Multi-Frame Transmission */

Definition at line 279 of file bna_hw_defs.h.

#define ct2_bit_defn_init (   _bna,
  _pcidev 
)
Value:
{ \
(_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
__HFN_INT_MBOX_LPU1_CT2); \
(_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
__HFN_INT_MBOX_LPU1_CT2); \
(_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2); \
(_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2); \
(_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2; \
(_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2; \
}

Definition at line 112 of file bna_hw_defs.h.

#define ct2_reg_addr_init (   _bna,
  _pcidev 
)
Value:
{ \
(_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \
CT2_HOSTFN_INT_STATUS; \
(_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \
CT2_HOSTFN_INTR_MASK; \
}

Definition at line 104 of file bna_hw_defs.h.

#define ct_bit_defn_init (   _bna,
  _pcidev 
)
Value:
{ \
(_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \
__HFN_INT_MBOX_LPU1); \
(_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \
__HFN_INT_MBOX_LPU1); \
(_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \
(_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \
(_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \
(_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \
}

Definition at line 92 of file bna_hw_defs.h.

#define ct_reg_addr_init (   _bna,
  _pcidev 
)
Value:
{ \
struct bna_reg_offset reg_offset[] = \
{{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK}, \
{HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK}, \
{HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK}, \
{HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} }; \
\
(_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \
reg_offset[(_pcidev)->pci_func].fn_int_status;\
(_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \
reg_offset[(_pcidev)->pci_func].fn_int_mask;\
}

Definition at line 78 of file bna_hw_defs.h.

#define IB_STATUS_BITS   0x0000ffff

Definition at line 142 of file bna_hw_defs.h.

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