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bnx2x_init_ops.h
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1 /* bnx2x_init_ops.h: Broadcom Everest network driver.
2  * Static functions needed during the initialization.
3  * This file is "included" in bnx2x_main.c.
4  *
5  * Copyright (c) 2007-2012 Broadcom Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * Maintained by: Eilon Greenstein <[email protected]>
12  * Written by: Vladislav Zolotarov <[email protected]>
13  */
14 
15 #ifndef BNX2X_INIT_OPS_H
16 #define BNX2X_INIT_OPS_H
17 
18 
19 #ifndef BP_ILT
20 #define BP_ILT(bp) NULL
21 #endif
22 
23 #ifndef BP_FUNC
24 #define BP_FUNC(bp) 0
25 #endif
26 
27 #ifndef BP_PORT
28 #define BP_PORT(bp) 0
29 #endif
30 
31 #ifndef BNX2X_ILT_FREE
32 #define BNX2X_ILT_FREE(x, y, sz)
33 #endif
34 
35 #ifndef BNX2X_ILT_ZALLOC
36 #define BNX2X_ILT_ZALLOC(x, y, sz)
37 #endif
38 
39 #ifndef ILOG2
40 #define ILOG2(x) x
41 #endif
42 
43 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
44 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
45 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp,
46  dma_addr_t phys_addr, u32 addr,
47  u32 len);
48 
49 static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr,
50  const u32 *data, u32 len)
51 {
52  u32 i;
53 
54  for (i = 0; i < len; i++)
55  REG_WR(bp, addr + i*4, data[i]);
56 }
57 
58 static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr,
59  const u32 *data, u32 len)
60 {
61  u32 i;
62 
63  for (i = 0; i < len; i++)
64  bnx2x_reg_wr_ind(bp, addr + i*4, data[i]);
65 }
66 
67 static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len,
68  u8 wb)
69 {
70  if (bp->dmae_ready)
71  bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
72 
73  /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
74  else if (wb && CHIP_IS_E1(bp))
75  bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
76 
77  /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
78  else
79  bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
80 }
81 
82 static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill,
83  u32 len, u8 wb)
84 {
85  u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
86  u32 buf_len32 = buf_len/4;
87  u32 i;
88 
89  memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
90 
91  for (i = 0; i < len; i += buf_len32) {
92  u32 cur_len = min(buf_len32, len - i);
93 
94  bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb);
95  }
96 }
97 
98 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
99 {
100  if (bp->dmae_ready)
101  bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
102 
103  /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
104  else if (CHIP_IS_E1(bp))
105  bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
106 
107  /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
108  else
109  bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
110 }
111 
112 static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr,
113  const u32 *data, u32 len64)
114 {
115  u32 buf_len32 = FW_BUF_SIZE/4;
116  u32 len = len64*2;
117  u64 data64 = 0;
118  u32 i;
119 
120  /* 64 bit value is in a blob: first low DWORD, then high DWORD */
121  data64 = HILO_U64((*(data + 1)), (*data));
122 
123  len64 = min((u32)(FW_BUF_SIZE/8), len64);
124  for (i = 0; i < len64; i++) {
125  u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
126 
127  *pdata = data64;
128  }
129 
130  for (i = 0; i < len; i += buf_len32) {
131  u32 cur_len = min(buf_len32, len - i);
132 
133  bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len);
134  }
135 }
136 
137 /*********************************************************
138  There are different blobs for each PRAM section.
139  In addition, each blob write operation is divided into a few operations
140  in order to decrease the amount of phys. contiguous buffer needed.
141  Thus, when we select a blob the address may be with some offset
142  from the beginning of PRAM section.
143  The same holds for the INT_TABLE sections.
144 **********************************************************/
145 #define IF_IS_INT_TABLE_ADDR(base, addr) \
146  if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
147 
148 #define IF_IS_PRAM_ADDR(base, addr) \
149  if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
150 
151 static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr,
152  const u8 *data)
153 {
154  IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
155  data = INIT_TSEM_INT_TABLE_DATA(bp);
156  else
157  IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
158  data = INIT_CSEM_INT_TABLE_DATA(bp);
159  else
160  IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
161  data = INIT_USEM_INT_TABLE_DATA(bp);
162  else
163  IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
164  data = INIT_XSEM_INT_TABLE_DATA(bp);
165  else
166  IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
167  data = INIT_TSEM_PRAM_DATA(bp);
168  else
169  IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
170  data = INIT_CSEM_PRAM_DATA(bp);
171  else
172  IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
173  data = INIT_USEM_PRAM_DATA(bp);
174  else
175  IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
176  data = INIT_XSEM_PRAM_DATA(bp);
177 
178  return data;
179 }
180 
181 static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr,
182  const u32 *data, u32 len)
183 {
184  if (bp->dmae_ready)
185  VIRT_WR_DMAE_LEN(bp, data, addr, len, 0);
186 
187  /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
188  else if (CHIP_IS_E1(bp))
189  bnx2x_init_ind_wr(bp, addr, data, len);
190 
191  /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
192  else
193  bnx2x_init_str_wr(bp, addr, data, len);
194 }
195 
196 static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo,
197  u32 val_hi)
198 {
199  u32 wb_write[2];
200 
201  wb_write[0] = val_lo;
202  wb_write[1] = val_hi;
203  REG_WR_DMAE_LEN(bp, reg, wb_write, 2);
204 }
205 static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len,
206  u32 blob_off)
207 {
208  const u8 *data = NULL;
209  int rc;
210  u32 i;
211 
212  data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
213 
214  rc = bnx2x_gunzip(bp, data, len);
215  if (rc)
216  return;
217 
218  /* gunzip_outlen is in dwords */
219  len = GUNZIP_OUTLEN(bp);
220  for (i = 0; i < len; i++)
221  ((u32 *)GUNZIP_BUF(bp))[i] =
222  cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
223 
224  bnx2x_write_big_buf_wb(bp, addr, len);
225 }
226 
227 static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
228 {
229  u16 op_start =
230  INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
231  STAGE_START)];
232  u16 op_end =
233  INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
234  STAGE_END)];
235  union init_op *op;
236  u32 op_idx, op_type, addr, len;
237  const u32 *data, *data_base;
238 
239  /* If empty block */
240  if (op_start == op_end)
241  return;
242 
243  data_base = INIT_DATA(bp);
244 
245  for (op_idx = op_start; op_idx < op_end; op_idx++) {
246 
247  op = (union init_op *)&(INIT_OPS(bp)[op_idx]);
248  /* Get generic data */
249  op_type = op->raw.op;
250  addr = op->raw.offset;
251  /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
252  * OP_WR64 (we assume that op_arr_write and op_write have the
253  * same structure).
254  */
255  len = op->arr_wr.data_len;
256  data = data_base + op->arr_wr.data_off;
257 
258  switch (op_type) {
259  case OP_RD:
260  REG_RD(bp, addr);
261  break;
262  case OP_WR:
263  REG_WR(bp, addr, op->write.val);
264  break;
265  case OP_SW:
266  bnx2x_init_str_wr(bp, addr, data, len);
267  break;
268  case OP_WB:
269  bnx2x_init_wr_wb(bp, addr, data, len);
270  break;
271  case OP_ZR:
272  bnx2x_init_fill(bp, addr, 0, op->zero.len, 0);
273  break;
274  case OP_WB_ZR:
275  bnx2x_init_fill(bp, addr, 0, op->zero.len, 1);
276  break;
277  case OP_ZP:
278  bnx2x_init_wr_zp(bp, addr, len,
279  op->arr_wr.data_off);
280  break;
281  case OP_WR_64:
282  bnx2x_init_wr_64(bp, addr, data, len);
283  break;
284  case OP_IF_MODE_AND:
285  /* if any of the flags doesn't match, skip the
286  * conditional block.
287  */
288  if ((INIT_MODE_FLAGS(bp) &
289  op->if_mode.mode_bit_map) !=
290  op->if_mode.mode_bit_map)
291  op_idx += op->if_mode.cmd_offset;
292  break;
293  case OP_IF_MODE_OR:
294  /* if all the flags don't match, skip the conditional
295  * block.
296  */
297  if ((INIT_MODE_FLAGS(bp) &
298  op->if_mode.mode_bit_map) == 0)
299  op_idx += op->if_mode.cmd_offset;
300  break;
301  default:
302  /* Should never get here! */
303 
304  break;
305  }
306  }
307 }
308 
309 
310 /****************************************************************************
311 * PXP Arbiter
312 ****************************************************************************/
313 /*
314  * This code configures the PCI read/write arbiter
315  * which implements a weighted round robin
316  * between the virtual queues in the chip.
317  *
318  * The values were derived for each PCI max payload and max request size.
319  * since max payload and max request size are only known at run time,
320  * this is done as a separate init stage.
321  */
322 
323 #define NUM_WR_Q 13
324 #define NUM_RD_Q 29
325 #define MAX_RD_ORD 3
326 #define MAX_WR_ORD 2
327 
328 /* configuration for one arbiter queue */
329 struct arb_line {
330  int l;
331  int add;
332  int ubound;
333 };
334 
335 /* derived configuration for each read queue for each max request size */
336 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
337 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
338  { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
339  { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
340  { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
341  { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
342  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
343  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
344  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
345  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
346 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
347  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
348  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
349  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
350  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
351  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
352  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
353  { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
354  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
355  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
356 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
357  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
358  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
359  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
360  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
361  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
362  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
363  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
364  { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
365  { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
366 };
367 
368 /* derived configuration for each write queue for each max request size */
369 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
370 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
371  { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
372  { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
373  { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
374  { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
375  { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
376  { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
377  { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
378  { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
379 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
380  { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
381  { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
382  { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
383 };
384 
385 /* register addresses for read queues */
386 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
387 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
388  PXP2_REG_RQ_BW_RD_UBOUND0},
389  {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
390  PXP2_REG_PSWRQ_BW_UB1},
391  {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
392  PXP2_REG_PSWRQ_BW_UB2},
393  {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
394  PXP2_REG_PSWRQ_BW_UB3},
395  {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
396  PXP2_REG_RQ_BW_RD_UBOUND4},
397  {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
398  PXP2_REG_RQ_BW_RD_UBOUND5},
399  {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
400  PXP2_REG_PSWRQ_BW_UB6},
401  {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
402  PXP2_REG_PSWRQ_BW_UB7},
403  {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
404  PXP2_REG_PSWRQ_BW_UB8},
405 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
406  PXP2_REG_PSWRQ_BW_UB9},
407  {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
408  PXP2_REG_PSWRQ_BW_UB10},
409  {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
410  PXP2_REG_PSWRQ_BW_UB11},
411  {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
412  PXP2_REG_RQ_BW_RD_UBOUND12},
413  {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
414  PXP2_REG_RQ_BW_RD_UBOUND13},
415  {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
416  PXP2_REG_RQ_BW_RD_UBOUND14},
417  {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
418  PXP2_REG_RQ_BW_RD_UBOUND15},
419  {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
420  PXP2_REG_RQ_BW_RD_UBOUND16},
421  {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
422  PXP2_REG_RQ_BW_RD_UBOUND17},
423  {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
424  PXP2_REG_RQ_BW_RD_UBOUND18},
425 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
426  PXP2_REG_RQ_BW_RD_UBOUND19},
427  {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
428  PXP2_REG_RQ_BW_RD_UBOUND20},
429  {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
430  PXP2_REG_RQ_BW_RD_UBOUND22},
431  {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
432  PXP2_REG_RQ_BW_RD_UBOUND23},
433  {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
434  PXP2_REG_RQ_BW_RD_UBOUND24},
435  {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
436  PXP2_REG_RQ_BW_RD_UBOUND25},
437  {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
438  PXP2_REG_RQ_BW_RD_UBOUND26},
439  {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
440  PXP2_REG_RQ_BW_RD_UBOUND27},
441  {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
442  PXP2_REG_PSWRQ_BW_UB28}
443 };
444 
445 /* register addresses for write queues */
446 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
447 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
448  PXP2_REG_PSWRQ_BW_UB1},
449  {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
450  PXP2_REG_PSWRQ_BW_UB2},
451  {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
452  PXP2_REG_PSWRQ_BW_UB3},
453  {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
454  PXP2_REG_PSWRQ_BW_UB6},
455  {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
456  PXP2_REG_PSWRQ_BW_UB7},
457  {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
458  PXP2_REG_PSWRQ_BW_UB8},
459  {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
460  PXP2_REG_PSWRQ_BW_UB9},
461  {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
462  PXP2_REG_PSWRQ_BW_UB10},
463  {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
464  PXP2_REG_PSWRQ_BW_UB11},
465 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
466  PXP2_REG_PSWRQ_BW_UB28},
467  {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
468  PXP2_REG_RQ_BW_WR_UBOUND29},
469  {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
470  PXP2_REG_RQ_BW_WR_UBOUND30}
471 };
472 
473 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order,
474  int w_order)
475 {
476  u32 val, i;
477 
478  if (r_order > MAX_RD_ORD) {
479  DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
480  r_order, MAX_RD_ORD);
481  r_order = MAX_RD_ORD;
482  }
483  if (w_order > MAX_WR_ORD) {
484  DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
485  w_order, MAX_WR_ORD);
486  w_order = MAX_WR_ORD;
487  }
488  if (CHIP_REV_IS_FPGA(bp)) {
489  DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
490  w_order = 0;
491  }
492  DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
493 
494  for (i = 0; i < NUM_RD_Q-1; i++) {
495  REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
496  REG_WR(bp, read_arb_addr[i].add,
497  read_arb_data[i][r_order].add);
498  REG_WR(bp, read_arb_addr[i].ubound,
499  read_arb_data[i][r_order].ubound);
500  }
501 
502  for (i = 0; i < NUM_WR_Q-1; i++) {
503  if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
504  (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
505 
506  REG_WR(bp, write_arb_addr[i].l,
507  write_arb_data[i][w_order].l);
508 
509  REG_WR(bp, write_arb_addr[i].add,
510  write_arb_data[i][w_order].add);
511 
512  REG_WR(bp, write_arb_addr[i].ubound,
513  write_arb_data[i][w_order].ubound);
514  } else {
515 
516  val = REG_RD(bp, write_arb_addr[i].l);
517  REG_WR(bp, write_arb_addr[i].l,
518  val | (write_arb_data[i][w_order].l << 10));
519 
520  val = REG_RD(bp, write_arb_addr[i].add);
521  REG_WR(bp, write_arb_addr[i].add,
522  val | (write_arb_data[i][w_order].add << 10));
523 
524  val = REG_RD(bp, write_arb_addr[i].ubound);
525  REG_WR(bp, write_arb_addr[i].ubound,
526  val | (write_arb_data[i][w_order].ubound << 7));
527  }
528  }
529 
530  val = write_arb_data[NUM_WR_Q-1][w_order].add;
531  val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
532  val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
533  REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
534 
535  val = read_arb_data[NUM_RD_Q-1][r_order].add;
536  val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
537  val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
538  REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
539 
540  REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
541  REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
542  REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
543  REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
544 
545  if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD))
546  REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
547 
548  if (CHIP_IS_E3(bp))
549  REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
550  else if (CHIP_IS_E2(bp))
551  REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
552  else
553  REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
554 
555  if (!CHIP_IS_E1(bp)) {
556  /* MPS w_order optimal TH presently TH
557  * 128 0 0 2
558  * 256 1 1 3
559  * >=512 2 2 3
560  */
561  /* DMAE is special */
562  if (!CHIP_IS_E1H(bp)) {
563  /* E2 can use optimal TH */
564  val = w_order;
565  REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val);
566  } else {
567  val = ((w_order == 0) ? 2 : 3);
568  REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2);
569  }
570 
571  REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
572  REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
573  REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
574  REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
575  REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
576  REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
577  REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
578  REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
579  REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
580  REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
581  }
582 
583  /* Validate number of tags suppoted by device */
584 #define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
585  val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
586  val &= 0xFF;
587  if (val <= 0x20)
588  REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
589 }
590 
591 /****************************************************************************
592 * ILT management
593 ****************************************************************************/
594 /*
595  * This codes hides the low level HW interaction for ILT management and
596  * configuration. The API consists of a shadow ILT table which is set by the
597  * driver and a set of routines to use it to configure the HW.
598  *
599  */
600 
601 /* ILT HW init operations */
602 
603 /* ILT memory management operations */
604 #define ILT_MEMOP_ALLOC 0
605 #define ILT_MEMOP_FREE 1
606 
607 /* the phys address is shifted right 12 bits and has an added
608  * 1=valid bit added to the 53rd bit
609  * then since this is a wide register(TM)
610  * we split it into two 32 bit writes
611  */
612 #define ILT_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
613 #define ILT_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
614 #define ILT_RANGE(f, l) (((l) << 10) | f)
615 
616 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp,
617  struct ilt_line *line, u32 size, u8 memop)
618 {
619  if (memop == ILT_MEMOP_FREE) {
620  BNX2X_ILT_FREE(line->page, line->page_mapping, line->size);
621  return 0;
622  }
623  BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size);
624  if (!line->page)
625  return -1;
626  line->size = size;
627  return 0;
628 }
629 
630 
631 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num,
632  u8 memop)
633 {
634  int i, rc;
635  struct bnx2x_ilt *ilt = BP_ILT(bp);
636  struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
637 
638  if (!ilt || !ilt->lines)
639  return -1;
640 
641  if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
642  return 0;
643 
644  for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
645  rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i],
646  ilt_cli->page_size, memop);
647  }
648  return rc;
649 }
650 
651 static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop)
652 {
653  int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop);
654  if (!rc)
655  rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop);
656  if (!rc)
657  rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
658  if (!rc)
659  rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop);
660 
661  return rc;
662 }
663 
664 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx,
665  dma_addr_t page_mapping)
666 {
667  u32 reg;
668 
669  if (CHIP_IS_E1(bp))
670  reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
671  else
672  reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
673 
674  bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
675 }
676 
677 static void bnx2x_ilt_line_init_op(struct bnx2x *bp,
678  struct bnx2x_ilt *ilt, int idx, u8 initop)
679 {
680  dma_addr_t null_mapping;
681  int abs_idx = ilt->start_line + idx;
682 
683 
684  switch (initop) {
685  case INITOP_INIT:
686  /* set in the init-value array */
687  case INITOP_SET:
688  bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping);
689  break;
690  case INITOP_CLEAR:
691  null_mapping = 0;
692  bnx2x_ilt_line_wr(bp, abs_idx, null_mapping);
693  break;
694  }
695 }
696 
697 static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp,
698  struct ilt_client_info *ilt_cli,
699  u32 ilt_start, u8 initop)
700 {
701  u32 start_reg = 0;
702  u32 end_reg = 0;
703 
704  /* The boundary is either SET or INIT,
705  CLEAR => SET and for now SET ~~ INIT */
706 
707  /* find the appropriate regs */
708  if (CHIP_IS_E1(bp)) {
709  switch (ilt_cli->client_num) {
710  case ILT_CLIENT_CDU:
711  start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
712  break;
713  case ILT_CLIENT_QM:
714  start_reg = PXP2_REG_PSWRQ_QM0_L2P;
715  break;
716  case ILT_CLIENT_SRC:
717  start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
718  break;
719  case ILT_CLIENT_TM:
720  start_reg = PXP2_REG_PSWRQ_TM0_L2P;
721  break;
722  }
723  REG_WR(bp, start_reg + BP_FUNC(bp)*4,
724  ILT_RANGE((ilt_start + ilt_cli->start),
725  (ilt_start + ilt_cli->end)));
726  } else {
727  switch (ilt_cli->client_num) {
728  case ILT_CLIENT_CDU:
729  start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
730  end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
731  break;
732  case ILT_CLIENT_QM:
733  start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
734  end_reg = PXP2_REG_RQ_QM_LAST_ILT;
735  break;
736  case ILT_CLIENT_SRC:
737  start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
738  end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
739  break;
740  case ILT_CLIENT_TM:
741  start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
742  end_reg = PXP2_REG_RQ_TM_LAST_ILT;
743  break;
744  }
745  REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));
746  REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
747  }
748 }
749 
750 static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp,
751  struct bnx2x_ilt *ilt,
752  struct ilt_client_info *ilt_cli,
753  u8 initop)
754 {
755  int i;
756 
757  if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
758  return;
759 
760  for (i = ilt_cli->start; i <= ilt_cli->end; i++)
761  bnx2x_ilt_line_init_op(bp, ilt, i, initop);
762 
763  /* init/clear the ILT boundries */
764  bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop);
765 }
766 
767 static void bnx2x_ilt_client_init_op(struct bnx2x *bp,
768  struct ilt_client_info *ilt_cli, u8 initop)
769 {
770  struct bnx2x_ilt *ilt = BP_ILT(bp);
771 
772  bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop);
773 }
774 
775 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp,
776  int cli_num, u8 initop)
777 {
778  struct bnx2x_ilt *ilt = BP_ILT(bp);
779  struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
780 
781  bnx2x_ilt_client_init_op(bp, ilt_cli, initop);
782 }
783 
784 static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop)
785 {
786  bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop);
787  bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop);
788  bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
789  bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop);
790 }
791 
792 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num,
793  u32 psz_reg, u8 initop)
794 {
795  struct bnx2x_ilt *ilt = BP_ILT(bp);
796  struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
797 
798  if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
799  return;
800 
801  switch (initop) {
802  case INITOP_INIT:
803  /* set in the init-value array */
804  case INITOP_SET:
805  REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12));
806  break;
807  case INITOP_CLEAR:
808  break;
809  }
810 }
811 
812 /*
813  * called during init common stage, ilt clients should be initialized
814  * prioir to calling this function
815  */
816 static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop)
817 {
818  bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU,
819  PXP2_REG_RQ_CDU_P_SIZE, initop);
820  bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM,
821  PXP2_REG_RQ_QM_P_SIZE, initop);
822  bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC,
823  PXP2_REG_RQ_SRC_P_SIZE, initop);
824  bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM,
825  PXP2_REG_RQ_TM_P_SIZE, initop);
826 }
827 
828 /****************************************************************************
829 * QM initializations
830 ****************************************************************************/
831 #define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
832 #define QM_INIT_MIN_CID_COUNT 31
833 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
834 
835 /* called during init port stage */
836 static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count,
837  u8 initop)
838 {
839  int port = BP_PORT(bp);
840 
841  if (QM_INIT(qm_cid_count)) {
842  switch (initop) {
843  case INITOP_INIT:
844  /* set in the init-value array */
845  case INITOP_SET:
846  REG_WR(bp, QM_REG_CONNNUM_0 + port*4,
847  qm_cid_count/16 - 1);
848  break;
849  case INITOP_CLEAR:
850  break;
851  }
852  }
853 }
854 
855 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count,
856  u32 base_reg, u32 reg)
857 {
858  int i;
859  u32 wb_data[2] = {0, 0};
860  for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
861  REG_WR(bp, base_reg + i*4,
862  qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
863  bnx2x_init_wr_wb(bp, reg + i*8, wb_data, 2);
864  }
865 }
866 
867 /* called during init common stage */
868 static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count,
869  u8 initop)
870 {
871  if (!QM_INIT(qm_cid_count))
872  return;
873 
874  switch (initop) {
875  case INITOP_INIT:
876  /* set in the init-value array */
877  case INITOP_SET:
878  bnx2x_qm_set_ptr_table(bp, qm_cid_count,
879  QM_REG_BASEADDR, QM_REG_PTRTBL);
880  if (CHIP_IS_E1H(bp))
881  bnx2x_qm_set_ptr_table(bp, qm_cid_count,
882  QM_REG_BASEADDR_EXT_A,
883  QM_REG_PTRTBL_EXT_A);
884  break;
885  case INITOP_CLEAR:
886  break;
887  }
888 }
889 
890 /****************************************************************************
891 * SRC initializations
892 ****************************************************************************/
893 #ifdef BCM_CNIC
894 /* called during init func stage */
895 static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2,
896  dma_addr_t t2_mapping, int src_cid_count)
897 {
898  int i;
899  int port = BP_PORT(bp);
900 
901  /* Initialize T2 */
902  for (i = 0; i < src_cid_count-1; i++)
903  t2[i].next = (u64)(t2_mapping +
904  (i+1)*sizeof(struct src_ent));
905 
906  /* tell the searcher where the T2 table is */
907  REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
908 
909  bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16,
910  U64_LO(t2_mapping), U64_HI(t2_mapping));
911 
912  bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16,
913  U64_LO((u64)t2_mapping +
914  (src_cid_count-1) * sizeof(struct src_ent)),
915  U64_HI((u64)t2_mapping +
916  (src_cid_count-1) * sizeof(struct src_ent)));
917 }
918 #endif
919 #endif /* BNX2X_INIT_OPS_H */
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