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#define | DRV_MODULE_VERSION "1.78.00-0" |
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#define | DRV_MODULE_RELDATE "2012/09/27" |
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#define | BNX2X_BC_VER 0x040200 |
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#define | BNX2X_MIN_MSIX_VEC_CNT 2 |
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#define | BNX2X_MSIX_VEC_FP_START 1 |
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#define | DRV_MODULE_NAME "bnx2x" |
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#define | BNX2X_MSG_OFF 0x0 |
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#define | BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ |
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#define | BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ |
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#define | BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ |
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#define | BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ |
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#define | BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ |
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#define | BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ |
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#define | BNX2X_MSG_IOV 0x0800000 |
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#define | BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ |
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#define | BNX2X_MSG_ETHTOOL 0x4000000 |
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#define | BNX2X_MSG_DCB 0x8000000 |
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#define | DP(__mask, fmt,...) |
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#define | DP_CONT(__mask, fmt,...) |
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#define | BNX2X_DBG_ERR(fmt,...) |
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#define | BNX2X_ERR(fmt,...) |
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#define | BNX2X_ERROR(fmt,...) pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) |
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#define | BNX2X_DEV_INFO(fmt,...) |
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#define | bnx2x_panic() |
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#define | bnx2x_mc_addr(ha) ((ha)->addr) |
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#define | bnx2x_uc_addr(ha) ((ha)->addr) |
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#define | U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
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#define | U64_HI(x) (u32)(((u64)(x)) >> 32) |
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#define | HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) |
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#define | REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
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#define | REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
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#define | REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) |
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#define | REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
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#define | REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) |
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#define | REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
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#define | REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
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#define | REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
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#define | REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) |
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#define | REG_RD_DMAE(bp, offset, valp, len32) |
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#define | REG_WR_DMAE(bp, offset, valp, len32) |
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#define | REG_WR_DMAE_LEN(bp, offset, valp, len32) REG_WR_DMAE(bp, offset, valp, len32) |
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#define | VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) |
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#define | SHMEM_ADDR(bp, field) |
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#define | SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) |
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#define | SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) |
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#define | SHMEM2_ADDR(bp, field) |
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#define | SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) |
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#define | SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) |
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#define | MF_CFG_ADDR(bp, field) |
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#define | MF2_CFG_ADDR(bp, field) |
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#define | MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
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#define | MF_CFG_WR(bp, field, val) |
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#define | MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
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#define | SHMEM2_HAS(bp, field) |
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#define | EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
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#define | EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
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#define | HC_SP_INDEX_ETH_DEF_CONS 3 |
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#define | HC_SP_INDEX_EQ_CONS 7 |
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#define | HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 |
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#define | HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 |
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#define | HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 |
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#define | HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 |
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#define | BNX2X_FCOE_L2_RX_INDEX |
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#define | BNX2X_FCOE_L2_TX_INDEX |
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#define | BNX2X_CNIC_START_ETH_CID(bp) |
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#define | BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) |
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#define | BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) |
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#define | CNIC_PRESENT 0 |
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#define | FCOE_PRESENT 0 |
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#define | NON_ETH_CONTEXT_USE (FCOE_PRESENT) |
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#define | AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |
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#define | SM_RX_ID 0 |
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#define | SM_TX_ID 1 |
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#define | FIRST_TX_ONLY_COS_INDEX 1 |
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#define | FIRST_TX_COS_INDEX 0 |
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#define | CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) |
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#define | CID_COS_TO_TX_ONLY_CID(cid, cos, bp) (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) |
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#define | FP_COS_TO_TXQ(fp, cos, bp) ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) |
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#define | MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) |
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#define | BNX2X_TSO_SPLIT_BD (1<<0) |
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#define | BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) |
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#define | MAX_AGG_QS(bp) |
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#define | FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) |
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#define | FW_PREFETCH_CNT 16 |
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#define | DROPLESS_FC_HEADROOM 100 |
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#define | BCM_PAGE_SHIFT 12 |
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#define | BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) |
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#define | BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) |
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#define | BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
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#define | PAGES_PER_SGE_SHIFT 0 |
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#define | PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) |
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#define | SGE_PAGE_SIZE PAGE_SIZE |
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#define | SGE_PAGE_SHIFT PAGE_SHIFT |
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#define | SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) |
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#define | NUM_RX_SGE_PAGES 2 |
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#define | RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
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#define | NEXT_PAGE_SGE_DESC_CNT 2 |
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#define | MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) |
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#define | RX_SGE_MASK (RX_SGE_CNT - 1) |
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#define | NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) |
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#define | MAX_RX_SGE (NUM_RX_SGE - 1) |
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#define | NEXT_SGE_IDX(x) |
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#define | RX_SGE(x) ((x) & MAX_RX_SGE) |
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#define | NUM_SGE_REQ |
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#define | NUM_SGE_PG_REQ |
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#define | SGE_TH_LO(bp) |
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#define | SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) |
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#define | BIT_VEC64_ELEM_SZ 64 |
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#define | BIT_VEC64_ELEM_SHIFT 6 |
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#define | BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) |
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#define | __BIT_VEC64_SET_BIT(el, bit) |
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#define | __BIT_VEC64_CLEAR_BIT(el, bit) |
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#define | BIT_VEC64_SET_BIT(vec64, idx) |
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#define | BIT_VEC64_CLEAR_BIT(vec64, idx) |
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#define | BIT_VEC64_TEST_BIT(vec64, idx) |
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#define | BIT_VEC64_ONES_MASK(idx) (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) |
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#define | BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) |
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#define | RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) |
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#define | RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
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#define | NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) |
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#define | BNX2X_TPA_START 1 |
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#define | BNX2X_TPA_STOP 2 |
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#define | BNX2X_TPA_ERROR 3 |
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#define | Q_STATS_OFFSET32(stat_name) (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) |
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#define | BNX2X_NAPI_WEIGHT 128 |
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#define | FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) |
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#define | bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) |
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#define | bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) |
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#define | bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) |
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#define | bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) |
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#define | BNX2X_FCOE_MINI_JUMBO_MTU 2500 |
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#define | FCOE_IDX_OFFSET 0 |
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#define | FCOE_IDX(bp) |
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#define | bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) |
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#define | bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) |
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#define | bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) |
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#define | bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) |
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#define | bnx2x_fcoe_tx(bp, var) |
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#define | IS_ETH_FP(fp) |
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#define | IS_FCOE_FP(fp) false |
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#define | IS_FCOE_IDX(idx) false |
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#define | MAX_FETCH_BD 13 /* HW max BDs per packet */ |
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#define | RX_COPY_THRESH 92 |
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#define | NUM_TX_RINGS 16 |
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#define | TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
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#define | NEXT_PAGE_TX_DESC_CNT 1 |
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#define | MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) |
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#define | NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
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#define | MAX_TX_BD (NUM_TX_BD - 1) |
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#define | MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) |
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#define | NEXT_TX_IDX(x) |
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#define | TX_BD(x) ((x) & MAX_TX_BD) |
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#define | TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) |
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#define | NEXT_CNT_PER_TX_PKT(bds) |
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#define | BDS_PER_TX_PKT 3 |
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#define | MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) |
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#define | MAX_DESC_PER_TX_PKT |
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#define | NUM_RX_RINGS 8 |
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#define | RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
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#define | NEXT_PAGE_RX_DESC_CNT 2 |
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#define | MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) |
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#define | RX_DESC_MASK (RX_DESC_CNT - 1) |
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#define | NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) |
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#define | MAX_RX_BD (NUM_RX_BD - 1) |
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#define | MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) |
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#define | NUM_BD_REQ BRB_SIZE(bp) |
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#define | NUM_BD_PG_REQ |
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#define | BD_TH_LO(bp) |
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#define | BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) |
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#define | MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) |
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#define | MIN_RX_SIZE_TPA_HW |
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#define | MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA |
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#define | MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) |
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#define | MIN_RX_SIZE_NONTPA |
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#define | NEXT_RX_IDX(x) |
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#define | RX_BD(x) ((x) & MAX_RX_BD) |
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#define | CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) |
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#define | NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) |
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#define | RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
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#define | NEXT_PAGE_RCQ_DESC_CNT 1 |
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#define | MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) |
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#define | NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
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#define | MAX_RCQ_BD (NUM_RCQ_BD - 1) |
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#define | MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) |
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#define | NEXT_RCQ_IDX(x) |
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#define | RCQ_BD(x) ((x) & MAX_RCQ_BD) |
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#define | NUM_RCQ_REQ BRB_SIZE(bp) |
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#define | NUM_RCQ_PG_REQ |
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#define | RCQ_TH_LO(bp) |
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#define | RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) |
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#define | SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
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#define | SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) |
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#define | BNX2X_SWCID_SHIFT 17 |
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#define | BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) |
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#define | SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) |
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#define | CQE_CMD(x) |
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#define | BD_UNMAP_ADDR(bd) |
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#define | BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) |
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#define | BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
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#define | BNX2X_DB_SHIFT 7 /* 128 bytes*/ |
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#define | DPM_TRIGER_TYPE 0x40 |
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#define | DOORBELL(bp, cid, val) |
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#define | SKB_CS_OFF(skb) |
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#define | SKB_CS(skb) |
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#define | pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) |
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#define | XMIT_PLAIN 0 |
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#define | XMIT_CSUM_V4 0x1 |
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#define | XMIT_CSUM_V6 0x2 |
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#define | XMIT_CSUM_TCP 0x4 |
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#define | XMIT_GSO_V4 0x8 |
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#define | XMIT_GSO_V6 0x10 |
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#define | XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) |
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#define | XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) |
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#define | CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
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#define | CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) |
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#define | CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) |
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#define | CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) |
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#define | CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) |
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#define | ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
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#define | BNX2X_PRS_FLAG_OVERETH_IPV4(flags) |
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#define | BNX2X_RX_SUM_FIX(cqe) BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
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#define | FP_USB_FUNC_OFF offsetof(struct cstorm_status_block_u, func) |
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#define | FP_CSB_FUNC_OFF offsetof(struct cstorm_status_block_c, func) |
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#define | HC_INDEX_ETH_RX_CQ_CONS 1 |
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#define | HC_INDEX_OOO_TX_CQ_CONS 4 |
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#define | HC_INDEX_ETH_TX_CQ_CONS_COS0 5 |
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#define | HC_INDEX_ETH_TX_CQ_CONS_COS1 6 |
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#define | HC_INDEX_ETH_TX_CQ_CONS_COS2 7 |
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#define | HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 |
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#define | BNX2X_RX_SB_INDEX (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) |
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#define | BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 |
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#define | BNX2X_TX_SB_INDEX_COS0 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) |
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#define | CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
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#define | CHIP_NUM(bp) (bp->common.chip_id >> 16) |
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#define | CHIP_NUM_57710 0x164e |
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#define | CHIP_NUM_57711 0x164f |
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#define | CHIP_NUM_57711E 0x1650 |
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#define | CHIP_NUM_57712 0x1662 |
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#define | CHIP_NUM_57712_MF 0x1663 |
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#define | CHIP_NUM_57713 0x1651 |
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#define | CHIP_NUM_57713E 0x1652 |
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#define | CHIP_NUM_57800 0x168a |
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#define | CHIP_NUM_57800_MF 0x16a5 |
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#define | CHIP_NUM_57810 0x168e |
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#define | CHIP_NUM_57810_MF 0x16ae |
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#define | CHIP_NUM_57811 0x163d |
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#define | CHIP_NUM_57811_MF 0x163e |
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#define | CHIP_NUM_57840_OBSOLETE 0x168d |
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#define | CHIP_NUM_57840_MF_OBSOLETE 0x16ab |
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#define | CHIP_NUM_57840_4_10 0x16a1 |
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#define | CHIP_NUM_57840_2_20 0x16a2 |
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#define | CHIP_NUM_57840_MF 0x16a4 |
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#define | CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
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#define | CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) |
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#define | CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) |
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#define | CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
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#define | CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) |
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#define | CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) |
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#define | CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) |
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#define | CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) |
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#define | CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) |
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#define | CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) |
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#define | CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) |
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#define | CHIP_IS_57840(bp) |
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#define | CHIP_IS_57840_MF(bp) |
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#define | CHIP_IS_E1H(bp) |
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#define | CHIP_IS_E2(bp) |
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#define | CHIP_IS_E3(bp) |
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#define | CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) |
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#define | USES_WARPCORE(bp) (CHIP_IS_E3(bp)) |
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#define | IS_E1H_OFFSET (!CHIP_IS_E1(bp)) |
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#define | CHIP_REV_SHIFT 12 |
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#define | CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) |
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#define | CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) |
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#define | CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) |
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#define | CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) |
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#define | CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) |
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#define | CHIP_REV_IS_EMUL(bp) |
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#define | CHIP_REV_IS_FPGA(bp) |
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#define | CHIP_TIME(bp) |
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#define | CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
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#define | CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) |
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#define | CHIP_REV_SIM(bp) |
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#define | CHIP_REV(bp) |
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#define | CHIP_IS_E3B0(bp) |
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#define | CHIP_IS_E3A0(bp) |
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#define | BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
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#define | BNX2X_NVRAM_TIMEOUT_COUNT 30000 |
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#define | BNX2X_NVRAM_PAGE_SIZE 256 |
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#define | INT_BLOCK_HC 0 |
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#define | INT_BLOCK_IGU 1 |
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#define | INT_BLOCK_MODE_NORMAL 0 |
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#define | INT_BLOCK_MODE_BW_COMP 2 |
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#define | CHIP_INT_MODE_IS_NBC(bp) |
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#define | CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) |
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#define | CHIP_4_PORT_MODE 0x0 |
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#define | CHIP_2_PORT_MODE 0x1 |
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#define | CHIP_PORT_MODE_NONE 0x2 |
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#define | CHIP_MODE(bp) (bp->common.chip_port_mode) |
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#define | CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) |
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#define | BNX2X_IGU_STAS_MSG_VF_CNT 64 |
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#define | BNX2X_IGU_STAS_MSG_PF_CNT 4 |
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#define | SUPPORTED_2500baseX_Full (1 << 15) |
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#define | ADVERTISED_2500baseX_Full (1 << 15) |
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#define | STATS_OFFSET32(stat_name) (offsetof(struct bnx2x_eth_stats, stat_name) / 4) |
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#define | BNX2X_MAX_NUM_OF_VFS 64 |
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#define | BNX2X_VF_ID_INVALID 0xFF |
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#define | FP_SB_MAX_E1x 16 |
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#define | FP_SB_MAX_E2 HC_SB_MAX_SB_E2 |
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#define | CDU_ILT_PAGE_SZ_HW 2 |
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#define | CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ |
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#define | ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
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#define | QM_ILT_PAGE_SZ_HW 0 |
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#define | QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ |
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#define | QM_CID_ROUND 1024 |
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#define | MAX_DMAE_C 8 |
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#define | bnx2x_sp(bp, var) (&bp->slowpath->var) |
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#define | bnx2x_sp_mapping(bp, var) (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) |
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#define | MAX_DYNAMIC_ATTN_GRPS 8 |
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#define | NUM_EQ_PAGES 1 |
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#define | EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) |
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#define | EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) |
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#define | NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) |
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#define | EQ_DESC_MASK (NUM_EQ_DESC - 1) |
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#define | MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) |
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#define | NEXT_EQ_IDX(x) |
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#define | EQ_DESC(x) ((x) & EQ_DESC_MASK) |
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#define | BNX2X_EQ_INDEX |
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#define | BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) |
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#define | BP_PORT(bp) (bp->pfid & 1) |
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#define | BP_FUNC(bp) (bp->pfid) |
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#define | BP_ABS_FUNC(bp) (bp->pf_num) |
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#define | BP_VN(bp) ((bp)->pfid >> 1) |
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#define | BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) |
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#define | BP_L_ID(bp) (BP_VN(bp) << 2) |
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#define | BP_FW_MB_IDX_VN(bp, vn) |
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#define | BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) |
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#define | IRO (bp->iro_arr) |
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#define | ETH_OVREHEAD (ETH_HLEN + 8 + 8) |
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#define | ETH_MIN_PACKET_SIZE 60 |
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#define | ETH_MAX_PACKET_SIZE 1500 |
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#define | ETH_MAX_JUMBO_PACKET_SIZE 9600 |
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#define | ETH_MAX_TPA_HEADER_SIZE 72 |
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#define | BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) |
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#define | BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) |
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#define | BNX2X_FW_RX_ALIGN_END |
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#define | BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
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#define | DEF_SB_IGU_ID 16 |
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#define | DEF_SB_ID HC_SP_SB_ID |
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#define | PCIX_FLAG (1 << 0) |
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#define | PCI_32BIT_FLAG (1 << 1) |
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#define | ONE_PORT_FLAG (1 << 2) |
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#define | NO_WOL_FLAG (1 << 3) |
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#define | USING_DAC_FLAG (1 << 4) |
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#define | USING_MSIX_FLAG (1 << 5) |
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#define | USING_MSI_FLAG (1 << 6) |
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#define | DISABLE_MSI_FLAG (1 << 7) |
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#define | TPA_ENABLE_FLAG (1 << 8) |
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#define | NO_MCP_FLAG (1 << 9) |
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#define | BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
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#define | GRO_ENABLE_FLAG (1 << 10) |
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#define | MF_FUNC_DIS (1 << 11) |
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#define | OWN_CNIC_IRQ (1 << 12) |
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#define | NO_ISCSI_OOO_FLAG (1 << 13) |
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#define | NO_ISCSI_FLAG (1 << 14) |
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#define | NO_FCOE_FLAG (1 << 15) |
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#define | BC_SUPPORTS_PFC_STATS (1 << 17) |
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#define | BC_SUPPORTS_FCOE_FEATURES (1 << 19) |
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#define | USING_SINGLE_MSIX_FLAG (1 << 20) |
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#define | BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) |
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#define | NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) |
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#define | NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) |
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#define | NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) |
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#define | IS_MF(bp) (bp->mf_mode != 0) |
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#define | IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
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#define | IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) |
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#define | IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) |
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#define | BNX2X_MAX_COALESCE_TOUT (0xf0*12) |
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#define | BNX2X_STATE_CLOSED 0 |
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#define | BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
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#define | BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 |
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#define | BNX2X_STATE_OPEN 0x3000 |
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#define | BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
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#define | BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
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#define | BNX2X_STATE_DIAG 0xe000 |
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#define | BNX2X_STATE_ERROR 0xf000 |
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#define | BNX2X_MAX_PRIORITY 8 |
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#define | BNX2X_MAX_ENTRIES_PER_PRI 16 |
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#define | BNX2X_MAX_COS 3 |
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#define | BNX2X_MAX_TX_COS 2 |
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#define | BNX2X_RX_MODE_NONE 0 |
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#define | BNX2X_RX_MODE_NORMAL 1 |
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#define | BNX2X_RX_MODE_ALLMULTI 2 |
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#define | BNX2X_RX_MODE_PROMISC 3 |
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#define | BNX2X_MAX_MULTICAST 64 |
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#define | ILT_MAX_L2_LINES 8 |
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#define | BP_ILT(bp) ((bp)->ilt) |
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#define | ILT_MAX_LINES 256 |
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#define | BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) |
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#define | BNX2X_L2_CID_COUNT(bp) |
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#define | BNX2X_L2_MAX_CID(bp) |
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#define | L2_ILT_LINES(bp) |
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#define | FW_BUF_SIZE 0x8000 |
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#define | GUNZIP_BUF(bp) (bp->gunzip_buf) |
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#define | GUNZIP_PHYS(bp) (bp->gunzip_mapping) |
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#define | GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) |
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#define | INIT_MODE_FLAGS(bp) (bp->init_mode_flags) |
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#define | INIT_OPS(bp) (bp->init_ops) |
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#define | INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) |
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#define | INIT_DATA(bp) (bp->init_data) |
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#define | INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) |
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#define | INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) |
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#define | INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) |
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#define | INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) |
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#define | INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) |
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#define | INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) |
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#define | INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) |
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#define | INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) |
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#define | PHY_FW_VER_LEN 20 |
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#define | BNX2X_DCB_STATE_OFF 0 |
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#define | BNX2X_DCB_STATE_ON 1 |
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#define | BNX2X_DCBX_ENABLED_OFF 0 |
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#define | BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 |
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#define | BNX2X_DCBX_ENABLED_ON_NEG_ON 2 |
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#define | BNX2X_DCBX_ENABLED_INVALID (-1) |
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#define | BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
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#define | BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) |
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#define | BNX2X_NUM_NON_CNIC_QUEUES(bp) |
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#define | BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) |
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#define | is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
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#define | BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) |
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#define | RSS_IPV4_CAP_MASK TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY |
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#define | RSS_IPV4_TCP_CAP_MASK TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY |
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#define | RSS_IPV6_CAP_MASK TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY |
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#define | RSS_IPV6_TCP_CAP_MASK TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY |
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#define | FUNC_FLG_RSS 0x0001 |
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#define | FUNC_FLG_STATS 0x0002 |
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#define | FUNC_FLG_TPA 0x0008 |
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#define | FUNC_FLG_SPQ 0x0010 |
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#define | FUNC_FLG_LEADING 0x0020 /* PF only */ |
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#define | for_each_eth_queue(bp, var) for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
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#define | for_each_nondefault_eth_queue(bp, var) for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
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#define | for_each_queue(bp, var) |
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#define | for_each_rx_queue(bp, var) |
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#define | for_each_tx_queue(bp, var) |
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#define | for_each_nondefault_queue(bp, var) |
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#define | for_each_cos_in_tx_queue(fp, var) for ((var) = 0; (var) < (fp)->max_cos; (var)++) |
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#define | skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) |
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#define | skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) |
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#define | skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) |
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#define | BNX2X_ILT_ZALLOC(x, y, size) |
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#define | BNX2X_ILT_FREE(x, y, size) |
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#define | ILOG2(x) (ilog2((x))) |
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#define | ILT_NUM_PAGE_ENTRIES (3072) |
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#define | ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) |
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#define | FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) |
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#define | ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) |
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#define | ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) |
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#define | LOAD_NORMAL 0 |
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#define | LOAD_OPEN 1 |
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#define | LOAD_DIAG 2 |
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#define | LOAD_LOOPBACK_EXT 3 |
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#define | UNLOAD_NORMAL 0 |
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#define | UNLOAD_CLOSE 1 |
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#define | UNLOAD_RECOVERY 2 |
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#define | DMAE_TIMEOUT -1 |
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#define | DMAE_PCI_ERROR -2 /* E2 and onward */ |
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#define | DMAE_NOT_RDY -3 |
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#define | DMAE_PCI_ERR_FLAG 0x80000000 |
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#define | DMAE_SRC_PCI 0 |
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#define | DMAE_SRC_GRC 1 |
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#define | DMAE_DST_NONE 0 |
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#define | DMAE_DST_PCI 1 |
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#define | DMAE_DST_GRC 2 |
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#define | DMAE_COMP_PCI 0 |
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#define | DMAE_COMP_GRC 1 |
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#define | DMAE_COMP_REGULAR 0 |
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#define | DMAE_COM_SET_ERR 1 |
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#define | DMAE_CMD_SRC_PCI |
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#define | DMAE_CMD_SRC_GRC |
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#define | DMAE_CMD_DST_PCI |
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#define | DMAE_CMD_DST_GRC |
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#define | DMAE_CMD_C_DST_PCI |
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#define | DMAE_CMD_C_DST_GRC |
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#define | DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE |
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#define | DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) |
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#define | DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) |
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#define | DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) |
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#define | DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) |
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#define | DMAE_CMD_PORT_0 0 |
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#define | DMAE_CMD_PORT_1 DMAE_COMMAND_PORT |
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#define | DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET |
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#define | DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET |
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#define | DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT |
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#define | DMAE_SRC_PF 0 |
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#define | DMAE_SRC_VF 1 |
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#define | DMAE_DST_PF 0 |
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#define | DMAE_DST_VF 1 |
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#define | DMAE_C_SRC 0 |
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#define | DMAE_C_DST 1 |
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#define | DMAE_LEN32_RD_MAX 0x80 |
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#define | DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
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#define | DMAE_COMP_VAL |
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#define | MAX_DMAE_C_PER_PORT 8 |
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#define | INIT_DMAE_C(bp) |
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#define | PMF_DMAE_C(bp) |
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#define | PCICFG_LINK_WIDTH 0x1f00000 |
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#define | PCICFG_LINK_WIDTH_SHIFT 20 |
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#define | PCICFG_LINK_SPEED 0xf0000 |
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#define | PCICFG_LINK_SPEED_SHIFT 16 |
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#define | BNX2X_NUM_TESTS_SF 7 |
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#define | BNX2X_NUM_TESTS_MF 3 |
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#define | BNX2X_NUM_TESTS(bp) |
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#define | BNX2X_PHY_LOOPBACK 0 |
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#define | BNX2X_MAC_LOOPBACK 1 |
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#define | BNX2X_EXT_LOOPBACK 2 |
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#define | BNX2X_PHY_LOOPBACK_FAILED 1 |
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#define | BNX2X_MAC_LOOPBACK_FAILED 2 |
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#define | BNX2X_EXT_LOOPBACK_FAILED 3 |
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#define | BNX2X_LOOPBACK_FAILED |
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#define | STROM_ASSERT_ARRAY_SIZE 50 |
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#define | HW_CID(bp, x) |
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#define | SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
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#define | MAX_SP_DESC_CNT (SP_DESC_CNT - 1) |
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#define | BNX2X_BTR 4 |
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#define | MAX_SPQ_PENDING 8 |
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#define | DEF_MIN_RATE 100 |
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#define | RS_PERIODIC_TIMEOUT_USEC 400 |
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#define | QM_ARB_BYTES 160000 |
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#define | MIN_RES 100 |
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#define | MIN_ABOVE_THRESH 32768 |
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#define | T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) |
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#define | FAIR_MEM 2 |
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#define | ATTN_NIG_FOR_FUNC (1L << 8) |
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#define | ATTN_SW_TIMER_4_FUNC (1L << 9) |
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#define | GPIO_2_FUNC (1L << 10) |
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#define | GPIO_3_FUNC (1L << 11) |
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#define | GPIO_4_FUNC (1L << 12) |
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#define | ATTN_GENERAL_ATTN_1 (1L << 13) |
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#define | ATTN_GENERAL_ATTN_2 (1L << 14) |
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#define | ATTN_GENERAL_ATTN_3 (1L << 15) |
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#define | ATTN_GENERAL_ATTN_4 (1L << 13) |
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#define | ATTN_GENERAL_ATTN_5 (1L << 14) |
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#define | ATTN_GENERAL_ATTN_6 (1L << 15) |
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#define | ATTN_HARD_WIRED_MASK 0xff00 |
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#define | ATTENTION_ID 4 |
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#define | BNX2X_PMF_LINK_ASSERT GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) |
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#define | BNX2X_MC_ASSERT_BITS |
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#define | BNX2X_MCP_ASSERT GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) |
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#define | BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
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#define | BNX2X_GRC_RSV |
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#define | HW_INTERRUT_ASSERT_SET_0 |
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#define | HW_PRTY_ASSERT_SET_0 |
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#define | HW_INTERRUT_ASSERT_SET_1 |
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#define | HW_PRTY_ASSERT_SET_1 |
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#define | HW_INTERRUT_ASSERT_SET_2 |
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#define | HW_PRTY_ASSERT_SET_2 |
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#define | HW_PRTY_ASSERT_SET_3 |
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#define | HW_PRTY_ASSERT_SET_4 |
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#define | MULTI_MASK 0x7f |
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#define | DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) |
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#define | DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) |
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#define | DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) |
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#define | DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) |
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#define | DEF_USB_IGU_INDEX_OFF offsetof(struct cstorm_def_status_block_u, igu_index) |
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#define | DEF_CSB_IGU_INDEX_OFF offsetof(struct cstorm_def_status_block_c, igu_index) |
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#define | DEF_XSB_IGU_INDEX_OFF offsetof(struct xstorm_def_status_block, igu_index) |
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#define | DEF_TSB_IGU_INDEX_OFF offsetof(struct tstorm_def_status_block, igu_index) |
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#define | DEF_USB_SEGMENT_OFF offsetof(struct cstorm_def_status_block_u, segment) |
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#define | DEF_CSB_SEGMENT_OFF offsetof(struct cstorm_def_status_block_c, segment) |
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#define | DEF_XSB_SEGMENT_OFF offsetof(struct xstorm_def_status_block, segment) |
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#define | DEF_TSB_SEGMENT_OFF offsetof(struct tstorm_def_status_block, segment) |
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#define | BNX2X_SP_DSB_INDEX |
|
#define | SET_FLAG(value, mask, flag) |
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#define | GET_FLAG(value, mask) (((value) & (mask)) >> (mask##_SHIFT)) |
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#define | GET_FIELD(value, fname) (((value) & (fname##_MASK)) >> (fname##_SHIFT)) |
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#define | CAM_IS_INVALID(x) |
|
#define | MC_HASH_SIZE 8 |
|
#define | MC_HASH_OFFSET(bp, i) |
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#define | PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 |
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#define | BNX2X_VPD_LEN 128 |
|
#define | VENDOR_ID_LEN 4 |
|
#define | CMNG_FNS_NONE 0 |
|
#define | CMNG_FNS_MINMAX 1 |
|
#define | HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ |
|
#define | HC_SEG_ACCESS_ATTN 4 |
|
#define | HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ |
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#define | BNX2X_MF_SD_PROTOCOL(bp) ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) |
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#define | IS_MF_FCOE_AFEX(bp) false |
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