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Data Structures | Macros | Functions
ca0106.h File Reference
#include "ca_midi.h"

Go to the source code of this file.

Data Structures

struct  snd_ca0106_channel
 
struct  snd_ca0106_pcm
 
struct  snd_ca0106_details
 
struct  snd_ca0106
 

Macros

#define PTR   0x00 /* Indexed register set pointer register */
 
#define DATA   0x04 /* Indexed register set data register */
 
#define IPR   0x08 /* Global interrupt pending register */
 
#define IPR_MIDI_RX_B   0x00020000 /* MIDI UART-B Receive buffer non-empty */
 
#define IPR_MIDI_TX_B   0x00010000 /* MIDI UART-B Transmit buffer empty */
 
#define IPR_SPDIF_IN_USER   0x00004000 /* SPDIF input user data has 16 more bits */
 
#define IPR_SPDIF_OUT_USER   0x00002000 /* SPDIF output user data needs 16 more bits */
 
#define IPR_SPDIF_OUT_FRAME   0x00001000 /* SPDIF frame about to start */
 
#define IPR_SPI   0x00000800 /* SPI transaction completed */
 
#define IPR_I2C_EEPROM   0x00000400 /* I2C EEPROM transaction completed */
 
#define IPR_I2C_DAC   0x00000200 /* I2C DAC transaction completed */
 
#define IPR_AI   0x00000100 /* Audio pending register changed. See PTR reg 0x76 */
 
#define IPR_GPI   0x00000080 /* General Purpose input changed */
 
#define IPR_SRC_LOCKED   0x00000040 /* SRC lock status changed */
 
#define IPR_SPDIF_STATUS   0x00000020 /* SPDIF status changed */
 
#define IPR_TIMER2   0x00000010 /* 192000Hz Timer */
 
#define IPR_TIMER1   0x00000008 /* 44100Hz Timer */
 
#define IPR_MIDI_RX_A   0x00000004 /* MIDI UART-A Receive buffer non-empty */
 
#define IPR_MIDI_TX_A   0x00000002 /* MIDI UART-A Transmit buffer empty */
 
#define IPR_PCI   0x00000001 /* PCI Bus error */
 
#define INTE   0x0c /* Interrupt enable register */
 
#define INTE_MIDI_RX_B   0x00020000 /* MIDI UART-B Receive buffer non-empty */
 
#define INTE_MIDI_TX_B   0x00010000 /* MIDI UART-B Transmit buffer empty */
 
#define INTE_SPDIF_IN_USER   0x00004000 /* SPDIF input user data has 16 more bits */
 
#define INTE_SPDIF_OUT_USER   0x00002000 /* SPDIF output user data needs 16 more bits */
 
#define INTE_SPDIF_OUT_FRAME   0x00001000 /* SPDIF frame about to start */
 
#define INTE_SPI   0x00000800 /* SPI transaction completed */
 
#define INTE_I2C_EEPROM   0x00000400 /* I2C EEPROM transaction completed */
 
#define INTE_I2C_DAC   0x00000200 /* I2C DAC transaction completed */
 
#define INTE_AI   0x00000100 /* Audio pending register changed. See PTR reg 0x75 */
 
#define INTE_GPI   0x00000080 /* General Purpose input changed */
 
#define INTE_SRC_LOCKED   0x00000040 /* SRC lock status changed */
 
#define INTE_SPDIF_STATUS   0x00000020 /* SPDIF status changed */
 
#define INTE_TIMER2   0x00000010 /* 192000Hz Timer */
 
#define INTE_TIMER1   0x00000008 /* 44100Hz Timer */
 
#define INTE_MIDI_RX_A   0x00000004 /* MIDI UART-A Receive buffer non-empty */
 
#define INTE_MIDI_TX_A   0x00000002 /* MIDI UART-A Transmit buffer empty */
 
#define INTE_PCI   0x00000001 /* PCI Bus error */
 
#define UNKNOWN10   0x10 /* Unknown ??. Defaults to 0 */
 
#define HCFG   0x14 /* Hardware config register */
 
#define HCFG_STAC   0x10000000 /* Special mode for STAC9460 Codec. */
 
#define HCFG_CAPTURE_I2S_BYPASS   0x08000000 /* 1 = bypass I2S input async SRC. */
 
#define HCFG_CAPTURE_SPDIF_BYPASS   0x04000000 /* 1 = bypass SPDIF input async SRC. */
 
#define HCFG_PLAYBACK_I2S_BYPASS   0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
 
#define HCFG_FORCE_LOCK   0x01000000 /* For test only. Force input SRC tracker to lock. */
 
#define HCFG_PLAYBACK_ATTENUATION   0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12dB, 3 = Mute. */
 
#define HCFG_PLAYBACK_DITHER   0x00001000 /* 1 = Add dither bit to all playback channels. */
 
#define HCFG_PLAYBACK_S32_LE   0x00000800 /* 1 = S32_LE, 0 = S16_LE */
 
#define HCFG_CAPTURE_S32_LE   0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
 
#define HCFG_8_CHANNEL_PLAY   0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
 
#define HCFG_8_CHANNEL_CAPTURE   0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/
 
#define HCFG_MONO   0x00000080 /* 1 = I2S Input mono */
 
#define HCFG_I2S_OUTPUT   0x00000010 /* 1 = I2S Output disabled */
 
#define HCFG_AC97   0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */
 
#define HCFG_LOCK_PLAYBACK_CACHE   0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */
 
#define HCFG_LOCK_CAPTURE_CACHE   0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */
 
#define HCFG_AUDIOENABLE   0x00000001 /* 0 = CODECs transmit zero-valued samples */
 
#define GPIO   0x18 /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF. */
 
#define AC97DATA   0x1c /* AC97 register set data register (16 bit) */
 
#define AC97ADDRESS   0x1e /* AC97 register set address register (8 bit) */
 
#define PLAYBACK_LIST_ADDR   0x00 /* Base DMA address of a list of pointers to each period/size */
 
#define PLAYBACK_LIST_SIZE   0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
 
#define PLAYBACK_LIST_PTR   0x02 /* Pointer to the current period being played */
 
#define PLAYBACK_UNKNOWN3   0x03 /* Not used ?? */
 
#define PLAYBACK_DMA_ADDR   0x04 /* Playback DMA address */
 
#define PLAYBACK_PERIOD_SIZE   0x05 /* Playback period size. win2000 uses 0x04000000 */
 
#define PLAYBACK_POINTER   0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */
 
#define PLAYBACK_PERIOD_END_ADDR   0x07 /* Playback fifo end address */
 
#define PLAYBACK_FIFO_OFFSET_ADDRESS   0x08 /* Current fifo offset address [21:16] */
 
#define PLAYBACK_UNKNOWN9   0x09 /* 0x9 to 0xf Unused */
 
#define CAPTURE_DMA_ADDR   0x10 /* Capture DMA address */
 
#define CAPTURE_BUFFER_SIZE   0x11 /* Capture buffer size */
 
#define CAPTURE_POINTER   0x12 /* Capture buffer pointer. Sample currently in ADC */
 
#define CAPTURE_FIFO_OFFSET_ADDRESS   0x13 /* Current fifo offset address [21:16] */
 
#define PLAYBACK_LAST_SAMPLE   0x20 /* The sample currently being played */
 
#define BASIC_INTERRUPT   0x40 /* Used by both playback and capture interrupt handler */
 
#define SPCS0   0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006 */
 
#define SPCS1   0x42 /* SPDIF output Channel Status 1 register. For Front */
 
#define SPCS2   0x43 /* SPDIF output Channel Status 2 register. For Center/LFE */
 
#define SPCS3   0x44 /* SPDIF output Channel Status 3 register. Unknown */
 
#define SPCS_CLKACCYMASK   0x30000000 /* Clock accuracy */
 
#define SPCS_CLKACCY_1000PPM   0x00000000 /* 1000 parts per million */
 
#define SPCS_CLKACCY_50PPM   0x10000000 /* 50 parts per million */
 
#define SPCS_CLKACCY_VARIABLE   0x20000000 /* Variable accuracy */
 
#define SPCS_SAMPLERATEMASK   0x0f000000 /* Sample rate */
 
#define SPCS_SAMPLERATE_44   0x00000000 /* 44.1kHz sample rate */
 
#define SPCS_SAMPLERATE_48   0x02000000 /* 48kHz sample rate */
 
#define SPCS_SAMPLERATE_32   0x03000000 /* 32kHz sample rate */
 
#define SPCS_CHANNELNUMMASK   0x00f00000 /* Channel number */
 
#define SPCS_CHANNELNUM_UNSPEC   0x00000000 /* Unspecified channel number */
 
#define SPCS_CHANNELNUM_LEFT   0x00100000 /* Left channel */
 
#define SPCS_CHANNELNUM_RIGHT   0x00200000 /* Right channel */
 
#define SPCS_SOURCENUMMASK   0x000f0000 /* Source number */
 
#define SPCS_SOURCENUM_UNSPEC   0x00000000 /* Unspecified source number */
 
#define SPCS_GENERATIONSTATUS   0x00008000 /* Originality flag (see IEC-958 spec) */
 
#define SPCS_CATEGORYCODEMASK   0x00007f00 /* Category code (see IEC-958 spec) */
 
#define SPCS_MODEMASK   0x000000c0 /* Mode (see IEC-958 spec) */
 
#define SPCS_EMPHASISMASK   0x00000038 /* Emphasis */
 
#define SPCS_EMPHASIS_NONE   0x00000000 /* No emphasis */
 
#define SPCS_EMPHASIS_50_15   0x00000008 /* 50/15 usec 2 channel */
 
#define SPCS_COPYRIGHT   0x00000004 /* Copyright asserted flag -- do not modify */
 
#define SPCS_NOTAUDIODATA   0x00000002 /* 0 = Digital audio, 1 = not audio */
 
#define SPCS_PROFESSIONAL   0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
 
#define SPCS_WORD_LENGTH_MASK   0x0000000f /* Word Length Mask */
 
#define SPCS_WORD_LENGTH_16   0x00000008 /* Word Length 16 bit */
 
#define SPCS_WORD_LENGTH_17   0x00000006 /* Word Length 17 bit */
 
#define SPCS_WORD_LENGTH_18   0x00000004 /* Word Length 18 bit */
 
#define SPCS_WORD_LENGTH_19   0x00000002 /* Word Length 19 bit */
 
#define SPCS_WORD_LENGTH_20A   0x0000000a /* Word Length 20 bit */
 
#define SPCS_WORD_LENGTH_20   0x00000009 /* Word Length 20 bit (both 0xa and 0x9 are 20 bit) */
 
#define SPCS_WORD_LENGTH_21   0x00000007 /* Word Length 21 bit */
 
#define SPCS_WORD_LENGTH_22   0x00000005 /* Word Length 22 bit */
 
#define SPCS_WORD_LENGTH_23   0x00000003 /* Word Length 23 bit */
 
#define SPCS_WORD_LENGTH_24   0x0000000b /* Word Length 24 bit */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_MASK   0x000000f0 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_NONE   0x00000000 /* Original Sample rate not indicated */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_16000   0x00000010 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_RES1   0x00000020 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_32000   0x00000030 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_12000   0x00000040 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_11025   0x00000050 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_8000   0x00000060 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_RES2   0x00000070 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_192000   0x00000080 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_24000   0x00000090 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_96000   0x000000a0 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_48000   0x000000b0 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_176400   0x000000c0 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_22050   0x000000d0 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_88200   0x000000e0 /* Original Sample rate */
 
#define SPCS_ORIGINAL_SAMPLE_RATE_44100   0x000000f0 /* Original Sample rate */
 
#define SPDIF_SELECT1   0x45 /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */
 
#define WATERMARK   0x46 /* Test bit to indicate cache usage level */
 
#define SPDIF_INPUT_STATUS
 
#define CAPTURE_CACHE_DATA   0x50 /* 0x50-0x5f Recorded samples. */
 
#define CAPTURE_SOURCE   0x60 /* Capture Source 0 = MIC */
 
#define CAPTURE_SOURCE_CHANNEL0   0xf0000000 /* Mask for selecting the Capture sources */
 
#define CAPTURE_SOURCE_CHANNEL1   0x0f000000 /* 0 - SPDIF mixer output. */
 
#define CAPTURE_SOURCE_CHANNEL2   0x00f00000 /* 1 - What you hear or . 2 - ?? */
 
#define CAPTURE_SOURCE_CHANNEL3   0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */
 
#define CAPTURE_SOURCE_RECORD_MAP   0x0000ffff /* Default 0x00e4 */
 
#define CAPTURE_VOLUME1   0x61 /* Capture volume per channel 0-3 */
 
#define CAPTURE_VOLUME2   0x62 /* Capture volume per channel 4-7 */
 
#define PLAYBACK_ROUTING1   0x63 /* Playback routing of channels 0-7. Effects AC3 output. Default 0x32765410 */
 
#define ROUTING1_REAR   0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */
 
#define ROUTING1_NULL   0x00770000 /* Channel_id 2 sends to 54, Channel_id 3 sends to 76 */
 
#define ROUTING1_CENTER_LFE   0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */
 
#define ROUTING1_FRONT   0x00000077 /* Channel_id 2 to CENTER_LFE, Channel_id 3 to NULL. */
 
#define PLAYBACK_ROUTING2   0x64 /* Playback Routing . Feeding Capture channels back into Playback. Effects AC3 output. Default 0x76767676 */
 
#define PLAYBACK_MUTE   0x65 /* Unknown. While playing 0x0, while silent 0x00fc0000 */
 
#define PLAYBACK_VOLUME1   0x66 /* Playback SPDIF volume per channel. Set to the same PLAYBACK_VOLUME(0x6a) */
 
#define CAPTURE_ROUTING1   0x67 /* Capture Routing. Default 0x32765410 */
 
#define CAPTURE_ROUTING2   0x68 /* Unknown Routing. Default 0x76767676 */
 
#define CAPTURE_MUTE   0x69 /* Unknown. While capturing 0x0, while silent 0x00fc0000 */
 
#define PLAYBACK_VOLUME2   0x6a /* Playback Analog volume per channel. Does not effect AC3 output */
 
#define UNKNOWN6b   0x6b /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */
 
#define MIDI_UART_A_DATA   0x6c /* Midi Uart A Data */
 
#define MIDI_UART_A_CMD   0x6d /* Midi Uart A Command/Status */
 
#define MIDI_UART_B_DATA   0x6e /* Midi Uart B Data (currently unused) */
 
#define MIDI_UART_B_CMD   0x6f /* Midi Uart B Command/Status (currently unused) */
 
#define CA0106_MIDI_CHAN_A   0x1
 
#define CA0106_MIDI_CHAN_B   0x2
 
#define CA0106_MIDI_INPUT_AVAIL   0x80
 
#define CA0106_MIDI_OUTPUT_READY   0x40
 
#define CA0106_MPU401_RESET   0xff
 
#define CA0106_MPU401_ENTER_UART   0x3f
 
#define CA0106_MPU401_ACK   0xfe
 
#define SAMPLE_RATE_TRACKER_STATUS   0x70 /* Readonly. Default 00108000 00108000 00500000 00500000 */
 
#define CAPTURE_CONTROL   0x71 /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */
 
#define SPDIF_SELECT2   0x72 /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */
 
#define ROUTING2_FRONT_MASK   0x00010000 /* Enable for Front speakers. */
 
#define ROUTING2_CENTER_LFE_MASK   0x00020000 /* Enable for Center/LFE speakers. */
 
#define ROUTING2_REAR_MASK   0x00080000 /* Enable for Rear speakers. */
 
#define UNKNOWN73   0x73 /* Unknown. Readonly. Default 0x0 */
 
#define CHIP_VERSION   0x74 /* P17 Chip version. Channel_id 0 only. Default 00000071 */
 
#define EXTENDED_INT_MASK   0x75 /* Used by both playback and capture interrupt handler */
 
#define EXTENDED_INT   0x76 /* Used by both playback and capture interrupt handler */
 
#define COUNTER77   0x77 /* Counter range 0 to 0x3fffff, 192000 counts per second. */
 
#define COUNTER78   0x78 /* Counter range 0 to 0x3fffff, 44100 counts per second. */
 
#define EXTENDED_INT_TIMER   0x79 /* Channel_id 0 only. Used by both playback and capture interrupt handler */
 
#define SPI   0x7a /* SPI: Serial Interface Register */
 
#define I2C_A   0x7b /* I2C Address. 32 bit */
 
#define I2C_D0   0x7c /* I2C Data Port 0. 32 bit */
 
#define I2C_D1   0x7d /* I2C Data Port 1. 32 bit */
 
#define I2C_A_ADC_ADD_MASK   0x000000fe
 
#define I2C_A_ADC_RW_MASK   0x00000001
 
#define I2C_A_ADC_TRANS_MASK   0x00000010
 
#define I2C_A_ADC_ABORT_MASK   0x00000020
 
#define I2C_A_ADC_LAST_MASK   0x00000040
 
#define I2C_A_ADC_BYTE_MASK   0x00000080
 
#define I2C_A_ADC_ADD   0x00000034
 
#define I2C_A_ADC_READ   0x00000001
 
#define I2C_A_ADC_START   0x00000100
 
#define I2C_A_ADC_ABORT   0x00000200
 
#define I2C_A_ADC_LAST   0x00000400
 
#define I2C_A_ADC_BYTE   0x00000800
 
#define I2C_D_ADC_REG_MASK   0xfe000000
 
#define I2C_D_ADC_DAT_MASK   0x01ff0000
 
#define ADC_TIMEOUT   0x00000007
 
#define ADC_IFC_CTRL   0x0000000b
 
#define ADC_MASTER   0x0000000c
 
#define ADC_POWER   0x0000000d
 
#define ADC_ATTEN_ADCL   0x0000000e
 
#define ADC_ATTEN_ADCR   0x0000000f
 
#define ADC_ALC_CTRL1   0x00000010
 
#define ADC_ALC_CTRL2   0x00000011
 
#define ADC_ALC_CTRL3   0x00000012
 
#define ADC_NOISE_CTRL   0x00000013
 
#define ADC_LIMIT_CTRL   0x00000014
 
#define ADC_MUX   0x00000015
 
#define ADC_MUX_MASK   0x0000000f
 
#define ADC_MUX_PHONE   0x00000001
 
#define ADC_MUX_MIC   0x00000002
 
#define ADC_MUX_LINEIN   0x00000004
 
#define ADC_MUX_AUX   0x00000008
 
#define SET_CHANNEL   0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
 
#define PCM_FRONT_CHANNEL   0
 
#define PCM_REAR_CHANNEL   1
 
#define PCM_CENTER_LFE_CHANNEL   2
 
#define PCM_UNKNOWN_CHANNEL   3
 
#define CONTROL_FRONT_CHANNEL   0
 
#define CONTROL_REAR_CHANNEL   3
 
#define CONTROL_CENTER_LFE_CHANNEL   1
 
#define CONTROL_UNKNOWN_CHANNEL   2
 
#define SPI_REG_MASK   0x1ff /* 16-bit SPI writes have a 7-bit address */
 
#define SPI_REG_SHIFT   9 /* followed by 9 bits of data */
 
#define SPI_LDA1_REG   0 /* digital attenuation */
 
#define SPI_RDA1_REG   1
 
#define SPI_LDA2_REG   4
 
#define SPI_RDA2_REG   5
 
#define SPI_LDA3_REG   6
 
#define SPI_RDA3_REG   7
 
#define SPI_LDA4_REG   13
 
#define SPI_RDA4_REG   14
 
#define SPI_MASTDA_REG   8
 
#define SPI_DA_BIT_UPDATE   (1<<8) /* update attenuation values */
 
#define SPI_DA_BIT_0dB   0xff /* 0 dB */
 
#define SPI_DA_BIT_infdB   0x00 /* inf dB attenuation (mute) */
 
#define SPI_PL_REG   2
 
#define SPI_PL_BIT_L_M   (0<<5) /* left channel = mute */
 
#define SPI_PL_BIT_L_L   (1<<5) /* left channel = left */
 
#define SPI_PL_BIT_L_R   (2<<5) /* left channel = right */
 
#define SPI_PL_BIT_L_C   (3<<5) /* left channel = (L+R)/2 */
 
#define SPI_PL_BIT_R_M   (0<<7) /* right channel = mute */
 
#define SPI_PL_BIT_R_L   (1<<7) /* right channel = left */
 
#define SPI_PL_BIT_R_R   (2<<7) /* right channel = right */
 
#define SPI_PL_BIT_R_C   (3<<7) /* right channel = (L+R)/2 */
 
#define SPI_IZD_REG   2
 
#define SPI_IZD_BIT   (1<<4) /* infinite zero detect */
 
#define SPI_FMT_REG   3
 
#define SPI_FMT_BIT_RJ   (0<<0) /* right justified mode */
 
#define SPI_FMT_BIT_LJ   (1<<0) /* left justified mode */
 
#define SPI_FMT_BIT_I2S   (2<<0) /* I2S mode */
 
#define SPI_FMT_BIT_DSP   (3<<0) /* DSP Modes A or B */
 
#define SPI_LRP_REG   3
 
#define SPI_LRP_BIT   (1<<2) /* invert LRCLK polarity */
 
#define SPI_BCP_REG   3
 
#define SPI_BCP_BIT   (1<<3) /* invert BCLK polarity */
 
#define SPI_IWL_REG   3
 
#define SPI_IWL_BIT_16   (0<<4) /* 16-bit world length */
 
#define SPI_IWL_BIT_20   (1<<4) /* 20-bit world length */
 
#define SPI_IWL_BIT_24   (2<<4) /* 24-bit world length */
 
#define SPI_IWL_BIT_32   (3<<4) /* 32-bit world length */
 
#define SPI_MS_REG   10
 
#define SPI_MS_BIT   (1<<5) /* master mode */
 
#define SPI_RATE_REG   10 /* only applies in master mode */
 
#define SPI_RATE_BIT_128   (0<<6) /* MCLK = LRCLK * 128 */
 
#define SPI_RATE_BIT_192   (1<<6)
 
#define SPI_RATE_BIT_256   (2<<6)
 
#define SPI_RATE_BIT_384   (3<<6)
 
#define SPI_RATE_BIT_512   (4<<6)
 
#define SPI_RATE_BIT_768   (5<<6)
 
#define SPI_DMUTE0_REG   9
 
#define SPI_DMUTE1_REG   9
 
#define SPI_DMUTE2_REG   9
 
#define SPI_DMUTE4_REG   15
 
#define SPI_DMUTE0_BIT   (1<<3)
 
#define SPI_DMUTE1_BIT   (1<<4)
 
#define SPI_DMUTE2_BIT   (1<<5)
 
#define SPI_DMUTE4_BIT   (1<<2)
 
#define SPI_PHASE0_REG   3
 
#define SPI_PHASE1_REG   3
 
#define SPI_PHASE2_REG   3
 
#define SPI_PHASE4_REG   15
 
#define SPI_PHASE0_BIT   (1<<6)
 
#define SPI_PHASE1_BIT   (1<<7)
 
#define SPI_PHASE2_BIT   (1<<8)
 
#define SPI_PHASE4_BIT   (1<<3)
 
#define SPI_PDWN_REG   2 /* power down all DACs */
 
#define SPI_PDWN_BIT   (1<<2)
 
#define SPI_DACD0_REG   10 /* power down individual DACs */
 
#define SPI_DACD1_REG   10
 
#define SPI_DACD2_REG   10
 
#define SPI_DACD4_REG   15
 
#define SPI_DACD0_BIT   (1<<1)
 
#define SPI_DACD1_BIT   (1<<2)
 
#define SPI_DACD2_BIT   (1<<3)
 
#define SPI_DACD4_BIT   (1<<0) /* datasheet error says it's 1 */
 
#define SPI_PWRDNALL_REG   10 /* power down everything */
 
#define SPI_PWRDNALL_BIT   (1<<4)
 
#define snd_ca0106_mixer_suspend(chip)   do { } while (0)
 
#define snd_ca0106_mixer_resume(chip)   do { } while (0)
 

Functions

int snd_ca0106_mixer (struct snd_ca0106 *emu)
 
int snd_ca0106_proc_init (struct snd_ca0106 *emu)
 
unsigned int snd_ca0106_ptr_read (struct snd_ca0106 *emu, unsigned int reg, unsigned int chn)
 
void snd_ca0106_ptr_write (struct snd_ca0106 *emu, unsigned int reg, unsigned int chn, unsigned int data)
 
int snd_ca0106_i2c_write (struct snd_ca0106 *emu, u32 reg, u32 value)
 
int snd_ca0106_spi_write (struct snd_ca0106 *emu, unsigned int data)
 

Macro Definition Documentation

#define AC97ADDRESS   0x1e /* AC97 register set address register (8 bit) */

Definition at line 172 of file ca0106.h.

#define AC97DATA   0x1c /* AC97 register set data register (16 bit) */

Definition at line 170 of file ca0106.h.

#define ADC_ALC_CTRL1   0x00000010

Definition at line 515 of file ca0106.h.

#define ADC_ALC_CTRL2   0x00000011

Definition at line 516 of file ca0106.h.

#define ADC_ALC_CTRL3   0x00000012

Definition at line 517 of file ca0106.h.

#define ADC_ATTEN_ADCL   0x0000000e

Definition at line 513 of file ca0106.h.

#define ADC_ATTEN_ADCR   0x0000000f

Definition at line 514 of file ca0106.h.

#define ADC_IFC_CTRL   0x0000000b

Definition at line 510 of file ca0106.h.

#define ADC_LIMIT_CTRL   0x00000014

Definition at line 519 of file ca0106.h.

#define ADC_MASTER   0x0000000c

Definition at line 511 of file ca0106.h.

#define ADC_MUX   0x00000015

Definition at line 520 of file ca0106.h.

#define ADC_MUX_AUX   0x00000008

Definition at line 538 of file ca0106.h.

#define ADC_MUX_LINEIN   0x00000004

Definition at line 537 of file ca0106.h.

#define ADC_MUX_MASK   0x0000000f

Definition at line 534 of file ca0106.h.

#define ADC_MUX_MIC   0x00000002

Definition at line 536 of file ca0106.h.

#define ADC_MUX_PHONE   0x00000001

Definition at line 535 of file ca0106.h.

#define ADC_NOISE_CTRL   0x00000013

Definition at line 518 of file ca0106.h.

#define ADC_POWER   0x0000000d

Definition at line 512 of file ca0106.h.

#define ADC_TIMEOUT   0x00000007

Definition at line 509 of file ca0106.h.

#define BASIC_INTERRUPT   0x40 /* Used by both playback and capture interrupt handler */

Definition at line 212 of file ca0106.h.

#define CA0106_MIDI_CHAN_A   0x1

Definition at line 404 of file ca0106.h.

#define CA0106_MIDI_CHAN_B   0x2

Definition at line 405 of file ca0106.h.

#define CA0106_MIDI_INPUT_AVAIL   0x80

Definition at line 409 of file ca0106.h.

#define CA0106_MIDI_OUTPUT_READY   0x40

Definition at line 410 of file ca0106.h.

#define CA0106_MPU401_ACK   0xfe

Definition at line 413 of file ca0106.h.

#define CA0106_MPU401_ENTER_UART   0x3f

Definition at line 412 of file ca0106.h.

#define CA0106_MPU401_RESET   0xff

Definition at line 411 of file ca0106.h.

#define CAPTURE_BUFFER_SIZE   0x11 /* Capture buffer size */

Definition at line 204 of file ca0106.h.

#define CAPTURE_CACHE_DATA   0x50 /* 0x50-0x5f Recorded samples. */

Definition at line 321 of file ca0106.h.

#define CAPTURE_CONTROL   0x71 /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */

Definition at line 421 of file ca0106.h.

#define CAPTURE_DMA_ADDR   0x10 /* Capture DMA address */

Definition at line 202 of file ca0106.h.

#define CAPTURE_FIFO_OFFSET_ADDRESS   0x13 /* Current fifo offset address [21:16] */

Definition at line 208 of file ca0106.h.

#define CAPTURE_MUTE   0x69 /* Unknown. While capturing 0x0, while silent 0x00fc0000 */

Definition at line 392 of file ca0106.h.

#define CAPTURE_POINTER   0x12 /* Capture buffer pointer. Sample currently in ADC */

Definition at line 206 of file ca0106.h.

#define CAPTURE_ROUTING1   0x67 /* Capture Routing. Default 0x32765410 */

Definition at line 388 of file ca0106.h.

#define CAPTURE_ROUTING2   0x68 /* Unknown Routing. Default 0x76767676 */

Definition at line 390 of file ca0106.h.

#define CAPTURE_SOURCE   0x60 /* Capture Source 0 = MIC */

Definition at line 322 of file ca0106.h.

#define CAPTURE_SOURCE_CHANNEL0   0xf0000000 /* Mask for selecting the Capture sources */

Definition at line 323 of file ca0106.h.

#define CAPTURE_SOURCE_CHANNEL1   0x0f000000 /* 0 - SPDIF mixer output. */

Definition at line 324 of file ca0106.h.

#define CAPTURE_SOURCE_CHANNEL2   0x00f00000 /* 1 - What you hear or . 2 - ?? */

Definition at line 325 of file ca0106.h.

#define CAPTURE_SOURCE_CHANNEL3   0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */

Definition at line 326 of file ca0106.h.

#define CAPTURE_SOURCE_RECORD_MAP   0x0000ffff /* Default 0x00e4 */

Definition at line 327 of file ca0106.h.

#define CAPTURE_VOLUME1   0x61 /* Capture volume per channel 0-3 */

Definition at line 340 of file ca0106.h.

#define CAPTURE_VOLUME2   0x62 /* Capture volume per channel 4-7 */

Definition at line 341 of file ca0106.h.

#define CHIP_VERSION   0x74 /* P17 Chip version. Channel_id 0 only. Default 00000071 */

Definition at line 466 of file ca0106.h.

#define CONTROL_CENTER_LFE_CHANNEL   1

Definition at line 547 of file ca0106.h.

#define CONTROL_FRONT_CHANNEL   0

Definition at line 545 of file ca0106.h.

#define CONTROL_REAR_CHANNEL   3

Definition at line 546 of file ca0106.h.

#define CONTROL_UNKNOWN_CHANNEL   2

Definition at line 548 of file ca0106.h.

#define COUNTER77   0x77 /* Counter range 0 to 0x3fffff, 192000 counts per second. */

Definition at line 483 of file ca0106.h.

#define COUNTER78   0x78 /* Counter range 0 to 0x3fffff, 44100 counts per second. */

Definition at line 484 of file ca0106.h.

#define DATA   0x04 /* Indexed register set data register */

Definition at line 82 of file ca0106.h.

#define EXTENDED_INT   0x76 /* Used by both playback and capture interrupt handler */

Definition at line 480 of file ca0106.h.

#define EXTENDED_INT_MASK   0x75 /* Used by both playback and capture interrupt handler */

Definition at line 467 of file ca0106.h.

#define EXTENDED_INT_TIMER   0x79 /* Channel_id 0 only. Used by both playback and capture interrupt handler */

Definition at line 485 of file ca0106.h.

#define GPIO   0x18 /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF. */

Definition at line 151 of file ca0106.h.

#define HCFG   0x14 /* Hardware config register */

Definition at line 127 of file ca0106.h.

#define HCFG_8_CHANNEL_CAPTURE   0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/

Definition at line 140 of file ca0106.h.

#define HCFG_8_CHANNEL_PLAY   0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/

Definition at line 139 of file ca0106.h.

#define HCFG_AC97   0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */

Definition at line 143 of file ca0106.h.

#define HCFG_AUDIOENABLE   0x00000001 /* 0 = CODECs transmit zero-valued samples */

Definition at line 148 of file ca0106.h.

#define HCFG_CAPTURE_I2S_BYPASS   0x08000000 /* 1 = bypass I2S input async SRC. */

Definition at line 131 of file ca0106.h.

#define HCFG_CAPTURE_S32_LE   0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */

Definition at line 138 of file ca0106.h.

#define HCFG_CAPTURE_SPDIF_BYPASS   0x04000000 /* 1 = bypass SPDIF input async SRC. */

Definition at line 132 of file ca0106.h.

#define HCFG_FORCE_LOCK   0x01000000 /* For test only. Force input SRC tracker to lock. */

Definition at line 134 of file ca0106.h.

#define HCFG_I2S_OUTPUT   0x00000010 /* 1 = I2S Output disabled */

Definition at line 142 of file ca0106.h.

#define HCFG_LOCK_CAPTURE_CACHE   0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */

Definition at line 146 of file ca0106.h.

#define HCFG_LOCK_PLAYBACK_CACHE   0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */

Definition at line 144 of file ca0106.h.

#define HCFG_MONO   0x00000080 /* 1 = I2S Input mono */

Definition at line 141 of file ca0106.h.

#define HCFG_PLAYBACK_ATTENUATION   0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12dB, 3 = Mute. */

Definition at line 135 of file ca0106.h.

#define HCFG_PLAYBACK_DITHER   0x00001000 /* 1 = Add dither bit to all playback channels. */

Definition at line 136 of file ca0106.h.

#define HCFG_PLAYBACK_I2S_BYPASS   0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */

Definition at line 133 of file ca0106.h.

#define HCFG_PLAYBACK_S32_LE   0x00000800 /* 1 = S32_LE, 0 = S16_LE */

Definition at line 137 of file ca0106.h.

#define HCFG_STAC   0x10000000 /* Special mode for STAC9460 Codec. */

Definition at line 130 of file ca0106.h.

#define I2C_A   0x7b /* I2C Address. 32 bit */

Definition at line 488 of file ca0106.h.

#define I2C_A_ADC_ABORT   0x00000200

Definition at line 502 of file ca0106.h.

#define I2C_A_ADC_ABORT_MASK   0x00000020

Definition at line 495 of file ca0106.h.

#define I2C_A_ADC_ADD   0x00000034

Definition at line 499 of file ca0106.h.

#define I2C_A_ADC_ADD_MASK   0x000000fe

Definition at line 492 of file ca0106.h.

#define I2C_A_ADC_BYTE   0x00000800

Definition at line 504 of file ca0106.h.

#define I2C_A_ADC_BYTE_MASK   0x00000080

Definition at line 497 of file ca0106.h.

#define I2C_A_ADC_LAST   0x00000400

Definition at line 503 of file ca0106.h.

#define I2C_A_ADC_LAST_MASK   0x00000040

Definition at line 496 of file ca0106.h.

#define I2C_A_ADC_READ   0x00000001

Definition at line 500 of file ca0106.h.

#define I2C_A_ADC_RW_MASK   0x00000001

Definition at line 493 of file ca0106.h.

#define I2C_A_ADC_START   0x00000100

Definition at line 501 of file ca0106.h.

#define I2C_A_ADC_TRANS_MASK   0x00000010

Definition at line 494 of file ca0106.h.

#define I2C_D0   0x7c /* I2C Data Port 0. 32 bit */

Definition at line 489 of file ca0106.h.

#define I2C_D1   0x7d /* I2C Data Port 1. 32 bit */

Definition at line 490 of file ca0106.h.

#define I2C_D_ADC_DAT_MASK   0x01ff0000

Definition at line 507 of file ca0106.h.

#define I2C_D_ADC_REG_MASK   0xfe000000

Definition at line 506 of file ca0106.h.

#define INTE   0x0c /* Interrupt enable register */

Definition at line 106 of file ca0106.h.

#define INTE_AI   0x00000100 /* Audio pending register changed. See PTR reg 0x75 */

Definition at line 116 of file ca0106.h.

#define INTE_GPI   0x00000080 /* General Purpose input changed */

Definition at line 117 of file ca0106.h.

#define INTE_I2C_DAC   0x00000200 /* I2C DAC transaction completed */

Definition at line 115 of file ca0106.h.

#define INTE_I2C_EEPROM   0x00000400 /* I2C EEPROM transaction completed */

Definition at line 114 of file ca0106.h.

#define INTE_MIDI_RX_A   0x00000004 /* MIDI UART-A Receive buffer non-empty */

Definition at line 122 of file ca0106.h.

#define INTE_MIDI_RX_B   0x00020000 /* MIDI UART-B Receive buffer non-empty */

Definition at line 108 of file ca0106.h.

#define INTE_MIDI_TX_A   0x00000002 /* MIDI UART-A Transmit buffer empty */

Definition at line 123 of file ca0106.h.

#define INTE_MIDI_TX_B   0x00010000 /* MIDI UART-B Transmit buffer empty */

Definition at line 109 of file ca0106.h.

#define INTE_PCI   0x00000001 /* PCI Bus error */

Definition at line 124 of file ca0106.h.

#define INTE_SPDIF_IN_USER   0x00004000 /* SPDIF input user data has 16 more bits */

Definition at line 110 of file ca0106.h.

#define INTE_SPDIF_OUT_FRAME   0x00001000 /* SPDIF frame about to start */

Definition at line 112 of file ca0106.h.

#define INTE_SPDIF_OUT_USER   0x00002000 /* SPDIF output user data needs 16 more bits */

Definition at line 111 of file ca0106.h.

#define INTE_SPDIF_STATUS   0x00000020 /* SPDIF status changed */

Definition at line 119 of file ca0106.h.

#define INTE_SPI   0x00000800 /* SPI transaction completed */

Definition at line 113 of file ca0106.h.

#define INTE_SRC_LOCKED   0x00000040 /* SRC lock status changed */

Definition at line 118 of file ca0106.h.

#define INTE_TIMER1   0x00000008 /* 44100Hz Timer */

Definition at line 121 of file ca0106.h.

#define INTE_TIMER2   0x00000010 /* 192000Hz Timer */

Definition at line 120 of file ca0106.h.

#define IPR   0x08 /* Global interrupt pending register */

Definition at line 85 of file ca0106.h.

#define IPR_AI   0x00000100 /* Audio pending register changed. See PTR reg 0x76 */

Definition at line 96 of file ca0106.h.

#define IPR_GPI   0x00000080 /* General Purpose input changed */

Definition at line 97 of file ca0106.h.

#define IPR_I2C_DAC   0x00000200 /* I2C DAC transaction completed */

Definition at line 95 of file ca0106.h.

#define IPR_I2C_EEPROM   0x00000400 /* I2C EEPROM transaction completed */

Definition at line 94 of file ca0106.h.

#define IPR_MIDI_RX_A   0x00000004 /* MIDI UART-A Receive buffer non-empty */

Definition at line 102 of file ca0106.h.

#define IPR_MIDI_RX_B   0x00020000 /* MIDI UART-B Receive buffer non-empty */

Definition at line 88 of file ca0106.h.

#define IPR_MIDI_TX_A   0x00000002 /* MIDI UART-A Transmit buffer empty */

Definition at line 103 of file ca0106.h.

#define IPR_MIDI_TX_B   0x00010000 /* MIDI UART-B Transmit buffer empty */

Definition at line 89 of file ca0106.h.

#define IPR_PCI   0x00000001 /* PCI Bus error */

Definition at line 104 of file ca0106.h.

#define IPR_SPDIF_IN_USER   0x00004000 /* SPDIF input user data has 16 more bits */

Definition at line 90 of file ca0106.h.

#define IPR_SPDIF_OUT_FRAME   0x00001000 /* SPDIF frame about to start */

Definition at line 92 of file ca0106.h.

#define IPR_SPDIF_OUT_USER   0x00002000 /* SPDIF output user data needs 16 more bits */

Definition at line 91 of file ca0106.h.

#define IPR_SPDIF_STATUS   0x00000020 /* SPDIF status changed */

Definition at line 99 of file ca0106.h.

#define IPR_SPI   0x00000800 /* SPI transaction completed */

Definition at line 93 of file ca0106.h.

#define IPR_SRC_LOCKED   0x00000040 /* SRC lock status changed */

Definition at line 98 of file ca0106.h.

#define IPR_TIMER1   0x00000008 /* 44100Hz Timer */

Definition at line 101 of file ca0106.h.

#define IPR_TIMER2   0x00000010 /* 192000Hz Timer */

Definition at line 100 of file ca0106.h.

#define MIDI_UART_A_CMD   0x6d /* Midi Uart A Command/Status */

Definition at line 398 of file ca0106.h.

#define MIDI_UART_A_DATA   0x6c /* Midi Uart A Data */

Definition at line 397 of file ca0106.h.

#define MIDI_UART_B_CMD   0x6f /* Midi Uart B Command/Status (currently unused) */

Definition at line 400 of file ca0106.h.

#define MIDI_UART_B_DATA   0x6e /* Midi Uart B Data (currently unused) */

Definition at line 399 of file ca0106.h.

#define PCM_CENTER_LFE_CHANNEL   2

Definition at line 543 of file ca0106.h.

#define PCM_FRONT_CHANNEL   0

Definition at line 541 of file ca0106.h.

#define PCM_REAR_CHANNEL   1

Definition at line 542 of file ca0106.h.

#define PCM_UNKNOWN_CHANNEL   3

Definition at line 544 of file ca0106.h.

#define PLAYBACK_DMA_ADDR   0x04 /* Playback DMA address */

Definition at line 191 of file ca0106.h.

#define PLAYBACK_FIFO_OFFSET_ADDRESS   0x08 /* Current fifo offset address [21:16] */

Definition at line 199 of file ca0106.h.

#define PLAYBACK_LAST_SAMPLE   0x20 /* The sample currently being played */

Definition at line 210 of file ca0106.h.

#define PLAYBACK_LIST_ADDR   0x00 /* Base DMA address of a list of pointers to each period/size */

Definition at line 179 of file ca0106.h.

#define PLAYBACK_LIST_PTR   0x02 /* Pointer to the current period being played */

Definition at line 188 of file ca0106.h.

#define PLAYBACK_LIST_SIZE   0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */

Definition at line 186 of file ca0106.h.

#define PLAYBACK_MUTE   0x65 /* Unknown. While playing 0x0, while silent 0x00fc0000 */

Definition at line 372 of file ca0106.h.

#define PLAYBACK_PERIOD_END_ADDR   0x07 /* Playback fifo end address */

Definition at line 197 of file ca0106.h.

#define PLAYBACK_PERIOD_SIZE   0x05 /* Playback period size. win2000 uses 0x04000000 */

Definition at line 193 of file ca0106.h.

#define PLAYBACK_POINTER   0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */

Definition at line 195 of file ca0106.h.

#define PLAYBACK_ROUTING1   0x63 /* Playback routing of channels 0-7. Effects AC3 output. Default 0x32765410 */

Definition at line 343 of file ca0106.h.

#define PLAYBACK_ROUTING2   0x64 /* Playback Routing . Feeding Capture channels back into Playback. Effects AC3 output. Default 0x76767676 */

Definition at line 360 of file ca0106.h.

#define PLAYBACK_UNKNOWN3   0x03 /* Not used ?? */

Definition at line 190 of file ca0106.h.

#define PLAYBACK_UNKNOWN9   0x09 /* 0x9 to 0xf Unused */

Definition at line 201 of file ca0106.h.

#define PLAYBACK_VOLUME1   0x66 /* Playback SPDIF volume per channel. Set to the same PLAYBACK_VOLUME(0x6a) */

Definition at line 379 of file ca0106.h.

#define PLAYBACK_VOLUME2   0x6a /* Playback Analog volume per channel. Does not effect AC3 output */

Definition at line 394 of file ca0106.h.

#define PTR   0x00 /* Indexed register set pointer register */

Definition at line 77 of file ca0106.h.

#define ROUTING1_CENTER_LFE   0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */

Definition at line 346 of file ca0106.h.

#define ROUTING1_FRONT   0x00000077 /* Channel_id 2 to CENTER_LFE, Channel_id 3 to NULL. */

Definition at line 347 of file ca0106.h.

#define ROUTING1_NULL   0x00770000 /* Channel_id 2 sends to 54, Channel_id 3 sends to 76 */

Definition at line 345 of file ca0106.h.

#define ROUTING1_REAR   0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */

Definition at line 344 of file ca0106.h.

#define ROUTING2_CENTER_LFE_MASK   0x00020000 /* Enable for Center/LFE speakers. */

Definition at line 458 of file ca0106.h.

#define ROUTING2_FRONT_MASK   0x00010000 /* Enable for Front speakers. */

Definition at line 457 of file ca0106.h.

#define ROUTING2_REAR_MASK   0x00080000 /* Enable for Rear speakers. */

Definition at line 459 of file ca0106.h.

#define SAMPLE_RATE_TRACKER_STATUS   0x70 /* Readonly. Default 00108000 00108000 00500000 00500000 */

Definition at line 415 of file ca0106.h.

#define SET_CHANNEL   0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */

Definition at line 540 of file ca0106.h.

#define snd_ca0106_mixer_resume (   chip)    do { } while (0)

Definition at line 741 of file ca0106.h.

#define snd_ca0106_mixer_suspend (   chip)    do { } while (0)

Definition at line 740 of file ca0106.h.

#define SPCS0   0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006 */

Definition at line 237 of file ca0106.h.

#define SPCS1   0x42 /* SPDIF output Channel Status 1 register. For Front */

Definition at line 238 of file ca0106.h.

#define SPCS2   0x43 /* SPDIF output Channel Status 2 register. For Center/LFE */

Definition at line 239 of file ca0106.h.

#define SPCS3   0x44 /* SPDIF output Channel Status 3 register. Unknown */

Definition at line 240 of file ca0106.h.

#define SPCS_CATEGORYCODEMASK   0x00007f00 /* Category code (see IEC-958 spec) */

Definition at line 257 of file ca0106.h.

#define SPCS_CHANNELNUM_LEFT   0x00100000 /* Left channel */

Definition at line 252 of file ca0106.h.

#define SPCS_CHANNELNUM_RIGHT   0x00200000 /* Right channel */

Definition at line 253 of file ca0106.h.

#define SPCS_CHANNELNUM_UNSPEC   0x00000000 /* Unspecified channel number */

Definition at line 251 of file ca0106.h.

#define SPCS_CHANNELNUMMASK   0x00f00000 /* Channel number */

Definition at line 250 of file ca0106.h.

#define SPCS_CLKACCY_1000PPM   0x00000000 /* 1000 parts per million */

Definition at line 243 of file ca0106.h.

#define SPCS_CLKACCY_50PPM   0x10000000 /* 50 parts per million */

Definition at line 244 of file ca0106.h.

#define SPCS_CLKACCY_VARIABLE   0x20000000 /* Variable accuracy */

Definition at line 245 of file ca0106.h.

#define SPCS_CLKACCYMASK   0x30000000 /* Clock accuracy */

Definition at line 242 of file ca0106.h.

#define SPCS_COPYRIGHT   0x00000004 /* Copyright asserted flag -- do not modify */

Definition at line 262 of file ca0106.h.

#define SPCS_EMPHASIS_50_15   0x00000008 /* 50/15 usec 2 channel */

Definition at line 261 of file ca0106.h.

#define SPCS_EMPHASIS_NONE   0x00000000 /* No emphasis */

Definition at line 260 of file ca0106.h.

#define SPCS_EMPHASISMASK   0x00000038 /* Emphasis */

Definition at line 259 of file ca0106.h.

#define SPCS_GENERATIONSTATUS   0x00008000 /* Originality flag (see IEC-958 spec) */

Definition at line 256 of file ca0106.h.

#define SPCS_MODEMASK   0x000000c0 /* Mode (see IEC-958 spec) */

Definition at line 258 of file ca0106.h.

#define SPCS_NOTAUDIODATA   0x00000002 /* 0 = Digital audio, 1 = not audio */

Definition at line 263 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_11025   0x00000050 /* Original Sample rate */

Definition at line 284 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_12000   0x00000040 /* Original Sample rate */

Definition at line 283 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_16000   0x00000010 /* Original Sample rate */

Definition at line 280 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_176400   0x000000c0 /* Original Sample rate */

Definition at line 291 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_192000   0x00000080 /* Original Sample rate */

Definition at line 287 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_22050   0x000000d0 /* Original Sample rate */

Definition at line 292 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_24000   0x00000090 /* Original Sample rate */

Definition at line 288 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_32000   0x00000030 /* Original Sample rate */

Definition at line 282 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_44100   0x000000f0 /* Original Sample rate */

Definition at line 294 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_48000   0x000000b0 /* Original Sample rate */

Definition at line 290 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_8000   0x00000060 /* Original Sample rate */

Definition at line 285 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_88200   0x000000e0 /* Original Sample rate */

Definition at line 293 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_96000   0x000000a0 /* Original Sample rate */

Definition at line 289 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_MASK   0x000000f0 /* Original Sample rate */

Definition at line 278 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_NONE   0x00000000 /* Original Sample rate not indicated */

Definition at line 279 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_RES1   0x00000020 /* Original Sample rate */

Definition at line 281 of file ca0106.h.

#define SPCS_ORIGINAL_SAMPLE_RATE_RES2   0x00000070 /* Original Sample rate */

Definition at line 286 of file ca0106.h.

#define SPCS_PROFESSIONAL   0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */

Definition at line 264 of file ca0106.h.

#define SPCS_SAMPLERATE_32   0x03000000 /* 32kHz sample rate */

Definition at line 249 of file ca0106.h.

#define SPCS_SAMPLERATE_44   0x00000000 /* 44.1kHz sample rate */

Definition at line 247 of file ca0106.h.

#define SPCS_SAMPLERATE_48   0x02000000 /* 48kHz sample rate */

Definition at line 248 of file ca0106.h.

#define SPCS_SAMPLERATEMASK   0x0f000000 /* Sample rate */

Definition at line 246 of file ca0106.h.

#define SPCS_SOURCENUM_UNSPEC   0x00000000 /* Unspecified source number */

Definition at line 255 of file ca0106.h.

#define SPCS_SOURCENUMMASK   0x000f0000 /* Source number */

Definition at line 254 of file ca0106.h.

#define SPCS_WORD_LENGTH_16   0x00000008 /* Word Length 16 bit */

Definition at line 268 of file ca0106.h.

#define SPCS_WORD_LENGTH_17   0x00000006 /* Word Length 17 bit */

Definition at line 269 of file ca0106.h.

#define SPCS_WORD_LENGTH_18   0x00000004 /* Word Length 18 bit */

Definition at line 270 of file ca0106.h.

#define SPCS_WORD_LENGTH_19   0x00000002 /* Word Length 19 bit */

Definition at line 271 of file ca0106.h.

#define SPCS_WORD_LENGTH_20   0x00000009 /* Word Length 20 bit (both 0xa and 0x9 are 20 bit) */

Definition at line 273 of file ca0106.h.

#define SPCS_WORD_LENGTH_20A   0x0000000a /* Word Length 20 bit */

Definition at line 272 of file ca0106.h.

#define SPCS_WORD_LENGTH_21   0x00000007 /* Word Length 21 bit */

Definition at line 274 of file ca0106.h.

#define SPCS_WORD_LENGTH_22   0x00000005 /* Word Length 22 bit */

Definition at line 275 of file ca0106.h.

#define SPCS_WORD_LENGTH_23   0x00000003 /* Word Length 23 bit */

Definition at line 276 of file ca0106.h.

#define SPCS_WORD_LENGTH_24   0x0000000b /* Word Length 24 bit */

Definition at line 277 of file ca0106.h.

#define SPCS_WORD_LENGTH_MASK   0x0000000f /* Word Length Mask */

Definition at line 267 of file ca0106.h.

#define SPDIF_INPUT_STATUS
Value:
0x49 /* SPDIF Input status register. Bits the same as SPCS.
* When Channel = 0: Bits the same as SPCS channel 0.
* When Channel = 1: Bits the same as SPCS channel 1.
* When Channel = 2:
* SPDIF Input User data [16:0]
* SPDIF Input Frame count [21:16]
*/

Definition at line 320 of file ca0106.h.

#define SPDIF_SELECT1   0x45 /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */

Definition at line 296 of file ca0106.h.

#define SPDIF_SELECT2   0x72 /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */

Definition at line 456 of file ca0106.h.

#define SPI   0x7a /* SPI: Serial Interface Register */

Definition at line 487 of file ca0106.h.

#define SPI_BCP_BIT   (1<<3) /* invert BCLK polarity */

Definition at line 589 of file ca0106.h.

#define SPI_BCP_REG   3

Definition at line 588 of file ca0106.h.

#define SPI_DA_BIT_0dB   0xff /* 0 dB */

Definition at line 566 of file ca0106.h.

#define SPI_DA_BIT_infdB   0x00 /* inf dB attenuation (mute) */

Definition at line 567 of file ca0106.h.

#define SPI_DA_BIT_UPDATE   (1<<8) /* update attenuation values */

Definition at line 565 of file ca0106.h.

#define SPI_DACD0_BIT   (1<<1)

Definition at line 631 of file ca0106.h.

#define SPI_DACD0_REG   10 /* power down individual DACs */

Definition at line 627 of file ca0106.h.

#define SPI_DACD1_BIT   (1<<2)

Definition at line 632 of file ca0106.h.

#define SPI_DACD1_REG   10

Definition at line 628 of file ca0106.h.

#define SPI_DACD2_BIT   (1<<3)

Definition at line 633 of file ca0106.h.

#define SPI_DACD2_REG   10

Definition at line 629 of file ca0106.h.

#define SPI_DACD4_BIT   (1<<0) /* datasheet error says it's 1 */

Definition at line 634 of file ca0106.h.

#define SPI_DACD4_REG   15

Definition at line 630 of file ca0106.h.

#define SPI_DMUTE0_BIT   (1<<3)

Definition at line 611 of file ca0106.h.

#define SPI_DMUTE0_REG   9

Definition at line 607 of file ca0106.h.

#define SPI_DMUTE1_BIT   (1<<4)

Definition at line 612 of file ca0106.h.

#define SPI_DMUTE1_REG   9

Definition at line 608 of file ca0106.h.

#define SPI_DMUTE2_BIT   (1<<5)

Definition at line 613 of file ca0106.h.

#define SPI_DMUTE2_REG   9

Definition at line 609 of file ca0106.h.

#define SPI_DMUTE4_BIT   (1<<2)

Definition at line 614 of file ca0106.h.

#define SPI_DMUTE4_REG   15

Definition at line 610 of file ca0106.h.

#define SPI_FMT_BIT_DSP   (3<<0) /* DSP Modes A or B */

Definition at line 585 of file ca0106.h.

#define SPI_FMT_BIT_I2S   (2<<0) /* I2S mode */

Definition at line 584 of file ca0106.h.

#define SPI_FMT_BIT_LJ   (1<<0) /* left justified mode */

Definition at line 583 of file ca0106.h.

#define SPI_FMT_BIT_RJ   (0<<0) /* right justified mode */

Definition at line 582 of file ca0106.h.

#define SPI_FMT_REG   3

Definition at line 581 of file ca0106.h.

#define SPI_IWL_BIT_16   (0<<4) /* 16-bit world length */

Definition at line 591 of file ca0106.h.

#define SPI_IWL_BIT_20   (1<<4) /* 20-bit world length */

Definition at line 592 of file ca0106.h.

#define SPI_IWL_BIT_24   (2<<4) /* 24-bit world length */

Definition at line 593 of file ca0106.h.

#define SPI_IWL_BIT_32   (3<<4) /* 32-bit world length */

Definition at line 594 of file ca0106.h.

#define SPI_IWL_REG   3

Definition at line 590 of file ca0106.h.

#define SPI_IZD_BIT   (1<<4) /* infinite zero detect */

Definition at line 579 of file ca0106.h.

#define SPI_IZD_REG   2

Definition at line 578 of file ca0106.h.

#define SPI_LDA1_REG   0 /* digital attenuation */

Definition at line 555 of file ca0106.h.

#define SPI_LDA2_REG   4

Definition at line 557 of file ca0106.h.

#define SPI_LDA3_REG   6

Definition at line 559 of file ca0106.h.

#define SPI_LDA4_REG   13

Definition at line 561 of file ca0106.h.

#define SPI_LRP_BIT   (1<<2) /* invert LRCLK polarity */

Definition at line 587 of file ca0106.h.

#define SPI_LRP_REG   3

Definition at line 586 of file ca0106.h.

#define SPI_MASTDA_REG   8

Definition at line 563 of file ca0106.h.

#define SPI_MS_BIT   (1<<5) /* master mode */

Definition at line 597 of file ca0106.h.

#define SPI_MS_REG   10

Definition at line 596 of file ca0106.h.

#define SPI_PDWN_BIT   (1<<2)

Definition at line 626 of file ca0106.h.

#define SPI_PDWN_REG   2 /* power down all DACs */

Definition at line 625 of file ca0106.h.

#define SPI_PHASE0_BIT   (1<<6)

Definition at line 620 of file ca0106.h.

#define SPI_PHASE0_REG   3

Definition at line 616 of file ca0106.h.

#define SPI_PHASE1_BIT   (1<<7)

Definition at line 621 of file ca0106.h.

#define SPI_PHASE1_REG   3

Definition at line 617 of file ca0106.h.

#define SPI_PHASE2_BIT   (1<<8)

Definition at line 622 of file ca0106.h.

#define SPI_PHASE2_REG   3

Definition at line 618 of file ca0106.h.

#define SPI_PHASE4_BIT   (1<<3)

Definition at line 623 of file ca0106.h.

#define SPI_PHASE4_REG   15

Definition at line 619 of file ca0106.h.

#define SPI_PL_BIT_L_C   (3<<5) /* left channel = (L+R)/2 */

Definition at line 573 of file ca0106.h.

#define SPI_PL_BIT_L_L   (1<<5) /* left channel = left */

Definition at line 571 of file ca0106.h.

#define SPI_PL_BIT_L_M   (0<<5) /* left channel = mute */

Definition at line 570 of file ca0106.h.

#define SPI_PL_BIT_L_R   (2<<5) /* left channel = right */

Definition at line 572 of file ca0106.h.

#define SPI_PL_BIT_R_C   (3<<7) /* right channel = (L+R)/2 */

Definition at line 577 of file ca0106.h.

#define SPI_PL_BIT_R_L   (1<<7) /* right channel = left */

Definition at line 575 of file ca0106.h.

#define SPI_PL_BIT_R_M   (0<<7) /* right channel = mute */

Definition at line 574 of file ca0106.h.

#define SPI_PL_BIT_R_R   (2<<7) /* right channel = right */

Definition at line 576 of file ca0106.h.

#define SPI_PL_REG   2

Definition at line 569 of file ca0106.h.

#define SPI_PWRDNALL_BIT   (1<<4)

Definition at line 637 of file ca0106.h.

#define SPI_PWRDNALL_REG   10 /* power down everything */

Definition at line 636 of file ca0106.h.

#define SPI_RATE_BIT_128   (0<<6) /* MCLK = LRCLK * 128 */

Definition at line 599 of file ca0106.h.

#define SPI_RATE_BIT_192   (1<<6)

Definition at line 600 of file ca0106.h.

#define SPI_RATE_BIT_256   (2<<6)

Definition at line 601 of file ca0106.h.

#define SPI_RATE_BIT_384   (3<<6)

Definition at line 602 of file ca0106.h.

#define SPI_RATE_BIT_512   (4<<6)

Definition at line 603 of file ca0106.h.

#define SPI_RATE_BIT_768   (5<<6)

Definition at line 604 of file ca0106.h.

#define SPI_RATE_REG   10 /* only applies in master mode */

Definition at line 598 of file ca0106.h.

#define SPI_RDA1_REG   1

Definition at line 556 of file ca0106.h.

#define SPI_RDA2_REG   5

Definition at line 558 of file ca0106.h.

#define SPI_RDA3_REG   7

Definition at line 560 of file ca0106.h.

#define SPI_RDA4_REG   14

Definition at line 562 of file ca0106.h.

#define SPI_REG_MASK   0x1ff /* 16-bit SPI writes have a 7-bit address */

Definition at line 552 of file ca0106.h.

#define SPI_REG_SHIFT   9 /* followed by 9 bits of data */

Definition at line 553 of file ca0106.h.

#define UNKNOWN10   0x10 /* Unknown ??. Defaults to 0 */

Definition at line 126 of file ca0106.h.

#define UNKNOWN6b   0x6b /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */

Definition at line 396 of file ca0106.h.

#define UNKNOWN73   0x73 /* Unknown. Readonly. Default 0x0 */

Definition at line 465 of file ca0106.h.

#define WATERMARK   0x46 /* Test bit to indicate cache usage level */

Definition at line 319 of file ca0106.h.

Function Documentation

int snd_ca0106_i2c_write ( struct snd_ca0106 emu,
u32  reg,
u32  value 
)

Definition at line 411 of file ca0106_main.c.

int snd_ca0106_mixer ( struct snd_ca0106 emu)

Definition at line 812 of file ca0106_mixer.c.

int snd_ca0106_proc_init ( struct snd_ca0106 emu)
unsigned int snd_ca0106_ptr_read ( struct snd_ca0106 emu,
unsigned int  reg,
unsigned int  chn 
)

Definition at line 346 of file ca0106_main.c.

void snd_ca0106_ptr_write ( struct snd_ca0106 emu,
unsigned int  reg,
unsigned int  chn,
unsigned int  data 
)

Definition at line 362 of file ca0106_main.c.

int snd_ca0106_spi_write ( struct snd_ca0106 emu,
unsigned int  data 
)

Definition at line 378 of file ca0106_main.c.