|
| #define | XGMAC_CONTROL 0x00000000 /* MAC Configuration */ |
| |
| #define | XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */ |
| |
| #define | XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */ |
| |
| #define | XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */ |
| |
| #define | XGMAC_VERSION 0x00000020 /* Version */ |
| |
| #define | XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */ |
| |
| #define | XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */ |
| |
| #define | XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */ |
| |
| #define | XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */ |
| |
| #define | XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */ |
| |
| #define | XGMAC_DEBUG 0x00000038 /* Debug */ |
| |
| #define | XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */ |
| |
| #define | XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8)) |
| |
| #define | XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8)) |
| |
| #define | XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */ |
| |
| #define | XGMAC_NUM_HASH 16 |
| |
| #define | XGMAC_OMR 0x00000400 |
| |
| #define | XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */ |
| |
| #define | XGMAC_PMT 0x00000704 /* PMT Control and Status */ |
| |
| #define | XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */ |
| |
| #define | XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */ |
| |
| #define | XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */ |
| |
| #define | XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */ |
| |
| #define | XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */ |
| |
| #define | XGMAC_MMC_TXOCTET_GB_LO 0x00000814 |
| |
| #define | XGMAC_MMC_TXOCTET_GB_HI 0x00000818 |
| |
| #define | XGMAC_MMC_TXFRAME_GB_LO 0x0000081C |
| |
| #define | XGMAC_MMC_TXFRAME_GB_HI 0x00000820 |
| |
| #define | XGMAC_MMC_TXBCFRAME_G 0x00000824 |
| |
| #define | XGMAC_MMC_TXMCFRAME_G 0x0000082C |
| |
| #define | XGMAC_MMC_TXUCFRAME_GB 0x00000864 |
| |
| #define | XGMAC_MMC_TXMCFRAME_GB 0x0000086C |
| |
| #define | XGMAC_MMC_TXBCFRAME_GB 0x00000874 |
| |
| #define | XGMAC_MMC_TXUNDERFLOW 0x0000087C |
| |
| #define | XGMAC_MMC_TXOCTET_G_LO 0x00000884 |
| |
| #define | XGMAC_MMC_TXOCTET_G_HI 0x00000888 |
| |
| #define | XGMAC_MMC_TXFRAME_G_LO 0x0000088C |
| |
| #define | XGMAC_MMC_TXFRAME_G_HI 0x00000890 |
| |
| #define | XGMAC_MMC_TXPAUSEFRAME 0x00000894 |
| |
| #define | XGMAC_MMC_TXVLANFRAME 0x0000089C |
| |
| #define | XGMAC_MMC_RXFRAME_GB_LO 0x00000900 |
| |
| #define | XGMAC_MMC_RXFRAME_GB_HI 0x00000904 |
| |
| #define | XGMAC_MMC_RXOCTET_GB_LO 0x00000908 |
| |
| #define | XGMAC_MMC_RXOCTET_GB_HI 0x0000090C |
| |
| #define | XGMAC_MMC_RXOCTET_G_LO 0x00000910 |
| |
| #define | XGMAC_MMC_RXOCTET_G_HI 0x00000914 |
| |
| #define | XGMAC_MMC_RXBCFRAME_G 0x00000918 |
| |
| #define | XGMAC_MMC_RXMCFRAME_G 0x00000920 |
| |
| #define | XGMAC_MMC_RXCRCERR 0x00000928 |
| |
| #define | XGMAC_MMC_RXRUNT 0x00000930 |
| |
| #define | XGMAC_MMC_RXJABBER 0x00000934 |
| |
| #define | XGMAC_MMC_RXUCFRAME_G 0x00000970 |
| |
| #define | XGMAC_MMC_RXLENGTHERR 0x00000978 |
| |
| #define | XGMAC_MMC_RXPAUSEFRAME 0x00000988 |
| |
| #define | XGMAC_MMC_RXOVERFLOW 0x00000990 |
| |
| #define | XGMAC_MMC_RXVLANFRAME 0x00000998 |
| |
| #define | XGMAC_MMC_RXWATCHDOG 0x000009a0 |
| |
| #define | XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */ |
| |
| #define | XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */ |
| |
| #define | XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */ |
| |
| #define | XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */ |
| |
| #define | XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */ |
| |
| #define | XGMAC_DMA_STATUS 0x00000f14 /* Status Register */ |
| |
| #define | XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */ |
| |
| #define | XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */ |
| |
| #define | XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */ |
| |
| #define | XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */ |
| |
| #define | XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */ |
| |
| #define | XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */ |
| |
| #define | XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */ |
| |
| #define | XGMAC_ADDR_AE 0x80000000 |
| |
| #define | XGMAC_MAX_FILTER_ADDR 31 |
| |
| #define | XGMAC_PMT_POINTER_RESET 0x80000000 |
| |
| #define | XGMAC_PMT_GLBL_UNICAST 0x00000200 |
| |
| #define | XGMAC_PMT_WAKEUP_RX_FRM 0x00000040 |
| |
| #define | XGMAC_PMT_MAGIC_PKT 0x00000020 |
| |
| #define | XGMAC_PMT_WAKEUP_FRM_EN 0x00000004 |
| |
| #define | XGMAC_PMT_MAGIC_PKT_EN 0x00000002 |
| |
| #define | XGMAC_PMT_POWERDOWN 0x00000001 |
| |
| #define | XGMAC_CONTROL_SPD 0x40000000 /* Speed control */ |
| |
| #define | XGMAC_CONTROL_SPD_MASK 0x60000000 |
| |
| #define | XGMAC_CONTROL_SPD_1G 0x60000000 |
| |
| #define | XGMAC_CONTROL_SPD_2_5G 0x40000000 |
| |
| #define | XGMAC_CONTROL_SPD_10G 0x00000000 |
| |
| #define | XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */ |
| |
| #define | XGMAC_CONTROL_SARK_MASK 0x18000000 |
| |
| #define | XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */ |
| |
| #define | XGMAC_CONTROL_CAR_MASK 0x06000000 |
| |
| #define | XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */ |
| |
| #define | XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */ |
| |
| #define | XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */ |
| |
| #define | XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ |
| |
| #define | XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ |
| |
| #define | XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ |
| |
| #define | XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */ |
| |
| #define | XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */ |
| |
| #define | XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ |
| |
| #define | XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ |
| |
| #define | XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ |
| |
| #define | XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ |
| |
| #define | XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ |
| |
| #define | XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ |
| |
| #define | XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ |
| |
| #define | XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ |
| |
| #define | XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ |
| |
| #define | XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ |
| |
| #define | XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ |
| |
| #define | XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */ |
| |
| #define | XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */ |
| |
| #define | XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ |
| |
| #define | XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ |
| |
| #define | XGMAC_FLOW_CTRL_PT_SHIFT 16 |
| |
| #define | XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */ |
| |
| #define | XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */ |
| |
| #define | XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */ |
| |
| #define | XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */ |
| |
| #define | XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ |
| |
| #define | XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ |
| |
| #define | XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ |
| |
| #define | XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */ |
| |
| #define | XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */ |
| |
| #define | DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */ |
| |
| #define | DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ |
| |
| #define | DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ |
| |
| #define | DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ |
| |
| #define | DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ |
| |
| #define | DMA_BUS_MODE_PBL_SHIFT 8 |
| |
| #define | DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ |
| |
| #define | DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ |
| |
| #define | DMA_BUS_MODE_RPBL_SHIFT 17 |
| |
| #define | DMA_BUS_MODE_USP 0x00800000 |
| |
| #define | DMA_BUS_MODE_8PBL 0x01000000 |
| |
| #define | DMA_BUS_MODE_AAL 0x02000000 |
| |
| #define | DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ |
| |
| #define | DMA_BUS_PR_RATIO_SHIFT 14 |
| |
| #define | DMA_BUS_FB 0x00010000 /* Fixed Burst */ |
| |
| #define | DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ |
| |
| #define | DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ |
| |
| #define | DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */ |
| |
| #define | DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */ |
| |
| #define | DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */ |
| |
| #define | DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */ |
| |
| #define | DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */ |
| |
| #define | DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */ |
| |
| #define | DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */ |
| |
| #define | DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */ |
| |
| #define | DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */ |
| |
| #define | DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */ |
| |
| #define | DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */ |
| |
| #define | DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */ |
| |
| #define | DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */ |
| |
| #define | DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */ |
| |
| #define | DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */ |
| |
| #define | DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */ |
| |
| #define | DMA_INTR_NORMAL |
| |
| #define | DMA_INTR_ABNORMAL |
| |
| #define | DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL) |
| |
| #define | DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ |
| |
| #define | DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ |
| |
| #define | DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ |
| |
| #define | DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ |
| |
| #define | DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ |
| |
| #define | DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ |
| |
| #define | DMA_STATUS_TS_SHIFT 20 |
| |
| #define | DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ |
| |
| #define | DMA_STATUS_RS_SHIFT 17 |
| |
| #define | DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ |
| |
| #define | DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ |
| |
| #define | DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ |
| |
| #define | DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ |
| |
| #define | DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ |
| |
| #define | DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ |
| |
| #define | DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ |
| |
| #define | DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ |
| |
| #define | DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ |
| |
| #define | DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ |
| |
| #define | DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ |
| |
| #define | DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ |
| |
| #define | DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */ |
| |
| #define | DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ |
| |
| #define | DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ |
| |
| #define | MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ |
| |
| #define | MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ |
| |
| #define | XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */ |
| |
| #define | XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */ |
| |
| #define | XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */ |
| |
| #define | XGMAC_OMR_TTC_MASK 0x00030000 |
| |
| #define | XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */ |
| |
| #define | XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */ |
| |
| #define | XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */ |
| |
| #define | XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */ |
| |
| #define | XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */ |
| |
| #define | XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */ |
| |
| #define | XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */ |
| |
| #define | XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */ |
| |
| #define | XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */ |
| |
| #define | XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */ |
| |
| #define | DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */ |
| |
| #define | XGMAC_MMC_CTRL_CNT_FRZ 0x00000008 |
| |
| #define | MAX_DESC_BUF_SZ (0x2000 - 8) |
| |
| #define | RXDESC_EXT_STATUS 0x00000001 |
| |
| #define | RXDESC_CRC_ERR 0x00000002 |
| |
| #define | RXDESC_RX_ERR 0x00000008 |
| |
| #define | RXDESC_RX_WDOG 0x00000010 |
| |
| #define | RXDESC_FRAME_TYPE 0x00000020 |
| |
| #define | RXDESC_GIANT_FRAME 0x00000080 |
| |
| #define | RXDESC_LAST_SEG 0x00000100 |
| |
| #define | RXDESC_FIRST_SEG 0x00000200 |
| |
| #define | RXDESC_VLAN_FRAME 0x00000400 |
| |
| #define | RXDESC_OVERFLOW_ERR 0x00000800 |
| |
| #define | RXDESC_LENGTH_ERR 0x00001000 |
| |
| #define | RXDESC_SA_FILTER_FAIL 0x00002000 |
| |
| #define | RXDESC_DESCRIPTOR_ERR 0x00004000 |
| |
| #define | RXDESC_ERROR_SUMMARY 0x00008000 |
| |
| #define | RXDESC_FRAME_LEN_OFFSET 16 |
| |
| #define | RXDESC_FRAME_LEN_MASK 0x3fff0000 |
| |
| #define | RXDESC_DA_FILTER_FAIL 0x40000000 |
| |
| #define | RXDESC1_END_RING 0x00008000 |
| |
| #define | RXDESC_IP_PAYLOAD_MASK 0x00000003 |
| |
| #define | RXDESC_IP_PAYLOAD_UDP 0x00000001 |
| |
| #define | RXDESC_IP_PAYLOAD_TCP 0x00000002 |
| |
| #define | RXDESC_IP_PAYLOAD_ICMP 0x00000003 |
| |
| #define | RXDESC_IP_HEADER_ERR 0x00000008 |
| |
| #define | RXDESC_IP_PAYLOAD_ERR 0x00000010 |
| |
| #define | RXDESC_IPV4_PACKET 0x00000040 |
| |
| #define | RXDESC_IPV6_PACKET 0x00000080 |
| |
| #define | TXDESC_UNDERFLOW_ERR 0x00000001 |
| |
| #define | TXDESC_JABBER_TIMEOUT 0x00000002 |
| |
| #define | TXDESC_LOCAL_FAULT 0x00000004 |
| |
| #define | TXDESC_REMOTE_FAULT 0x00000008 |
| |
| #define | TXDESC_VLAN_FRAME 0x00000010 |
| |
| #define | TXDESC_FRAME_FLUSHED 0x00000020 |
| |
| #define | TXDESC_IP_HEADER_ERR 0x00000040 |
| |
| #define | TXDESC_PAYLOAD_CSUM_ERR 0x00000080 |
| |
| #define | TXDESC_ERROR_SUMMARY 0x00008000 |
| |
| #define | TXDESC_SA_CTRL_INSERT 0x00040000 |
| |
| #define | TXDESC_SA_CTRL_REPLACE 0x00080000 |
| |
| #define | TXDESC_2ND_ADDR_CHAINED 0x00100000 |
| |
| #define | TXDESC_END_RING 0x00200000 |
| |
| #define | TXDESC_CSUM_IP 0x00400000 |
| |
| #define | TXDESC_CSUM_IP_PAYLD 0x00800000 |
| |
| #define | TXDESC_CSUM_ALL 0x00C00000 |
| |
| #define | TXDESC_CRC_EN_REPLACE 0x01000000 |
| |
| #define | TXDESC_CRC_EN_APPEND 0x02000000 |
| |
| #define | TXDESC_DISABLE_PAD 0x04000000 |
| |
| #define | TXDESC_FIRST_SEG 0x10000000 |
| |
| #define | TXDESC_LAST_SEG 0x20000000 |
| |
| #define | TXDESC_INTERRUPT 0x40000000 |
| |
| #define | DESC_OWN 0x80000000 |
| |
| #define | DESC_BUFFER1_SZ_MASK 0x00001fff |
| |
| #define | DESC_BUFFER2_SZ_MASK 0x1fff0000 |
| |
| #define | DESC_BUFFER2_SZ_OFFSET 16 |
| |
| #define | MAX_MTU 9000 |
| |
| #define | PAUSE_TIME 0x400 |
| |
| #define | DMA_RX_RING_SZ 256 |
| |
| #define | DMA_TX_RING_SZ 128 |
| |
| #define | TX_THRESH (DMA_TX_RING_SZ/4) |
| |
| #define | dma_ring_incr(n, s) (((n) + 1) & ((s) - 1)) |
| |
| #define | dma_ring_space(h, t, s) CIRC_SPACE(h, t, s) |
| |
| #define | dma_ring_cnt(h, t, s) CIRC_CNT(h, t, s) |
| |
| #define | XGMAC_STAT(m) { #m, offsetof(struct xgmac_priv, xstats.m), false } |
| |
| #define | XGMAC_HW_STAT(m, reg_offset) { #m, reg_offset, true } |
| |
| #define | XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats) |
| |
| #define | XGMAC_PM_OPS NULL |
| |
1.8.2