Macros
#define	DMA_BUS_MODE 0x00001000 /* Bus Mode */

#define	DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */

#define	DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */

#define	DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */

#define	DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */

#define	DMA_STATUS 0x00001014 /* Status Register */

#define	DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */

#define	DMA_INTR_ENA 0x0000101c /* Interrupt Enable */

#define	DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */

#define	DMA_AXI_BUS_MODE 0x00001028 /* AXI Bus Mode */

#define	DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */

#define	DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */

#define	DMA_HW_FEATURE 0x00001058 /* HW Feature Register */

#define	DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */

#define	DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */

#define	DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */

#define	DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */

#define	DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */

#define	DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */

#define	DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */

#define	DMA_INTR_NORMAL

#define	DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */

#define	DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */

#define	DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */

#define	DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */

#define	DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */

#define	DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */

#define	DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */

#define	DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */

#define	DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */

#define	DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */

#define	DMA_INTR_ABNORMAL

#define	DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL \| DMA_INTR_ABNORMAL)

#define	DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */

#define	DMA_STATUS_GPI 0x10000000 /* PMT interrupt */

#define	DMA_STATUS_GMI 0x08000000 /* MMC interrupt */

#define	DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */

#define	DMA_STATUS_GMI 0x08000000

#define	DMA_STATUS_GLI 0x04000000

#define	DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */

#define	DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */

#define	DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */

#define	DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */

#define	DMA_STATUS_TS_SHIFT 20

#define	DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */

#define	DMA_STATUS_RS_SHIFT 17

#define	DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */

#define	DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */

#define	DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */

#define	DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */

#define	DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */

#define	DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */

#define	DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */

#define	DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */

#define	DMA_STATUS_RI 0x00000040 /* Receive Interrupt */

#define	DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */

#define	DMA_STATUS_OVF 0x00000010 /* Receive Overflow */

#define	DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */

#define	DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */

#define	DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */

#define	DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */

#define	DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */

Functions
void	dwmac_enable_dma_transmission (void __iomem *ioaddr)

void	dwmac_enable_dma_irq (void __iomem *ioaddr)

void	dwmac_disable_dma_irq (void __iomem *ioaddr)

void	dwmac_dma_start_tx (void __iomem *ioaddr)

void	dwmac_dma_stop_tx (void __iomem *ioaddr)

void	dwmac_dma_start_rx (void __iomem *ioaddr)

void	dwmac_dma_stop_rx (void __iomem *ioaddr)

int	dwmac_dma_interrupt (void __iomem ioaddr, struct stmmac_extra_stats x)

Macro Definition Documentation

#define DMA_AXI_BUS_MODE 0x00001028 /* AXI Bus Mode */

Definition at line 38 of file dwmac_dma.h.

#define DMA_BUS_MODE 0x00001000 /* Bus Mode */

Definition at line 29 of file dwmac_dma.h.

#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */

Definition at line 35 of file dwmac_dma.h.

#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */

Definition at line 104 of file dwmac_dma.h.

#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */

Definition at line 45 of file dwmac_dma.h.

#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */

Definition at line 44 of file dwmac_dma.h.

#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */

Definition at line 40 of file dwmac_dma.h.

#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */

Definition at line 39 of file dwmac_dma.h.

#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */

Definition at line 41 of file dwmac_dma.h.

#define DMA_INTR_ABNORMAL

Value:

(DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \

DMA_INTR_ENA_UNE)

Definition at line 69 of file dwmac_dma.h.

#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)

Definition at line 73 of file dwmac_dma.h.

#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */

Definition at line 36 of file dwmac_dma.h.

#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */

Definition at line 58 of file dwmac_dma.h.

#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */

Definition at line 52 of file dwmac_dma.h.

#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */

Definition at line 60 of file dwmac_dma.h.

#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */

Definition at line 59 of file dwmac_dma.h.

#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */

Definition at line 48 of file dwmac_dma.h.

#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */

Definition at line 65 of file dwmac_dma.h.

#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */

Definition at line 51 of file dwmac_dma.h.

#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */

Definition at line 62 of file dwmac_dma.h.

#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */

Definition at line 63 of file dwmac_dma.h.

#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */

Definition at line 61 of file dwmac_dma.h.

#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */

Definition at line 49 of file dwmac_dma.h.

#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */

Definition at line 66 of file dwmac_dma.h.

#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */

Definition at line 67 of file dwmac_dma.h.

#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */

Definition at line 50 of file dwmac_dma.h.

#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */

Definition at line 64 of file dwmac_dma.h.

#define DMA_INTR_NORMAL

Value:

(DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \

DMA_INTR_ENA_TIE)

Definition at line 54 of file dwmac_dma.h.

#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */

Definition at line 37 of file dwmac_dma.h.

#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */

Definition at line 32 of file dwmac_dma.h.

#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */

Definition at line 31 of file dwmac_dma.h.

#define DMA_STATUS 0x00001014 /* Status Register */

Definition at line 34 of file dwmac_dma.h.

#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */

Definition at line 90 of file dwmac_dma.h.

#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */

Definition at line 82 of file dwmac_dma.h.

#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */

Definition at line 84 of file dwmac_dma.h.

#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */

Definition at line 83 of file dwmac_dma.h.

#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */

Definition at line 91 of file dwmac_dma.h.

#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */

Definition at line 93 of file dwmac_dma.h.

#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */

Definition at line 92 of file dwmac_dma.h.

#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */

Definition at line 81 of file dwmac_dma.h.

#define DMA_STATUS_GLI 0x04000000

Definition at line 81 of file dwmac_dma.h.

#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */

Definition at line 76 of file dwmac_dma.h.

#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */

Definition at line 80 of file dwmac_dma.h.

#define DMA_STATUS_GMI 0x08000000

Definition at line 80 of file dwmac_dma.h.

#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */

Definition at line 77 of file dwmac_dma.h.

#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */

Definition at line 89 of file dwmac_dma.h.

#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */

Definition at line 99 of file dwmac_dma.h.

#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */

Definition at line 97 of file dwmac_dma.h.

#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */

Definition at line 95 of file dwmac_dma.h.

#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */

Definition at line 87 of file dwmac_dma.h.

#define DMA_STATUS_RS_SHIFT 17

Definition at line 88 of file dwmac_dma.h.

#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */

Definition at line 96 of file dwmac_dma.h.

#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */

Definition at line 94 of file dwmac_dma.h.

#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */

Definition at line 103 of file dwmac_dma.h.

#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */

Definition at line 100 of file dwmac_dma.h.

#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */

Definition at line 102 of file dwmac_dma.h.

#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */

Definition at line 85 of file dwmac_dma.h.

#define DMA_STATUS_TS_SHIFT 20

Definition at line 86 of file dwmac_dma.h.

#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */

Definition at line 101 of file dwmac_dma.h.

#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */

Definition at line 98 of file dwmac_dma.h.

#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */

Definition at line 33 of file dwmac_dma.h.

#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */

Definition at line 30 of file dwmac_dma.h.

Function Documentation

void dwmac_disable_dma_irq ( void __iomem * ioaddr )

Definition at line 47 of file dwmac_lib.c.

int dwmac_dma_interrupt	(	void __iomem *	ioaddr,
		struct stmmac_extra_stats *	x
	)

Definition at line 150 of file dwmac_lib.c.

void dwmac_dma_start_rx ( void __iomem * ioaddr )

Definition at line 66 of file dwmac_lib.c.

void dwmac_dma_start_tx ( void __iomem * ioaddr )

Definition at line 52 of file dwmac_lib.c.

void dwmac_dma_stop_rx ( void __iomem * ioaddr )

Definition at line 73 of file dwmac_lib.c.

void dwmac_dma_stop_tx ( void __iomem * ioaddr )

Definition at line 59 of file dwmac_lib.c.

void dwmac_enable_dma_irq ( void __iomem * ioaddr )

Definition at line 42 of file dwmac_lib.c.

void dwmac_enable_dma_transmission ( void __iomem * ioaddr )

Definition at line 37 of file dwmac_lib.c.

Macros

Functions

Macro Definition Documentation

Function Documentation