|
| enum | base_address_regions {
PLX9080_BADDRINDEX = 0,
MAIN_BADDRINDEX = 2,
DIO_COUNTER_BADDRINDEX = 3,
PLX9080_BADDRINDEX = 0,
HPDI_BADDRINDEX = 2
} |
| |
| enum | write_only_registers {
INTR_ENABLE_REG = 0x0,
HW_CONFIG_REG = 0x2,
DAQ_SYNC_REG = 0xc,
DAQ_ATRIG_LOW_4020_REG = 0xc,
ADC_CONTROL0_REG = 0x10,
ADC_CONTROL1_REG = 0x12,
CALIBRATION_REG = 0x14,
ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
ADC_COUNT_LOWER_REG = 0x1e,
ADC_COUNT_UPPER_REG = 0x20,
ADC_START_REG = 0x22,
ADC_CONVERT_REG = 0x24,
ADC_QUEUE_CLEAR_REG = 0x26,
ADC_QUEUE_LOAD_REG = 0x28,
ADC_BUFFER_CLEAR_REG = 0x2a,
ADC_QUEUE_HIGH_REG = 0x2c,
DAC_CONTROL0_REG = 0x50,
DAC_CONTROL1_REG = 0x52,
DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
DAC_SELECT_REG = 0x60,
DAC_START_REG = 0x64,
DAC_BUFFER_CLEAR_REG = 0x66
} |
| |
| enum | read_only_registers {
HW_STATUS_REG = 0x0,
PIPE1_READ_REG = 0x4,
ADC_READ_PNTR_REG = 0x8,
LOWER_XFER_REG = 0x10,
ADC_WRITE_PNTR_REG = 0xc,
PREPOST_REG = 0x14
} |
| |
| enum | read_write_registers { I8255_4020_REG = 0x48,
ADC_QUEUE_FIFO_REG = 0x100,
ADC_FIFO_REG = 0x200,
DAC_FIFO_REG = 0x300
} |
| |
| enum | dio_counter_registers {
DIO_8255_OFFSET = 0x0,
DO_REG = 0x20,
DI_REG = 0x28,
DIO_DIRECTION_60XX_REG = 0x40,
DIO_DATA_60XX_REG = 0x48
} |
| |
| enum | intr_enable_contents {
ADC_INTR_SRC_MASK = 0x3,
ADC_INTR_QFULL_BITS = 0x0,
ADC_INTR_EOC_BITS = 0x1,
ADC_INTR_EOSCAN_BITS = 0x2,
ADC_INTR_EOSEQ_BITS = 0x3,
EN_ADC_INTR_SRC_BIT = 0x4,
EN_ADC_DONE_INTR_BIT = 0x8,
DAC_INTR_SRC_MASK = 0x30,
DAC_INTR_QEMPTY_BITS = 0x0,
DAC_INTR_HIGH_CHAN_BITS = 0x10,
EN_DAC_INTR_SRC_BIT = 0x40,
EN_DAC_DONE_INTR_BIT = 0x80,
EN_ADC_ACTIVE_INTR_BIT = 0x200,
EN_ADC_STOP_INTR_BIT = 0x400,
EN_DAC_ACTIVE_INTR_BIT = 0x800,
EN_DAC_UNDERRUN_BIT = 0x4000,
EN_ADC_OVERRUN_BIT = 0x8000
} |
| |
| enum | hw_config_contents {
MASTER_CLOCK_4020_MASK = 0x3,
INTERNAL_CLOCK_4020_BITS = 0x1,
BNC_CLOCK_4020_BITS = 0x2,
EXT_CLOCK_4020_BITS = 0x3,
EXT_QUEUE_BIT = 0x200,
SLOW_DAC_BIT = 0x400,
HW_CONFIG_DUMMY_BITS = 0x2000,
DMA_CH_SELECT_BIT = 0x8000,
FIFO_SIZE_REG = 0x4,
DAC_FIFO_SIZE_MASK = 0xff00,
DAC_FIFO_BITS = 0xf800
} |
| |
| enum | daq_atrig_low_4020_contents { EXT_AGATE_BNC_BIT = 0x8000,
EXT_STOP_TRIG_BNC_BIT = 0x4000,
EXT_START_TRIG_BNC_BIT = 0x2000
} |
| |
| enum | adc_control0_contents {
ADC_GATE_SRC_MASK = 0x3,
ADC_SOFT_GATE_BITS = 0x1,
ADC_EXT_GATE_BITS = 0x2,
ADC_ANALOG_GATE_BITS = 0x3,
ADC_GATE_LEVEL_BIT = 0x4,
ADC_GATE_POLARITY_BIT = 0x8,
ADC_START_TRIG_SOFT_BITS = 0x10,
ADC_START_TRIG_EXT_BITS = 0x20,
ADC_START_TRIG_ANALOG_BITS = 0x30,
ADC_START_TRIG_MASK = 0x30,
ADC_START_TRIG_FALLING_BIT = 0x40,
ADC_EXT_CONV_FALLING_BIT = 0x800,
ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
ADC_DMA_DISABLE_BIT = 0x4000,
ADC_ENABLE_BIT = 0x8000
} |
| |
| enum | adc_control1_contents {
ADC_QUEUE_CONFIG_BIT = 0x1,
CONVERT_POLARITY_BIT = 0x10,
EOC_POLARITY_BIT = 0x20,
ADC_SW_GATE_BIT = 0x40,
ADC_DITHER_BIT = 0x200,
RETRIGGER_BIT = 0x800,
ADC_LO_CHANNEL_4020_MASK = 0x300,
ADC_HI_CHANNEL_4020_MASK = 0xc00,
TWO_CHANNEL_4020_BITS = 0x1000,
FOUR_CHANNEL_4020_BITS = 0x2000,
CHANNEL_MODE_4020_MASK = 0x3000,
ADC_MODE_MASK = 0xf000
} |
| |
| enum | calibration_contents {
SELECT_8800_BIT = 0x1,
SELECT_8402_64XX_BIT = 0x2,
SELECT_1590_60XX_BIT = 0x2,
CAL_EN_64XX_BIT = 0x40,
SERIAL_DATA_IN_BIT = 0x80,
SERIAL_CLOCK_BIT = 0x100,
CAL_EN_60XX_BIT = 0x200,
CAL_GAIN_BIT = 0x800
} |
| |
| enum | adc_queue_load_contents {
UNIP_BIT = 0x800,
ADC_SE_DIFF_BIT = 0x1000,
ADC_COMMON_BIT = 0x2000,
QUEUE_EOSEQ_BIT = 0x4000,
QUEUE_EOSCAN_BIT = 0x8000
} |
| |
| enum | dac_control0_contents {
DAC_ENABLE_BIT = 0x8000,
DAC_CYCLIC_STOP_BIT = 0x4000,
DAC_WAVEFORM_MODE_BIT = 0x100,
DAC_EXT_UPDATE_FALLING_BIT = 0x80,
DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
WAVEFORM_TRIG_MASK = 0x30,
WAVEFORM_TRIG_DISABLED_BITS = 0x0,
WAVEFORM_TRIG_SOFT_BITS = 0x10,
WAVEFORM_TRIG_EXT_BITS = 0x20,
WAVEFORM_TRIG_ADC1_BITS = 0x30,
WAVEFORM_TRIG_FALLING_BIT = 0x8,
WAVEFORM_GATE_LEVEL_BIT = 0x4,
WAVEFORM_GATE_ENABLE_BIT = 0x2,
WAVEFORM_GATE_SELECT_BIT = 0x1
} |
| |
| enum | dac_control1_contents {
DAC_WRITE_POLARITY_BIT = 0x800,
DAC1_EXT_REF_BIT = 0x200,
DAC0_EXT_REF_BIT = 0x100,
DAC_OUTPUT_ENABLE_BIT = 0x80,
DAC_UPDATE_POLARITY_BIT = 0x40,
DAC_SW_GATE_BIT = 0x20,
DAC1_UNIPOLAR_BIT = 0x8,
DAC0_UNIPOLAR_BIT = 0x2
} |
| |
| enum | hw_status_contents {
DAC_UNDERRUN_BIT = 0x1,
ADC_OVERRUN_BIT = 0x2,
DAC_ACTIVE_BIT = 0x4,
ADC_ACTIVE_BIT = 0x8,
DAC_INTR_PENDING_BIT = 0x10,
ADC_INTR_PENDING_BIT = 0x20,
DAC_DONE_BIT = 0x40,
ADC_DONE_BIT = 0x80,
EXT_INTR_PENDING_BIT = 0x100,
ADC_STOP_BIT = 0x200
} |
| |
| enum | i2c_addresses { RANGE_CAL_I2C_ADDR = 0x20,
CALDAC0_I2C_ADDR = 0xc,
CALDAC1_I2C_ADDR = 0xd
} |
| |
| enum | range_cal_i2c_contents { ADC_SRC_4020_MASK = 0x70,
BNC_TRIG_THRESHOLD_0V_BIT = 0x80
} |
| |
| enum | register_layout { LAYOUT_60XX,
LAYOUT_64XX,
LAYOUT_4020
} |
| |
1.8.2