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cb_pcidas64.c
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1 /*
2  comedi/drivers/cb_pcidas64.c
3  This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4  64xx, 60xx, and 4020 cards.
5 
6  Author: Frank Mori Hess <[email protected]>
7  Copyright (C) 2001, 2002 Frank Mori Hess
8 
9  Thanks also go to the following people:
10 
11  Steve Rosenbluth, for providing the source code for
12  his pci-das6402 driver, and source code for working QNX pci-6402
13  drivers by Greg Laird and Mariusz Bogacz. None of the code was
14  used directly here, but it was useful as an additional source of
15  documentation on how to program the boards.
16 
17  John Sims, for much testing and feedback on pcidas-4020 support.
18 
19  COMEDI - Linux Control and Measurement Device Interface
20  Copyright (C) 1997-8 David A. Schleef <[email protected]>
21 
22  This program is free software; you can redistribute it and/or modify
23  it under the terms of the GNU General Public License as published by
24  the Free Software Foundation; either version 2 of the License, or
25  (at your option) any later version.
26 
27  This program is distributed in the hope that it will be useful,
28  but WITHOUT ANY WARRANTY; without even the implied warranty of
29  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30  GNU General Public License for more details.
31 
32  You should have received a copy of the GNU General Public License
33  along with this program; if not, write to the Free Software
34  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 
36 ************************************************************************/
37 
38 /*
39 
40 Driver: cb_pcidas64
41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
42 Author: Frank Mori Hess <[email protected]>
43 Status: works
44 Updated: 2002-10-09
45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46  PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47  PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48  PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49  PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50  PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51  PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52  PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53  PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
54 
55 Configuration options:
56  [0] - PCI bus of device (optional)
57  [1] - PCI slot of device (optional)
58 
59 These boards may be autocalibrated with the comedi_calibrate utility.
60 
61 To select the bnc trigger input on the 4020 (instead of the dio input),
62 specify a nonzero channel in the chanspec. If you wish to use an external
63 master clock on the 4020, you may do so by setting the scan_begin_src
64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
65 to configure the divisor to use for the external clock.
66 
67 Some devices are not identified because the PCI device IDs are not yet
68 known. If you have such a board, please file a bug report at
69 https://bugs.comedi.org.
70 
71 */
72 
73 /*
74 
75 TODO:
76  make it return error if user attempts an ai command that uses the
77  external queue, and an ao command simultaneously
78  user counter subdevice
79  there are a number of boards this driver will support when they are
80  fully released, but does not yet since the pci device id numbers
81  are not yet available.
82  support prescaled 100khz clock for slow pacing (not available on 6000 series?)
83  make ao fifo size adjustable like ai fifo
84 */
85 
86 #include "../comedidev.h"
87 #include <linux/delay.h>
88 #include <linux/interrupt.h>
89 
90 #include "8253.h"
91 #include "8255.h"
92 #include "plx9080.h"
93 #include "comedi_fc.h"
94 
95 #undef PCIDAS64_DEBUG /* disable debugging code */
96 /* #define PCIDAS64_DEBUG enable debugging code */
97 
98 #ifdef PCIDAS64_DEBUG
99 #define DEBUG_PRINT(format, args...) printk(format , ## args)
100 #else
101 #define DEBUG_PRINT(format, args...)
102 #endif
103 
104 #define TIMER_BASE 25 /* 40MHz master clock */
105 #define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
106 #define DMA_BUFFER_SIZE 0x1000
107 
108 #define PCI_VENDOR_ID_COMPUTERBOARDS 0x1307
109 
110 /* maximum value that can be loaded into board's 24-bit counters*/
111 static const int max_counter_value = 0xffffff;
112 
113 /* PCI-DAS64xxx base addresses */
114 
115 /* indices of base address regions */
116 enum base_address_regions {
117  PLX9080_BADDRINDEX = 0,
118  MAIN_BADDRINDEX = 2,
119  DIO_COUNTER_BADDRINDEX = 3,
120 };
121 
122 /* priv(dev)->main_iobase registers */
123 enum write_only_registers {
124  INTR_ENABLE_REG = 0x0, /* interrupt enable register */
125  HW_CONFIG_REG = 0x2, /* hardware config register */
126  DAQ_SYNC_REG = 0xc,
127  DAQ_ATRIG_LOW_4020_REG = 0xc,
128  ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
129  ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
130  CALIBRATION_REG = 0x14,
131  ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, /* lower 16 bits of adc sample interval counter */
132  ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, /* upper 8 bits of adc sample interval counter */
133  ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, /* lower 16 bits of delay interval counter */
134  ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, /* upper 8 bits of delay interval counter */
135  ADC_COUNT_LOWER_REG = 0x1e, /* lower 16 bits of hardware conversion/scan counter */
136  ADC_COUNT_UPPER_REG = 0x20, /* upper 8 bits of hardware conversion/scan counter */
137  ADC_START_REG = 0x22, /* software trigger to start acquisition */
138  ADC_CONVERT_REG = 0x24, /* initiates single conversion */
139  ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
140  ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
141  ADC_BUFFER_CLEAR_REG = 0x2a,
142  ADC_QUEUE_HIGH_REG = 0x2c, /* high channel for internal queue, use adc_chan_bits() inline above */
143  DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
144  DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
145  DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, /* lower 16 bits of dac sample interval counter */
146  DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, /* upper 8 bits of dac sample interval counter */
147  DAC_SELECT_REG = 0x60,
148  DAC_START_REG = 0x64,
149  DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
150 };
151 static inline unsigned int dac_convert_reg(unsigned int channel)
152 {
153  return 0x70 + (2 * (channel & 0x1));
154 }
155 
156 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
157 {
158  return 0x70 + (4 * (channel & 0x1));
159 }
160 
161 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
162 {
163  return 0x72 + (4 * (channel & 0x1));
164 }
165 
166 enum read_only_registers {
167  HW_STATUS_REG = 0x0, /* hardware status register, reading this apparently clears pending interrupts as well */
168  PIPE1_READ_REG = 0x4,
169  ADC_READ_PNTR_REG = 0x8,
170  LOWER_XFER_REG = 0x10,
171  ADC_WRITE_PNTR_REG = 0xc,
172  PREPOST_REG = 0x14,
173 };
174 
175 enum read_write_registers {
176  I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
177  ADC_QUEUE_FIFO_REG = 0x100, /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
178  ADC_FIFO_REG = 0x200, /* adc data fifo */
179  DAC_FIFO_REG = 0x300, /* dac data fifo, has weird interactions with external channel queue */
180 };
181 
182 /* priv(dev)->dio_counter_iobase registers */
183 enum dio_counter_registers {
184  DIO_8255_OFFSET = 0x0,
185  DO_REG = 0x20,
186  DI_REG = 0x28,
187  DIO_DIRECTION_60XX_REG = 0x40,
188  DIO_DATA_60XX_REG = 0x48,
189 };
190 
191 /* bit definitions for write-only registers */
192 
193 enum intr_enable_contents {
194  ADC_INTR_SRC_MASK = 0x3, /* bits that set adc interrupt source */
195  ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quater full */
196  ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
197  ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
198  ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */
199  EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
200  EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done interrupt */
201  DAC_INTR_SRC_MASK = 0x30,
202  DAC_INTR_QEMPTY_BITS = 0x0,
203  DAC_INTR_HIGH_CHAN_BITS = 0x10,
204  EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
205  EN_DAC_DONE_INTR_BIT = 0x80,
206  EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
207  EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
208  EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
209  EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
210  EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
211 };
212 
213 enum hw_config_contents {
214  MASTER_CLOCK_4020_MASK = 0x3, /* bits that specify master clock source for 4020 */
215  INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock for 4020 */
216  BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
217  EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
218  EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue (more versatile than internal queue) */
219  SLOW_DAC_BIT = 0x400, /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
220  HW_CONFIG_DUMMY_BITS = 0x2000, /* bit with unknown function yet given as default value in pci-das64 manual */
221  DMA_CH_SELECT_BIT = 0x8000, /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
222  FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
223  DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
224  DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
225 };
226 #define DAC_FIFO_SIZE 0x2000
227 
228 enum daq_atrig_low_4020_contents {
229  EXT_AGATE_BNC_BIT = 0x8000, /* use trig/ext clk bnc input for analog gate signal */
230  EXT_STOP_TRIG_BNC_BIT = 0x4000, /* use trig/ext clk bnc input for external stop trigger signal */
231  EXT_START_TRIG_BNC_BIT = 0x2000, /* use trig/ext clk bnc input for external start trigger signal */
232 };
233 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
234 {
235  return threshold & 0xfff;
236 }
237 
238 enum adc_control0_contents {
239  ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
240  ADC_SOFT_GATE_BITS = 0x1, /* software gate */
241  ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
242  ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
243  ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */
244  ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
245  ADC_START_TRIG_SOFT_BITS = 0x10,
246  ADC_START_TRIG_EXT_BITS = 0x20,
247  ADC_START_TRIG_ANALOG_BITS = 0x30,
248  ADC_START_TRIG_MASK = 0x30,
249  ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
250  ADC_EXT_CONV_FALLING_BIT = 0x800, /* external pacing uses falling edge */
251  ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, /* enable hardware scan counter */
252  ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
253  ADC_ENABLE_BIT = 0x8000, /* master adc enable */
254 };
255 
256 enum adc_control1_contents {
257  ADC_QUEUE_CONFIG_BIT = 0x1, /* should be set for boards with > 16 channels */
258  CONVERT_POLARITY_BIT = 0x10,
259  EOC_POLARITY_BIT = 0x20,
260  ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
261  ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
262  RETRIGGER_BIT = 0x800,
263  ADC_LO_CHANNEL_4020_MASK = 0x300,
264  ADC_HI_CHANNEL_4020_MASK = 0xc00,
265  TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
266  FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
267  CHANNEL_MODE_4020_MASK = 0x3000,
268  ADC_MODE_MASK = 0xf000,
269 };
270 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
271 {
272  return (channel & 0x3) << 8;
273 };
274 
275 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
276 {
277  return (channel & 0x3) << 10;
278 };
279 
280 static inline uint16_t adc_mode_bits(unsigned int mode)
281 {
282  return (mode & 0xf) << 12;
283 };
284 
285 enum calibration_contents {
286  SELECT_8800_BIT = 0x1,
287  SELECT_8402_64XX_BIT = 0x2,
288  SELECT_1590_60XX_BIT = 0x2,
289  CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
290  SERIAL_DATA_IN_BIT = 0x80,
291  SERIAL_CLOCK_BIT = 0x100,
292  CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
293  CAL_GAIN_BIT = 0x800,
294 };
295 /* calibration sources for 6025 are:
296  * 0 : ground
297  * 1 : 10V
298  * 2 : 5V
299  * 3 : 0.5V
300  * 4 : 0.05V
301  * 5 : ground
302  * 6 : dac channel 0
303  * 7 : dac channel 1
304  */
305 static inline uint16_t adc_src_bits(unsigned int source)
306 {
307  return (source & 0xf) << 3;
308 };
309 
310 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
311 {
312  return (channel & 0x3) << 8;
313 };
314 
315 enum adc_queue_load_contents {
316  UNIP_BIT = 0x800, /* unipolar/bipolar bit */
317  ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
318  ADC_COMMON_BIT = 0x2000, /* non-referenced single-ended (common-mode input) */
319  QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
320  QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
321 };
322 static inline uint16_t adc_chan_bits(unsigned int channel)
323 {
324  return channel & 0x3f;
325 };
326 
327 enum dac_control0_contents {
328  DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
329  DAC_CYCLIC_STOP_BIT = 0x4000,
330  DAC_WAVEFORM_MODE_BIT = 0x100,
331  DAC_EXT_UPDATE_FALLING_BIT = 0x80,
332  DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
333  WAVEFORM_TRIG_MASK = 0x30,
334  WAVEFORM_TRIG_DISABLED_BITS = 0x0,
335  WAVEFORM_TRIG_SOFT_BITS = 0x10,
336  WAVEFORM_TRIG_EXT_BITS = 0x20,
337  WAVEFORM_TRIG_ADC1_BITS = 0x30,
338  WAVEFORM_TRIG_FALLING_BIT = 0x8,
339  WAVEFORM_GATE_LEVEL_BIT = 0x4,
340  WAVEFORM_GATE_ENABLE_BIT = 0x2,
341  WAVEFORM_GATE_SELECT_BIT = 0x1,
342 };
343 
344 enum dac_control1_contents {
345  DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
346  DAC1_EXT_REF_BIT = 0x200,
347  DAC0_EXT_REF_BIT = 0x100,
348  DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
349  DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
350  DAC_SW_GATE_BIT = 0x20,
351  DAC1_UNIPOLAR_BIT = 0x8,
352  DAC0_UNIPOLAR_BIT = 0x2,
353 };
354 
355 /* bit definitions for read-only registers */
356 enum hw_status_contents {
357  DAC_UNDERRUN_BIT = 0x1,
358  ADC_OVERRUN_BIT = 0x2,
359  DAC_ACTIVE_BIT = 0x4,
360  ADC_ACTIVE_BIT = 0x8,
361  DAC_INTR_PENDING_BIT = 0x10,
362  ADC_INTR_PENDING_BIT = 0x20,
363  DAC_DONE_BIT = 0x40,
364  ADC_DONE_BIT = 0x80,
365  EXT_INTR_PENDING_BIT = 0x100,
366  ADC_STOP_BIT = 0x200,
367 };
368 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
369 {
370  return (hw_status_bits >> 10) & 0x3;
371 };
372 
373 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
374 {
375  return (prepost_bits >> 6) & 0x3;
376 }
377 
378 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
379 {
380  return (prepost_bits >> 12) & 0x3;
381 }
382 
383 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
384 {
385  return (prepost_bits >> 14) & 0x3;
386 }
387 
388 /* I2C addresses for 4020 */
389 enum i2c_addresses {
390  RANGE_CAL_I2C_ADDR = 0x20,
391  CALDAC0_I2C_ADDR = 0xc,
392  CALDAC1_I2C_ADDR = 0xd,
393 };
394 
395 enum range_cal_i2c_contents {
396  ADC_SRC_4020_MASK = 0x70, /* bits that set what source the adc converter measures */
397  BNC_TRIG_THRESHOLD_0V_BIT = 0x80, /* make bnc trig/ext clock threshold 0V instead of 2.5V */
398 };
399 static inline uint8_t adc_src_4020_bits(unsigned int source)
400 {
401  return (source << 4) & ADC_SRC_4020_MASK;
402 };
403 
404 static inline uint8_t attenuate_bit(unsigned int channel)
405 {
406  /* attenuate channel (+-5V input range) */
407  return 1 << (channel & 0x3);
408 };
409 
410 /* analog input ranges for 64xx boards */
411 static const struct comedi_lrange ai_ranges_64xx = {
412  8,
413  {
414  BIP_RANGE(10),
415  BIP_RANGE(5),
416  BIP_RANGE(2.5),
417  BIP_RANGE(1.25),
418  UNI_RANGE(10),
419  UNI_RANGE(5),
420  UNI_RANGE(2.5),
421  UNI_RANGE(1.25)
422  }
423 };
424 
425 /* analog input ranges for 60xx boards */
426 static const struct comedi_lrange ai_ranges_60xx = {
427  4,
428  {
429  BIP_RANGE(10),
430  BIP_RANGE(5),
431  BIP_RANGE(0.5),
432  BIP_RANGE(0.05),
433  }
434 };
435 
436 /* analog input ranges for 6030, etc boards */
437 static const struct comedi_lrange ai_ranges_6030 = {
438  14,
439  {
440  BIP_RANGE(10),
441  BIP_RANGE(5),
442  BIP_RANGE(2),
443  BIP_RANGE(1),
444  BIP_RANGE(0.5),
445  BIP_RANGE(0.2),
446  BIP_RANGE(0.1),
447  UNI_RANGE(10),
448  UNI_RANGE(5),
449  UNI_RANGE(2),
450  UNI_RANGE(1),
451  UNI_RANGE(0.5),
452  UNI_RANGE(0.2),
453  UNI_RANGE(0.1),
454  }
455 };
456 
457 /* analog input ranges for 6052, etc boards */
458 static const struct comedi_lrange ai_ranges_6052 = {
459  15,
460  {
461  BIP_RANGE(10),
462  BIP_RANGE(5),
463  BIP_RANGE(2.5),
464  BIP_RANGE(1),
465  BIP_RANGE(0.5),
466  BIP_RANGE(0.25),
467  BIP_RANGE(0.1),
468  BIP_RANGE(0.05),
469  UNI_RANGE(10),
470  UNI_RANGE(5),
471  UNI_RANGE(2),
472  UNI_RANGE(1),
473  UNI_RANGE(0.5),
474  UNI_RANGE(0.2),
475  UNI_RANGE(0.1),
476  }
477 };
478 
479 /* analog input ranges for 4020 board */
480 static const struct comedi_lrange ai_ranges_4020 = {
481  2,
482  {
483  BIP_RANGE(5),
484  BIP_RANGE(1),
485  }
486 };
487 
488 /* analog output ranges */
489 static const struct comedi_lrange ao_ranges_64xx = {
490  4,
491  {
492  BIP_RANGE(5),
493  BIP_RANGE(10),
494  UNI_RANGE(5),
495  UNI_RANGE(10),
496  }
497 };
498 
499 static const int ao_range_code_64xx[] = {
500  0x0,
501  0x1,
502  0x2,
503  0x3,
504 };
505 
506 static const struct comedi_lrange ao_ranges_60xx = {
507  1,
508  {
509  BIP_RANGE(10),
510  }
511 };
512 
513 static const int ao_range_code_60xx[] = {
514  0x0,
515 };
516 
517 static const struct comedi_lrange ao_ranges_6030 = {
518  2,
519  {
520  BIP_RANGE(10),
521  UNI_RANGE(10),
522  }
523 };
524 
525 static const int ao_range_code_6030[] = {
526  0x0,
527  0x2,
528 };
529 
530 static const struct comedi_lrange ao_ranges_4020 = {
531  2,
532  {
533  BIP_RANGE(5),
534  BIP_RANGE(10),
535  }
536 };
537 
538 static const int ao_range_code_4020[] = {
539  0x1,
540  0x0,
541 };
542 
543 enum register_layout {
544  LAYOUT_60XX,
545  LAYOUT_64XX,
546  LAYOUT_4020,
547 };
548 
549 struct hw_fifo_info {
550  unsigned int num_segments;
551  unsigned int max_segment_length;
552  unsigned int sample_packing_ratio;
553  uint16_t fifo_size_reg_mask;
554 };
555 
556 struct pcidas64_board {
557  const char *name;
558  int device_id; /* pci device id */
559  int ai_se_chans; /* number of ai inputs in single-ended mode */
560  int ai_bits; /* analog input resolution */
561  int ai_speed; /* fastest conversion period in ns */
562  const struct comedi_lrange *ai_range_table;
563  int ao_nchan; /* number of analog out channels */
564  int ao_bits; /* analog output resolution */
565  int ao_scan_speed; /* analog output speed (for a scan, not conversion) */
566  const struct comedi_lrange *ao_range_table;
567  const int *ao_range_code;
568  const struct hw_fifo_info *const ai_fifo;
569  enum register_layout layout; /* different board families have slightly different registers */
570  unsigned has_8255:1;
571 };
572 
573 static const struct hw_fifo_info ai_fifo_4020 = {
574  .num_segments = 2,
575  .max_segment_length = 0x8000,
576  .sample_packing_ratio = 2,
577  .fifo_size_reg_mask = 0x7f,
578 };
579 
580 static const struct hw_fifo_info ai_fifo_64xx = {
581  .num_segments = 4,
582  .max_segment_length = 0x800,
583  .sample_packing_ratio = 1,
584  .fifo_size_reg_mask = 0x3f,
585 };
586 
587 static const struct hw_fifo_info ai_fifo_60xx = {
588  .num_segments = 4,
589  .max_segment_length = 0x800,
590  .sample_packing_ratio = 1,
591  .fifo_size_reg_mask = 0x7f,
592 };
593 
594 /* maximum number of dma transfers we will chain together into a ring
595  * (and the maximum number of dma buffers we maintain) */
596 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
597 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
598 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
599 static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board)
600 {
601  if (board->layout == LAYOUT_4020)
602  return MAX_AI_DMA_RING_COUNT;
603  else
604  return MIN_AI_DMA_RING_COUNT;
605 }
606 
607 static const int bytes_in_sample = 2;
608 
609 static const struct pcidas64_board pcidas64_boards[] = {
610  {
611  .name = "pci-das6402/16",
612  .device_id = 0x1d,
613  .ai_se_chans = 64,
614  .ai_bits = 16,
615  .ai_speed = 5000,
616  .ao_nchan = 2,
617  .ao_bits = 16,
618  .ao_scan_speed = 10000,
619  .layout = LAYOUT_64XX,
620  .ai_range_table = &ai_ranges_64xx,
621  .ao_range_table = &ao_ranges_64xx,
622  .ao_range_code = ao_range_code_64xx,
623  .ai_fifo = &ai_fifo_64xx,
624  .has_8255 = 1,
625  },
626  {
627  .name = "pci-das6402/12", /* XXX check */
628  .device_id = 0x1e,
629  .ai_se_chans = 64,
630  .ai_bits = 12,
631  .ai_speed = 5000,
632  .ao_nchan = 2,
633  .ao_bits = 12,
634  .ao_scan_speed = 10000,
635  .layout = LAYOUT_64XX,
636  .ai_range_table = &ai_ranges_64xx,
637  .ao_range_table = &ao_ranges_64xx,
638  .ao_range_code = ao_range_code_64xx,
639  .ai_fifo = &ai_fifo_64xx,
640  .has_8255 = 1,
641  },
642  {
643  .name = "pci-das64/m1/16",
644  .device_id = 0x35,
645  .ai_se_chans = 64,
646  .ai_bits = 16,
647  .ai_speed = 1000,
648  .ao_nchan = 2,
649  .ao_bits = 16,
650  .ao_scan_speed = 10000,
651  .layout = LAYOUT_64XX,
652  .ai_range_table = &ai_ranges_64xx,
653  .ao_range_table = &ao_ranges_64xx,
654  .ao_range_code = ao_range_code_64xx,
655  .ai_fifo = &ai_fifo_64xx,
656  .has_8255 = 1,
657  },
658  {
659  .name = "pci-das64/m2/16",
660  .device_id = 0x36,
661  .ai_se_chans = 64,
662  .ai_bits = 16,
663  .ai_speed = 500,
664  .ao_nchan = 2,
665  .ao_bits = 16,
666  .ao_scan_speed = 10000,
667  .layout = LAYOUT_64XX,
668  .ai_range_table = &ai_ranges_64xx,
669  .ao_range_table = &ao_ranges_64xx,
670  .ao_range_code = ao_range_code_64xx,
671  .ai_fifo = &ai_fifo_64xx,
672  .has_8255 = 1,
673  },
674  {
675  .name = "pci-das64/m3/16",
676  .device_id = 0x37,
677  .ai_se_chans = 64,
678  .ai_bits = 16,
679  .ai_speed = 333,
680  .ao_nchan = 2,
681  .ao_bits = 16,
682  .ao_scan_speed = 10000,
683  .layout = LAYOUT_64XX,
684  .ai_range_table = &ai_ranges_64xx,
685  .ao_range_table = &ao_ranges_64xx,
686  .ao_range_code = ao_range_code_64xx,
687  .ai_fifo = &ai_fifo_64xx,
688  .has_8255 = 1,
689  },
690  {
691  .name = "pci-das6013",
692  .device_id = 0x78,
693  .ai_se_chans = 16,
694  .ai_bits = 16,
695  .ai_speed = 5000,
696  .ao_nchan = 0,
697  .ao_bits = 16,
698  .layout = LAYOUT_60XX,
699  .ai_range_table = &ai_ranges_60xx,
700  .ao_range_table = &ao_ranges_60xx,
701  .ao_range_code = ao_range_code_60xx,
702  .ai_fifo = &ai_fifo_60xx,
703  .has_8255 = 0,
704  },
705  {
706  .name = "pci-das6014",
707  .device_id = 0x79,
708  .ai_se_chans = 16,
709  .ai_bits = 16,
710  .ai_speed = 5000,
711  .ao_nchan = 2,
712  .ao_bits = 16,
713  .ao_scan_speed = 100000,
714  .layout = LAYOUT_60XX,
715  .ai_range_table = &ai_ranges_60xx,
716  .ao_range_table = &ao_ranges_60xx,
717  .ao_range_code = ao_range_code_60xx,
718  .ai_fifo = &ai_fifo_60xx,
719  .has_8255 = 0,
720  },
721  {
722  .name = "pci-das6023",
723  .device_id = 0x5d,
724  .ai_se_chans = 16,
725  .ai_bits = 12,
726  .ai_speed = 5000,
727  .ao_nchan = 0,
728  .ao_scan_speed = 100000,
729  .layout = LAYOUT_60XX,
730  .ai_range_table = &ai_ranges_60xx,
731  .ao_range_table = &ao_ranges_60xx,
732  .ao_range_code = ao_range_code_60xx,
733  .ai_fifo = &ai_fifo_60xx,
734  .has_8255 = 1,
735  },
736  {
737  .name = "pci-das6025",
738  .device_id = 0x5e,
739  .ai_se_chans = 16,
740  .ai_bits = 12,
741  .ai_speed = 5000,
742  .ao_nchan = 2,
743  .ao_bits = 12,
744  .ao_scan_speed = 100000,
745  .layout = LAYOUT_60XX,
746  .ai_range_table = &ai_ranges_60xx,
747  .ao_range_table = &ao_ranges_60xx,
748  .ao_range_code = ao_range_code_60xx,
749  .ai_fifo = &ai_fifo_60xx,
750  .has_8255 = 1,
751  },
752  {
753  .name = "pci-das6030",
754  .device_id = 0x5f,
755  .ai_se_chans = 16,
756  .ai_bits = 16,
757  .ai_speed = 10000,
758  .ao_nchan = 2,
759  .ao_bits = 16,
760  .ao_scan_speed = 10000,
761  .layout = LAYOUT_60XX,
762  .ai_range_table = &ai_ranges_6030,
763  .ao_range_table = &ao_ranges_6030,
764  .ao_range_code = ao_range_code_6030,
765  .ai_fifo = &ai_fifo_60xx,
766  .has_8255 = 0,
767  },
768  {
769  .name = "pci-das6031",
770  .device_id = 0x60,
771  .ai_se_chans = 64,
772  .ai_bits = 16,
773  .ai_speed = 10000,
774  .ao_nchan = 2,
775  .ao_bits = 16,
776  .ao_scan_speed = 10000,
777  .layout = LAYOUT_60XX,
778  .ai_range_table = &ai_ranges_6030,
779  .ao_range_table = &ao_ranges_6030,
780  .ao_range_code = ao_range_code_6030,
781  .ai_fifo = &ai_fifo_60xx,
782  .has_8255 = 0,
783  },
784  {
785  .name = "pci-das6032",
786  .device_id = 0x61,
787  .ai_se_chans = 16,
788  .ai_bits = 16,
789  .ai_speed = 10000,
790  .ao_nchan = 0,
791  .layout = LAYOUT_60XX,
792  .ai_range_table = &ai_ranges_6030,
793  .ai_fifo = &ai_fifo_60xx,
794  .has_8255 = 0,
795  },
796  {
797  .name = "pci-das6033",
798  .device_id = 0x62,
799  .ai_se_chans = 64,
800  .ai_bits = 16,
801  .ai_speed = 10000,
802  .ao_nchan = 0,
803  .layout = LAYOUT_60XX,
804  .ai_range_table = &ai_ranges_6030,
805  .ai_fifo = &ai_fifo_60xx,
806  .has_8255 = 0,
807  },
808  {
809  .name = "pci-das6034",
810  .device_id = 0x63,
811  .ai_se_chans = 16,
812  .ai_bits = 16,
813  .ai_speed = 5000,
814  .ao_nchan = 0,
815  .ao_scan_speed = 0,
816  .layout = LAYOUT_60XX,
817  .ai_range_table = &ai_ranges_60xx,
818  .ai_fifo = &ai_fifo_60xx,
819  .has_8255 = 0,
820  },
821  {
822  .name = "pci-das6035",
823  .device_id = 0x64,
824  .ai_se_chans = 16,
825  .ai_bits = 16,
826  .ai_speed = 5000,
827  .ao_nchan = 2,
828  .ao_bits = 12,
829  .ao_scan_speed = 100000,
830  .layout = LAYOUT_60XX,
831  .ai_range_table = &ai_ranges_60xx,
832  .ao_range_table = &ao_ranges_60xx,
833  .ao_range_code = ao_range_code_60xx,
834  .ai_fifo = &ai_fifo_60xx,
835  .has_8255 = 0,
836  },
837  {
838  .name = "pci-das6036",
839  .device_id = 0x6f,
840  .ai_se_chans = 16,
841  .ai_bits = 16,
842  .ai_speed = 5000,
843  .ao_nchan = 2,
844  .ao_bits = 16,
845  .ao_scan_speed = 100000,
846  .layout = LAYOUT_60XX,
847  .ai_range_table = &ai_ranges_60xx,
848  .ao_range_table = &ao_ranges_60xx,
849  .ao_range_code = ao_range_code_60xx,
850  .ai_fifo = &ai_fifo_60xx,
851  .has_8255 = 0,
852  },
853  {
854  .name = "pci-das6040",
855  .device_id = 0x65,
856  .ai_se_chans = 16,
857  .ai_bits = 12,
858  .ai_speed = 2000,
859  .ao_nchan = 2,
860  .ao_bits = 12,
861  .ao_scan_speed = 1000,
862  .layout = LAYOUT_60XX,
863  .ai_range_table = &ai_ranges_6052,
864  .ao_range_table = &ao_ranges_6030,
865  .ao_range_code = ao_range_code_6030,
866  .ai_fifo = &ai_fifo_60xx,
867  .has_8255 = 0,
868  },
869  {
870  .name = "pci-das6052",
871  .device_id = 0x66,
872  .ai_se_chans = 16,
873  .ai_bits = 16,
874  .ai_speed = 3333,
875  .ao_nchan = 2,
876  .ao_bits = 16,
877  .ao_scan_speed = 3333,
878  .layout = LAYOUT_60XX,
879  .ai_range_table = &ai_ranges_6052,
880  .ao_range_table = &ao_ranges_6030,
881  .ao_range_code = ao_range_code_6030,
882  .ai_fifo = &ai_fifo_60xx,
883  .has_8255 = 0,
884  },
885  {
886  .name = "pci-das6070",
887  .device_id = 0x67,
888  .ai_se_chans = 16,
889  .ai_bits = 12,
890  .ai_speed = 800,
891  .ao_nchan = 2,
892  .ao_bits = 12,
893  .ao_scan_speed = 1000,
894  .layout = LAYOUT_60XX,
895  .ai_range_table = &ai_ranges_6052,
896  .ao_range_table = &ao_ranges_6030,
897  .ao_range_code = ao_range_code_6030,
898  .ai_fifo = &ai_fifo_60xx,
899  .has_8255 = 0,
900  },
901  {
902  .name = "pci-das6071",
903  .device_id = 0x68,
904  .ai_se_chans = 64,
905  .ai_bits = 12,
906  .ai_speed = 800,
907  .ao_nchan = 2,
908  .ao_bits = 12,
909  .ao_scan_speed = 1000,
910  .layout = LAYOUT_60XX,
911  .ai_range_table = &ai_ranges_6052,
912  .ao_range_table = &ao_ranges_6030,
913  .ao_range_code = ao_range_code_6030,
914  .ai_fifo = &ai_fifo_60xx,
915  .has_8255 = 0,
916  },
917  {
918  .name = "pci-das4020/12",
919  .device_id = 0x52,
920  .ai_se_chans = 4,
921  .ai_bits = 12,
922  .ai_speed = 50,
923  .ao_bits = 12,
924  .ao_nchan = 2,
925  .ao_scan_speed = 0, /* no hardware pacing on ao */
926  .layout = LAYOUT_4020,
927  .ai_range_table = &ai_ranges_4020,
928  .ao_range_table = &ao_ranges_4020,
929  .ao_range_code = ao_range_code_4020,
930  .ai_fifo = &ai_fifo_4020,
931  .has_8255 = 1,
932  },
933 #if 0
934  {
935  .name = "pci-das6402/16/jr",
936  .device_id = 0 /* XXX, */
937  .ai_se_chans = 64,
938  .ai_bits = 16,
939  .ai_speed = 5000,
940  .ao_nchan = 0,
941  .ao_scan_speed = 10000,
942  .layout = LAYOUT_64XX,
943  .ai_range_table = &ai_ranges_64xx,
944  .ai_fifo = ai_fifo_64xx,
945  .has_8255 = 1,
946  },
947  {
948  .name = "pci-das64/m1/16/jr",
949  .device_id = 0 /* XXX, */
950  .ai_se_chans = 64,
951  .ai_bits = 16,
952  .ai_speed = 1000,
953  .ao_nchan = 0,
954  .ao_scan_speed = 10000,
955  .layout = LAYOUT_64XX,
956  .ai_range_table = &ai_ranges_64xx,
957  .ai_fifo = ai_fifo_64xx,
958  .has_8255 = 1,
959  },
960  {
961  .name = "pci-das64/m2/16/jr",
962  .device_id = 0 /* XXX, */
963  .ai_se_chans = 64,
964  .ai_bits = 16,
965  .ai_speed = 500,
966  .ao_nchan = 0,
967  .ao_scan_speed = 10000,
968  .layout = LAYOUT_64XX,
969  .ai_range_table = &ai_ranges_64xx,
970  .ai_fifo = ai_fifo_64xx,
971  .has_8255 = 1,
972  },
973  {
974  .name = "pci-das64/m3/16/jr",
975  .device_id = 0 /* XXX, */
976  .ai_se_chans = 64,
977  .ai_bits = 16,
978  .ai_speed = 333,
979  .ao_nchan = 0,
980  .ao_scan_speed = 10000,
981  .layout = LAYOUT_64XX,
982  .ai_range_table = &ai_ranges_64xx,
983  .ai_fifo = ai_fifo_64xx,
984  .has_8255 = 1,
985  },
986  {
987  .name = "pci-das64/m1/14",
988  .device_id = 0, /* XXX */
989  .ai_se_chans = 64,
990  .ai_bits = 14,
991  .ai_speed = 1000,
992  .ao_nchan = 2,
993  .ao_scan_speed = 10000,
994  .layout = LAYOUT_64XX,
995  .ai_range_table = &ai_ranges_64xx,
996  .ai_fifo = ai_fifo_64xx,
997  .has_8255 = 1,
998  },
999  {
1000  .name = "pci-das64/m2/14",
1001  .device_id = 0, /* XXX */
1002  .ai_se_chans = 64,
1003  .ai_bits = 14,
1004  .ai_speed = 500,
1005  .ao_nchan = 2,
1006  .ao_scan_speed = 10000,
1007  .layout = LAYOUT_64XX,
1008  .ai_range_table = &ai_ranges_64xx,
1009  .ai_fifo = ai_fifo_64xx,
1010  .has_8255 = 1,
1011  },
1012  {
1013  .name = "pci-das64/m3/14",
1014  .device_id = 0, /* XXX */
1015  .ai_se_chans = 64,
1016  .ai_bits = 14,
1017  .ai_speed = 333,
1018  .ao_nchan = 2,
1019  .ao_scan_speed = 10000,
1020  .layout = LAYOUT_64XX,
1021  .ai_range_table = &ai_ranges_64xx,
1022  .ai_fifo = ai_fifo_64xx,
1023  .has_8255 = 1,
1024  },
1025 #endif
1026 };
1027 
1028 static inline struct pcidas64_board *board(const struct comedi_device *dev)
1029 {
1030  return (struct pcidas64_board *)dev->board_ptr;
1031 }
1032 
1033 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1034  int use_differential)
1035 {
1036  if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1037  (board(dev)->layout == LAYOUT_60XX && use_differential))
1038  return ADC_SE_DIFF_BIT;
1039  else
1040  return 0;
1041 };
1042 
1043 struct ext_clock_info {
1044  unsigned int divisor; /* master clock divisor to use for scans with external master clock */
1045  unsigned int chanspec; /* chanspec for master clock input when used as scan begin src */
1046 };
1047 
1048 /* this structure is for data unique to this hardware driver. */
1049 struct pcidas64_private {
1050  /* base addresses (physical) */
1051  resource_size_t plx9080_phys_iobase;
1052  resource_size_t main_phys_iobase;
1053  resource_size_t dio_counter_phys_iobase;
1054  /* base addresses (ioremapped) */
1055  void __iomem *plx9080_iobase;
1056  void __iomem *main_iobase;
1057  void __iomem *dio_counter_iobase;
1058  /* local address (used by dma controller) */
1059  uint32_t local0_iobase;
1060  uint32_t local1_iobase;
1061  volatile unsigned int ai_count; /* number of analog input samples remaining */
1062  uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; /* dma buffers for analog input */
1063  dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; /* physical addresses of ai dma buffers */
1064  struct plx_dma_desc *ai_dma_desc; /* array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1065  dma_addr_t ai_dma_desc_bus_addr; /* physical address of ai dma descriptor array */
1066  volatile unsigned int ai_dma_index; /* index of the ai dma descriptor/buffer that is currently being used */
1067  uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /* dma buffers for analog output */
1068  dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; /* physical addresses of ao dma buffers */
1069  struct plx_dma_desc *ao_dma_desc;
1070  dma_addr_t ao_dma_desc_bus_addr;
1071  volatile unsigned int ao_dma_index; /* keeps track of buffer where the next ao sample should go */
1072  volatile unsigned long ao_count; /* number of analog output samples remaining */
1073  volatile unsigned int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */
1074  unsigned int hw_revision; /* stc chip hardware revision number */
1075  volatile unsigned int intr_enable_bits; /* last bits sent to INTR_ENABLE_REG register */
1076  volatile uint16_t adc_control1_bits; /* last bits sent to ADC_CONTROL1_REG register */
1077  volatile uint16_t fifo_size_bits; /* last bits sent to FIFO_SIZE_REG register */
1078  volatile uint16_t hw_config_bits; /* last bits sent to HW_CONFIG_REG register */
1079  volatile uint16_t dac_control1_bits;
1080  volatile uint32_t plx_control_bits; /* last bits written to plx9080 control register */
1081  volatile uint32_t plx_intcsr_bits; /* last bits written to plx interrupt control and status register */
1082  volatile int calibration_source; /* index of calibration source readable through ai ch0 */
1083  volatile uint8_t i2c_cal_range_bits; /* bits written to i2c calibration/range register */
1084  volatile unsigned int ext_trig_falling; /* configure digital triggers to trigger on falling edge */
1085  /* states of various devices stored to enable read-back */
1086  unsigned int ad8402_state[2];
1087  unsigned int caldac_state[8];
1088  volatile short ai_cmd_running;
1089  unsigned int ai_fifo_segment_length;
1090  struct ext_clock_info ext_clock;
1091  short ao_bounce_buffer[DAC_FIFO_SIZE];
1092 };
1093 
1094 /* inline function that makes it easier to
1095  * access the private structure.
1096  */
1097 static inline struct pcidas64_private *priv(struct comedi_device *dev)
1098 {
1099  return dev->private;
1100 }
1101 
1102 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1103  struct comedi_insn *insn, unsigned int *data);
1104 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1105  struct comedi_insn *insn, unsigned int *data);
1106 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1107  struct comedi_insn *insn, unsigned int *data);
1108 static int ao_readback_insn(struct comedi_device *dev,
1109  struct comedi_subdevice *s,
1110  struct comedi_insn *insn, unsigned int *data);
1111 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1112 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1113  struct comedi_cmd *cmd);
1114 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1115 static int ao_inttrig(struct comedi_device *dev,
1116  struct comedi_subdevice *subdev, unsigned int trig_num);
1117 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1118  struct comedi_cmd *cmd);
1119 static irqreturn_t handle_interrupt(int irq, void *d);
1120 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1121 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1122 static int dio_callback(int dir, int port, int data, unsigned long arg);
1123 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1124 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
1125  struct comedi_insn *insn, unsigned int *data);
1126 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1127  struct comedi_insn *insn, unsigned int *data);
1128 static int dio_60xx_config_insn(struct comedi_device *dev,
1129  struct comedi_subdevice *s,
1130  struct comedi_insn *insn, unsigned int *data);
1131 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1132  struct comedi_insn *insn, unsigned int *data);
1133 static int calib_read_insn(struct comedi_device *dev,
1134  struct comedi_subdevice *s, struct comedi_insn *insn,
1135  unsigned int *data);
1136 static int calib_write_insn(struct comedi_device *dev,
1137  struct comedi_subdevice *s,
1138  struct comedi_insn *insn, unsigned int *data);
1139 static int ad8402_read_insn(struct comedi_device *dev,
1140  struct comedi_subdevice *s,
1141  struct comedi_insn *insn, unsigned int *data);
1142 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
1143  unsigned int value);
1144 static int ad8402_write_insn(struct comedi_device *dev,
1145  struct comedi_subdevice *s,
1146  struct comedi_insn *insn, unsigned int *data);
1147 static int eeprom_read_insn(struct comedi_device *dev,
1148  struct comedi_subdevice *s,
1149  struct comedi_insn *insn, unsigned int *data);
1150 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
1151 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1152 static void i2c_write(struct comedi_device *dev, unsigned int address,
1153  const uint8_t *data, unsigned int length);
1154 static void caldac_write(struct comedi_device *dev, unsigned int channel,
1155  unsigned int value);
1156 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
1157  uint8_t value);
1158 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1159 static int caldac_i2c_write(struct comedi_device *dev,
1160  unsigned int caldac_channel, unsigned int value);
1161 static void abort_dma(struct comedi_device *dev, unsigned int channel);
1162 static void disable_plx_interrupts(struct comedi_device *dev);
1163 static int set_ai_fifo_size(struct comedi_device *dev,
1164  unsigned int num_samples);
1165 static unsigned int ai_fifo_size(struct comedi_device *dev);
1166 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1167  unsigned int num_entries);
1168 static void disable_ai_pacing(struct comedi_device *dev);
1169 static void disable_ai_interrupts(struct comedi_device *dev);
1170 static void enable_ai_interrupts(struct comedi_device *dev,
1171  const struct comedi_cmd *cmd);
1172 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1173 static void load_ao_dma(struct comedi_device *dev,
1174  const struct comedi_cmd *cmd);
1175 
1176 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1177  unsigned int range_index)
1178 {
1179  const struct comedi_krange *range =
1180  &board(dev)->ai_range_table->range[range_index];
1181  unsigned int bits = 0;
1182 
1183  switch (range->max) {
1184  case 10000000:
1185  bits = 0x000;
1186  break;
1187  case 5000000:
1188  bits = 0x100;
1189  break;
1190  case 2000000:
1191  case 2500000:
1192  bits = 0x200;
1193  break;
1194  case 1000000:
1195  case 1250000:
1196  bits = 0x300;
1197  break;
1198  case 500000:
1199  bits = 0x400;
1200  break;
1201  case 200000:
1202  case 250000:
1203  bits = 0x500;
1204  break;
1205  case 100000:
1206  bits = 0x600;
1207  break;
1208  case 50000:
1209  bits = 0x700;
1210  break;
1211  default:
1212  comedi_error(dev, "bug! in ai_range_bits_6xxx");
1213  break;
1214  }
1215  if (range->min == 0)
1216  bits += 0x900;
1217  return bits;
1218 }
1219 
1220 static unsigned int hw_revision(const struct comedi_device *dev,
1221  uint16_t hw_status_bits)
1222 {
1223  if (board(dev)->layout == LAYOUT_4020)
1224  return (hw_status_bits >> 13) & 0x7;
1225 
1226  return (hw_status_bits >> 12) & 0xf;
1227 }
1228 
1229 static void set_dac_range_bits(struct comedi_device *dev,
1230  volatile uint16_t *bits, unsigned int channel,
1231  unsigned int range)
1232 {
1233  unsigned int code = board(dev)->ao_range_code[range];
1234 
1235  if (channel > 1)
1236  comedi_error(dev, "bug! bad channel?");
1237  if (code & ~0x3)
1238  comedi_error(dev, "bug! bad range code?");
1239 
1240  *bits &= ~(0x3 << (2 * channel));
1241  *bits |= code << (2 * channel);
1242 };
1243 
1244 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1245 {
1246  return board->ao_nchan && board->layout != LAYOUT_4020;
1247 }
1248 
1249 /* initialize plx9080 chip */
1250 static void init_plx9080(struct comedi_device *dev)
1251 {
1252  uint32_t bits;
1253  void __iomem *plx_iobase = priv(dev)->plx9080_iobase;
1254 
1255  priv(dev)->plx_control_bits =
1256  readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
1257 
1258  /* plx9080 dump */
1259  DEBUG_PRINT(" plx interrupt status 0x%x\n",
1260  readl(plx_iobase + PLX_INTRCS_REG));
1261  DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1262  DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits);
1263  DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1264  readl(plx_iobase + PLX_MARB_REG));
1265  DEBUG_PRINT(" plx region0 reg 0x%x\n",
1266  readl(plx_iobase + PLX_REGION0_REG));
1267  DEBUG_PRINT(" plx region1 reg 0x%x\n",
1268  readl(plx_iobase + PLX_REGION1_REG));
1269 
1270  DEBUG_PRINT(" plx revision 0x%x\n",
1271  readl(plx_iobase + PLX_REVISION_REG));
1272  DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1273  readl(plx_iobase + PLX_DMA0_MODE_REG));
1274  DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1275  readl(plx_iobase + PLX_DMA1_MODE_REG));
1276  DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1277  readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1278  DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1279  readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1280  DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1281  readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1282  DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1283  readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1284  DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1285  readb(plx_iobase + PLX_DMA0_CS_REG));
1286  DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1287  readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1288  DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1289 
1290 #ifdef __BIG_ENDIAN
1291  bits = BIGEND_DMA0 | BIGEND_DMA1;
1292 #else
1293  bits = 0;
1294 #endif
1295  writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
1296 
1297  disable_plx_interrupts(dev);
1298 
1299  abort_dma(dev, 0);
1300  abort_dma(dev, 1);
1301 
1302  /* configure dma0 mode */
1303  bits = 0;
1304  /* enable ready input, not sure if this is necessary */
1305  bits |= PLX_DMA_EN_READYIN_BIT;
1306  /* enable bterm, not sure if this is necessary */
1307  bits |= PLX_EN_BTERM_BIT;
1308  /* enable dma chaining */
1309  bits |= PLX_EN_CHAIN_BIT;
1310  /* enable interrupt on dma done (probably don't need this, since chain never finishes) */
1311  bits |= PLX_EN_DMA_DONE_INTR_BIT;
1312  /* don't increment local address during transfers (we are transferring from a fixed fifo register) */
1313  bits |= PLX_LOCAL_ADDR_CONST_BIT;
1314  /* route dma interrupt to pci bus */
1315  bits |= PLX_DMA_INTR_PCI_BIT;
1316  /* enable demand mode */
1317  bits |= PLX_DEMAND_MODE_BIT;
1318  /* enable local burst mode */
1319  bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1320  /* 4020 uses 32 bit dma */
1321  if (board(dev)->layout == LAYOUT_4020) {
1322  bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1323  } else { /* localspace0 bus is 16 bits wide */
1324  bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1325  }
1326  writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1327  if (ao_cmd_is_supported(board(dev)))
1328  writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1329 
1330  /* enable interrupts on plx 9080 */
1331  priv(dev)->plx_intcsr_bits |=
1332  ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1333  ICS_DMA0_E | ICS_DMA1_E;
1334  writel(priv(dev)->plx_intcsr_bits,
1335  priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1336 }
1337 
1338 /* Allocate and initialize the subdevice structures.
1339  */
1340 static int setup_subdevices(struct comedi_device *dev)
1341 {
1342  struct comedi_subdevice *s;
1343  void __iomem *dio_8255_iobase;
1344  int i;
1345  int ret;
1346 
1347  ret = comedi_alloc_subdevices(dev, 10);
1348  if (ret)
1349  return ret;
1350 
1351  s = &dev->subdevices[0];
1352  /* analog input subdevice */
1353  dev->read_subdev = s;
1354  s->type = COMEDI_SUBD_AI;
1355  s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1356  if (board(dev)->layout == LAYOUT_60XX)
1357  s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1358  else if (board(dev)->layout == LAYOUT_64XX)
1359  s->subdev_flags |= SDF_DIFF;
1360  /* XXX Number of inputs in differential mode is ignored */
1361  s->n_chan = board(dev)->ai_se_chans;
1362  s->len_chanlist = 0x2000;
1363  s->maxdata = (1 << board(dev)->ai_bits) - 1;
1364  s->range_table = board(dev)->ai_range_table;
1365  s->insn_read = ai_rinsn;
1366  s->insn_config = ai_config_insn;
1367  s->do_cmd = ai_cmd;
1368  s->do_cmdtest = ai_cmdtest;
1369  s->cancel = ai_cancel;
1370  if (board(dev)->layout == LAYOUT_4020) {
1371  uint8_t data;
1372  /* set adc to read from inputs (not internal calibration sources) */
1373  priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4);
1374  /* set channels to +-5 volt input ranges */
1375  for (i = 0; i < s->n_chan; i++)
1376  priv(dev)->i2c_cal_range_bits |= attenuate_bit(i);
1377  data = priv(dev)->i2c_cal_range_bits;
1378  i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1379  }
1380 
1381  /* analog output subdevice */
1382  s = &dev->subdevices[1];
1383  if (board(dev)->ao_nchan) {
1384  s->type = COMEDI_SUBD_AO;
1385  s->subdev_flags =
1386  SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1387  s->n_chan = board(dev)->ao_nchan;
1388  s->maxdata = (1 << board(dev)->ao_bits) - 1;
1389  s->range_table = board(dev)->ao_range_table;
1390  s->insn_read = ao_readback_insn;
1391  s->insn_write = ao_winsn;
1392  if (ao_cmd_is_supported(board(dev))) {
1393  dev->write_subdev = s;
1394  s->do_cmdtest = ao_cmdtest;
1395  s->do_cmd = ao_cmd;
1396  s->len_chanlist = board(dev)->ao_nchan;
1397  s->cancel = ao_cancel;
1398  }
1399  } else {
1400  s->type = COMEDI_SUBD_UNUSED;
1401  }
1402 
1403  /* digital input */
1404  s = &dev->subdevices[2];
1405  if (board(dev)->layout == LAYOUT_64XX) {
1406  s->type = COMEDI_SUBD_DI;
1407  s->subdev_flags = SDF_READABLE;
1408  s->n_chan = 4;
1409  s->maxdata = 1;
1410  s->range_table = &range_digital;
1411  s->insn_bits = di_rbits;
1412  } else
1413  s->type = COMEDI_SUBD_UNUSED;
1414 
1415  /* digital output */
1416  if (board(dev)->layout == LAYOUT_64XX) {
1417  s = &dev->subdevices[3];
1418  s->type = COMEDI_SUBD_DO;
1419  s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1420  s->n_chan = 4;
1421  s->maxdata = 1;
1422  s->range_table = &range_digital;
1423  s->insn_bits = do_wbits;
1424  } else
1425  s->type = COMEDI_SUBD_UNUSED;
1426 
1427  /* 8255 */
1428  s = &dev->subdevices[4];
1429  if (board(dev)->has_8255) {
1430  if (board(dev)->layout == LAYOUT_4020) {
1431  dio_8255_iobase =
1432  priv(dev)->main_iobase + I8255_4020_REG;
1433  subdev_8255_init(dev, s, dio_callback_4020,
1434  (unsigned long)dio_8255_iobase);
1435  } else {
1436  dio_8255_iobase =
1437  priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
1438  subdev_8255_init(dev, s, dio_callback,
1439  (unsigned long)dio_8255_iobase);
1440  }
1441  } else
1442  s->type = COMEDI_SUBD_UNUSED;
1443 
1444  /* 8 channel dio for 60xx */
1445  s = &dev->subdevices[5];
1446  if (board(dev)->layout == LAYOUT_60XX) {
1447  s->type = COMEDI_SUBD_DIO;
1448  s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1449  s->n_chan = 8;
1450  s->maxdata = 1;
1451  s->range_table = &range_digital;
1452  s->insn_config = dio_60xx_config_insn;
1453  s->insn_bits = dio_60xx_wbits;
1454  } else
1455  s->type = COMEDI_SUBD_UNUSED;
1456 
1457  /* caldac */
1458  s = &dev->subdevices[6];
1459  s->type = COMEDI_SUBD_CALIB;
1460  s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1461  s->n_chan = 8;
1462  if (board(dev)->layout == LAYOUT_4020)
1463  s->maxdata = 0xfff;
1464  else
1465  s->maxdata = 0xff;
1466  s->insn_read = calib_read_insn;
1467  s->insn_write = calib_write_insn;
1468  for (i = 0; i < s->n_chan; i++)
1469  caldac_write(dev, i, s->maxdata / 2);
1470 
1471  /* 2 channel ad8402 potentiometer */
1472  s = &dev->subdevices[7];
1473  if (board(dev)->layout == LAYOUT_64XX) {
1474  s->type = COMEDI_SUBD_CALIB;
1475  s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1476  s->n_chan = 2;
1477  s->insn_read = ad8402_read_insn;
1478  s->insn_write = ad8402_write_insn;
1479  s->maxdata = 0xff;
1480  for (i = 0; i < s->n_chan; i++)
1481  ad8402_write(dev, i, s->maxdata / 2);
1482  } else
1483  s->type = COMEDI_SUBD_UNUSED;
1484 
1485  /* serial EEPROM, if present */
1486  s = &dev->subdevices[8];
1487  if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1488  s->type = COMEDI_SUBD_MEMORY;
1489  s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1490  s->n_chan = 128;
1491  s->maxdata = 0xffff;
1492  s->insn_read = eeprom_read_insn;
1493  } else
1494  s->type = COMEDI_SUBD_UNUSED;
1495 
1496  /* user counter subd XXX */
1497  s = &dev->subdevices[9];
1498  s->type = COMEDI_SUBD_UNUSED;
1499 
1500  return 0;
1501 }
1502 
1503 static void disable_plx_interrupts(struct comedi_device *dev)
1504 {
1505  priv(dev)->plx_intcsr_bits = 0;
1506  writel(priv(dev)->plx_intcsr_bits,
1507  priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1508 }
1509 
1510 static void init_stc_registers(struct comedi_device *dev)
1511 {
1512  uint16_t bits;
1513  unsigned long flags;
1514 
1515  spin_lock_irqsave(&dev->spinlock, flags);
1516 
1517  /* bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1518  if (1)
1519  priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1520  writew(priv(dev)->adc_control1_bits,
1521  priv(dev)->main_iobase + ADC_CONTROL1_REG);
1522 
1523  /* 6402/16 manual says this register must be initialized to 0xff? */
1524  writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1525 
1526  bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1527  if (board(dev)->layout == LAYOUT_4020)
1528  bits |= INTERNAL_CLOCK_4020_BITS;
1529  priv(dev)->hw_config_bits |= bits;
1530  writew(priv(dev)->hw_config_bits,
1531  priv(dev)->main_iobase + HW_CONFIG_REG);
1532 
1533  writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG);
1534  writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1535 
1536  spin_unlock_irqrestore(&dev->spinlock, flags);
1537 
1538  /* set fifos to maximum size */
1539  priv(dev)->fifo_size_bits |= DAC_FIFO_BITS;
1540  set_ai_fifo_segment_length(dev,
1541  board(dev)->ai_fifo->max_segment_length);
1542 
1543  priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1544  priv(dev)->intr_enable_bits = /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1545  EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1546  writew(priv(dev)->intr_enable_bits,
1547  priv(dev)->main_iobase + INTR_ENABLE_REG);
1548 
1549  disable_ai_pacing(dev);
1550 };
1551 
1552 static int alloc_and_init_dma_members(struct comedi_device *dev)
1553 {
1554  struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1555  int i;
1556 
1557  /* alocate pci dma buffers */
1558  for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1559  priv(dev)->ai_buffer[i] =
1560  pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1561  &priv(dev)->ai_buffer_bus_addr[i]);
1562  if (priv(dev)->ai_buffer[i] == NULL)
1563  return -ENOMEM;
1564 
1565  }
1566  for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1567  if (ao_cmd_is_supported(board(dev))) {
1568  priv(dev)->ao_buffer[i] =
1569  pci_alloc_consistent(pcidev,
1570  DMA_BUFFER_SIZE,
1571  &priv(dev)->
1572  ao_buffer_bus_addr[i]);
1573  if (priv(dev)->ao_buffer[i] == NULL)
1574  return -ENOMEM;
1575 
1576  }
1577  }
1578  /* allocate dma descriptors */
1579  priv(dev)->ai_dma_desc =
1580  pci_alloc_consistent(pcidev,
1581  sizeof(struct plx_dma_desc) *
1582  ai_dma_ring_count(board(dev)),
1583  &priv(dev)->ai_dma_desc_bus_addr);
1584  if (priv(dev)->ai_dma_desc == NULL)
1585  return -ENOMEM;
1586 
1587  DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1588  priv(dev)->ai_dma_desc_bus_addr);
1589  if (ao_cmd_is_supported(board(dev))) {
1590  priv(dev)->ao_dma_desc =
1591  pci_alloc_consistent(pcidev,
1592  sizeof(struct plx_dma_desc) *
1593  AO_DMA_RING_COUNT,
1594  &priv(dev)->ao_dma_desc_bus_addr);
1595  if (priv(dev)->ao_dma_desc == NULL)
1596  return -ENOMEM;
1597 
1598  DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1599  priv(dev)->ao_dma_desc_bus_addr);
1600  }
1601  /* initialize dma descriptors */
1602  for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1603  priv(dev)->ai_dma_desc[i].pci_start_addr =
1604  cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]);
1605  if (board(dev)->layout == LAYOUT_4020)
1606  priv(dev)->ai_dma_desc[i].local_start_addr =
1607  cpu_to_le32(priv(dev)->local1_iobase +
1608  ADC_FIFO_REG);
1609  else
1610  priv(dev)->ai_dma_desc[i].local_start_addr =
1611  cpu_to_le32(priv(dev)->local0_iobase +
1612  ADC_FIFO_REG);
1613  priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1614  priv(dev)->ai_dma_desc[i].next =
1615  cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i +
1616  1) %
1617  ai_dma_ring_count
1618  (board
1619  (dev))) *
1620  sizeof(priv(dev)->ai_dma_desc[0])) |
1621  PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1622  PLX_XFER_LOCAL_TO_PCI);
1623  }
1624  if (ao_cmd_is_supported(board(dev))) {
1625  for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1626  priv(dev)->ao_dma_desc[i].pci_start_addr =
1627  cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]);
1628  priv(dev)->ao_dma_desc[i].local_start_addr =
1629  cpu_to_le32(priv(dev)->local0_iobase +
1630  DAC_FIFO_REG);
1631  priv(dev)->ao_dma_desc[i].transfer_size =
1632  cpu_to_le32(0);
1633  priv(dev)->ao_dma_desc[i].next =
1634  cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr +
1635  ((i + 1) % (AO_DMA_RING_COUNT)) *
1636  sizeof(priv(dev)->ao_dma_desc[0])) |
1637  PLX_DESC_IN_PCI_BIT |
1638  PLX_INTR_TERM_COUNT);
1639  }
1640  }
1641  return 0;
1642 }
1643 
1644 static inline void warn_external_queue(struct comedi_device *dev)
1645 {
1646  comedi_error(dev,
1647  "AO command and AI external channel queue cannot be used simultaneously.");
1648  comedi_error(dev,
1649  "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1650 }
1651 
1652 static struct pci_dev *cb_pcidas64_find_pci_dev(struct comedi_device *dev,
1653  struct comedi_devconfig *it)
1654 {
1655  struct pci_dev *pcidev = NULL;
1656  int bus = it->options[0];
1657  int slot = it->options[1];
1658  int i;
1659 
1660  for_each_pci_dev(pcidev) {
1661  if (bus || slot) {
1662  if (bus != pcidev->bus->number ||
1663  slot != PCI_SLOT(pcidev->devfn))
1664  continue;
1665  }
1666  if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS)
1667  continue;
1668 
1669  for (i = 0; i < ARRAY_SIZE(pcidas64_boards); i++) {
1670  if (pcidas64_boards[i].device_id != pcidev->device)
1671  continue;
1672  dev->board_ptr = pcidas64_boards + i;
1673  return pcidev;
1674  }
1675  }
1676  dev_err(dev->class_dev,
1677  "No supported board found! (req. bus %d, slot %d)\n",
1678  bus, slot);
1679  return NULL;
1680 }
1681 
1682 /*
1683  * Attach is called by the Comedi core to configure the driver
1684  * for a particular board.
1685  */
1686 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1687 {
1688  struct pci_dev *pcidev;
1689  uint32_t local_range, local_decode;
1690  int retval;
1691 
1692 /*
1693  * Allocate the private structure area.
1694  */
1695  if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0)
1696  return -ENOMEM;
1697 
1698  pcidev = cb_pcidas64_find_pci_dev(dev, it);
1699  if (!pcidev)
1700  return -EIO;
1701  comedi_set_hw_dev(dev, &pcidev->dev);
1702 
1703  if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
1704  dev_warn(dev->class_dev,
1705  "failed to enable PCI device and request regions\n");
1706  return -EIO;
1707  }
1708  pci_set_master(pcidev);
1709 
1710  /* Initialize dev->board_name */
1711  dev->board_name = board(dev)->name;
1712 
1713  dev->iobase = pci_resource_start(pcidev, MAIN_BADDRINDEX);
1714 
1715  priv(dev)->plx9080_phys_iobase =
1716  pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1717  priv(dev)->main_phys_iobase = dev->iobase;
1718  priv(dev)->dio_counter_phys_iobase =
1719  pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1720 
1721  /* remap, won't work with 2.0 kernels but who cares */
1722  priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
1723  pci_resource_len(pcidev,
1724  PLX9080_BADDRINDEX));
1725  priv(dev)->main_iobase =
1726  ioremap(priv(dev)->main_phys_iobase,
1727  pci_resource_len(pcidev, MAIN_BADDRINDEX));
1728  priv(dev)->dio_counter_iobase =
1729  ioremap(priv(dev)->dio_counter_phys_iobase,
1730  pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1731 
1732  if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase
1733  || !priv(dev)->dio_counter_iobase) {
1734  dev_warn(dev->class_dev, "failed to remap io memory\n");
1735  return -ENOMEM;
1736  }
1737 
1738  DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
1739  DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase);
1740  DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1741  priv(dev)->dio_counter_iobase);
1742 
1743  /* figure out what local addresses are */
1744  local_range =
1745  readl(priv(dev)->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1746  local_decode =
1747  readl(priv(dev)->plx9080_iobase +
1748  PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1749  priv(dev)->local0_iobase =
1750  ((uint32_t) priv(dev)->main_phys_iobase & ~local_range) |
1751  local_decode;
1752  local_range =
1753  readl(priv(dev)->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1754  local_decode =
1755  readl(priv(dev)->plx9080_iobase +
1756  PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1757  priv(dev)->local1_iobase =
1758  ((uint32_t) priv(dev)->dio_counter_phys_iobase & ~local_range) |
1759  local_decode;
1760 
1761  DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase);
1762  DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase);
1763 
1764  retval = alloc_and_init_dma_members(dev);
1765  if (retval < 0)
1766  return retval;
1767 
1768  priv(dev)->hw_revision =
1769  hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG));
1770  dev_dbg(dev->class_dev, "stc hardware revision %i\n",
1771  priv(dev)->hw_revision);
1772  init_plx9080(dev);
1773  init_stc_registers(dev);
1774  /* get irq */
1775  if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1776  "cb_pcidas64", dev)) {
1777  dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
1778  pcidev->irq);
1779  return -EINVAL;
1780  }
1781  dev->irq = pcidev->irq;
1782  dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
1783 
1784  retval = setup_subdevices(dev);
1785  if (retval < 0)
1786  return retval;
1787 
1788 
1789  return 0;
1790 }
1791 
1792 static void detach(struct comedi_device *dev)
1793 {
1794  struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1795  unsigned int i;
1796 
1797  if (dev->irq)
1798  free_irq(dev->irq, dev);
1799  if (priv(dev)) {
1800  if (pcidev) {
1801  if (priv(dev)->plx9080_iobase) {
1802  disable_plx_interrupts(dev);
1803  iounmap(priv(dev)->plx9080_iobase);
1804  }
1805  if (priv(dev)->main_iobase)
1806  iounmap(priv(dev)->main_iobase);
1807  if (priv(dev)->dio_counter_iobase)
1808  iounmap(priv(dev)->dio_counter_iobase);
1809  /* free pci dma buffers */
1810  for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1811  if (priv(dev)->ai_buffer[i])
1812  pci_free_consistent(pcidev,
1813  DMA_BUFFER_SIZE,
1814  priv(dev)->
1815  ai_buffer[i],
1816  priv
1817  (dev)->ai_buffer_bus_addr
1818  [i]);
1819  }
1820  for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1821  if (priv(dev)->ao_buffer[i])
1822  pci_free_consistent(pcidev,
1823  DMA_BUFFER_SIZE,
1824  priv(dev)->
1825  ao_buffer[i],
1826  priv
1827  (dev)->ao_buffer_bus_addr
1828  [i]);
1829  }
1830  /* free dma descriptors */
1831  if (priv(dev)->ai_dma_desc)
1832  pci_free_consistent(pcidev,
1833  sizeof(struct plx_dma_desc)
1834  *
1835  ai_dma_ring_count(board
1836  (dev)),
1837  priv(dev)->ai_dma_desc,
1838  priv(dev)->
1839  ai_dma_desc_bus_addr);
1840  if (priv(dev)->ao_dma_desc)
1841  pci_free_consistent(pcidev,
1842  sizeof(struct plx_dma_desc)
1843  * AO_DMA_RING_COUNT,
1844  priv(dev)->ao_dma_desc,
1845  priv(dev)->
1846  ao_dma_desc_bus_addr);
1847  }
1848  }
1849  if (dev->subdevices)
1850  subdev_8255_cleanup(dev, &dev->subdevices[4]);
1851  if (pcidev) {
1852  if (dev->iobase)
1853  comedi_pci_disable(pcidev);
1854 
1855  pci_dev_put(pcidev);
1856  }
1857 }
1858 
1859 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1860  struct comedi_insn *insn, unsigned int *data)
1861 {
1862  unsigned int bits = 0, n, i;
1863  unsigned int channel, range, aref;
1864  unsigned long flags;
1865  static const int timeout = 100;
1866 
1867  DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1868  channel = CR_CHAN(insn->chanspec);
1869  range = CR_RANGE(insn->chanspec);
1870  aref = CR_AREF(insn->chanspec);
1871 
1872  /* disable card's analog input interrupt sources and pacing */
1873  /* 4020 generates dac done interrupts even though they are disabled */
1874  disable_ai_pacing(dev);
1875 
1876  spin_lock_irqsave(&dev->spinlock, flags);
1877  if (insn->chanspec & CR_ALT_FILTER)
1878  priv(dev)->adc_control1_bits |= ADC_DITHER_BIT;
1879  else
1880  priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
1881  writew(priv(dev)->adc_control1_bits,
1882  priv(dev)->main_iobase + ADC_CONTROL1_REG);
1883  spin_unlock_irqrestore(&dev->spinlock, flags);
1884 
1885  if (board(dev)->layout != LAYOUT_4020) {
1886  /* use internal queue */
1887  priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
1888  writew(priv(dev)->hw_config_bits,
1889  priv(dev)->main_iobase + HW_CONFIG_REG);
1890 
1891  /* ALT_SOURCE is internal calibration reference */
1892  if (insn->chanspec & CR_ALT_SOURCE) {
1893  unsigned int cal_en_bit;
1894 
1895  DEBUG_PRINT("reading calibration source\n");
1896  if (board(dev)->layout == LAYOUT_60XX)
1897  cal_en_bit = CAL_EN_60XX_BIT;
1898  else
1899  cal_en_bit = CAL_EN_64XX_BIT;
1900  /* select internal reference source to connect to channel 0 */
1901  writew(cal_en_bit |
1902  adc_src_bits(priv(dev)->calibration_source),
1903  priv(dev)->main_iobase + CALIBRATION_REG);
1904  } else {
1905  /* make sure internal calibration source is turned off */
1906  writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1907  }
1908  /* load internal queue */
1909  bits = 0;
1910  /* set gain */
1911  bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1912  /* set single-ended / differential */
1913  bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1914  if (aref == AREF_COMMON)
1915  bits |= ADC_COMMON_BIT;
1916  bits |= adc_chan_bits(channel);
1917  /* set stop channel */
1918  writew(adc_chan_bits(channel),
1919  priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
1920  /* set start channel, and rest of settings */
1921  writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
1922  } else {
1923  uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits;
1924 
1925  priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1926  if (insn->chanspec & CR_ALT_SOURCE) {
1927  DEBUG_PRINT("reading calibration source\n");
1928  priv(dev)->i2c_cal_range_bits |=
1929  adc_src_4020_bits(priv(dev)->calibration_source);
1930  } else { /* select BNC inputs */
1931  priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
1932  }
1933  /* select range */
1934  if (range == 0)
1935  priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel);
1936  else
1937  priv(dev)->i2c_cal_range_bits &=
1938  ~attenuate_bit(channel);
1939  /* update calibration/range i2c register only if necessary, as it is very slow */
1940  if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
1941  uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
1942  i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1943  sizeof(i2c_data));
1944  }
1945 
1946  /* 4020 manual asks that sample interval register to be set before writing to convert register.
1947  * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
1948  writew(0,
1949  priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1950  writew(2,
1951  priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1952  }
1953 
1954  for (n = 0; n < insn->n; n++) {
1955 
1956  /* clear adc buffer (inside loop for 4020 sake) */
1957  writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
1958 
1959  /* trigger conversion, bits sent only matter for 4020 */
1960  writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1961  priv(dev)->main_iobase + ADC_CONVERT_REG);
1962 
1963  /* wait for data */
1964  for (i = 0; i < timeout; i++) {
1965  bits = readw(priv(dev)->main_iobase + HW_STATUS_REG);
1966  DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1967  if (board(dev)->layout == LAYOUT_4020) {
1968  if (readw(priv(dev)->main_iobase +
1969  ADC_WRITE_PNTR_REG))
1970  break;
1971  } else {
1972  if (pipe_full_bits(bits))
1973  break;
1974  }
1975  udelay(1);
1976  }
1977  DEBUG_PRINT(" looped %i times waiting for data\n", i);
1978  if (i == timeout) {
1979  comedi_error(dev, " analog input read insn timed out");
1980  printk(" status 0x%x\n", bits);
1981  return -ETIME;
1982  }
1983  if (board(dev)->layout == LAYOUT_4020)
1984  data[n] =
1985  readl(priv(dev)->dio_counter_iobase +
1986  ADC_FIFO_REG) & 0xffff;
1987  else
1988  data[n] =
1989  readw(priv(dev)->main_iobase + PIPE1_READ_REG);
1990  }
1991 
1992  return n;
1993 }
1994 
1995 static int ai_config_calibration_source(struct comedi_device *dev,
1996  unsigned int *data)
1997 {
1998  unsigned int source = data[1];
1999  int num_calibration_sources;
2000 
2001  if (board(dev)->layout == LAYOUT_60XX)
2002  num_calibration_sources = 16;
2003  else
2004  num_calibration_sources = 8;
2005  if (source >= num_calibration_sources) {
2006  dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
2007  source);
2008  return -EINVAL;
2009  }
2010 
2011  DEBUG_PRINT("setting calibration source to %i\n", source);
2012  priv(dev)->calibration_source = source;
2013 
2014  return 2;
2015 }
2016 
2017 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
2018 {
2019  int fifo_size;
2020  const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2021  unsigned int block_size, requested_block_size;
2022  int retval;
2023 
2024  requested_block_size = data[1];
2025 
2026  if (requested_block_size) {
2027  fifo_size =
2028  requested_block_size * fifo->num_segments / bytes_in_sample;
2029 
2030  retval = set_ai_fifo_size(dev, fifo_size);
2031  if (retval < 0)
2032  return retval;
2033 
2034  }
2035 
2036  block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2037 
2038  data[1] = block_size;
2039 
2040  return 2;
2041 }
2042 
2043 static int ai_config_master_clock_4020(struct comedi_device *dev,
2044  unsigned int *data)
2045 {
2046  unsigned int divisor = data[4];
2047  int retval = 0;
2048 
2049  if (divisor < 2) {
2050  divisor = 2;
2051  retval = -EAGAIN;
2052  }
2053 
2054  switch (data[1]) {
2055  case COMEDI_EV_SCAN_BEGIN:
2056  priv(dev)->ext_clock.divisor = divisor;
2057  priv(dev)->ext_clock.chanspec = data[2];
2058  break;
2059  default:
2060  return -EINVAL;
2061  break;
2062  }
2063 
2064  data[4] = divisor;
2065 
2066  return retval ? retval : 5;
2067 }
2068 
2069 /* XXX could add support for 60xx series */
2070 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
2071 {
2072 
2073  switch (board(dev)->layout) {
2074  case LAYOUT_4020:
2075  return ai_config_master_clock_4020(dev, data);
2076  break;
2077  default:
2078  return -EINVAL;
2079  break;
2080  }
2081 
2082  return -EINVAL;
2083 }
2084 
2085 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
2086  struct comedi_insn *insn, unsigned int *data)
2087 {
2088  int id = data[0];
2089 
2090  switch (id) {
2091  case INSN_CONFIG_ALT_SOURCE:
2092  return ai_config_calibration_source(dev, data);
2093  break;
2094  case INSN_CONFIG_BLOCK_SIZE:
2095  return ai_config_block_size(dev, data);
2096  break;
2097  case INSN_CONFIG_TIMER_1:
2098  return ai_config_master_clock(dev, data);
2099  break;
2100  default:
2101  return -EINVAL;
2102  break;
2103  }
2104  return -EINVAL;
2105 }
2106 
2107 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2108  struct comedi_cmd *cmd)
2109 {
2110  int err = 0;
2111  unsigned int tmp_arg, tmp_arg2;
2112  int i;
2113  int aref;
2114  unsigned int triggers;
2115 
2116  /* Step 1 : check if triggers are trivially valid */
2117 
2118  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2119 
2120  triggers = TRIG_TIMER;
2121  if (board(dev)->layout == LAYOUT_4020)
2122  triggers |= TRIG_OTHER;
2123  else
2124  triggers |= TRIG_FOLLOW;
2125  err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2126 
2127  triggers = TRIG_TIMER;
2128  if (board(dev)->layout == LAYOUT_4020)
2129  triggers |= TRIG_NOW;
2130  else
2131  triggers |= TRIG_EXT;
2132  err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2133 
2134  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2135  err |= cfc_check_trigger_src(&cmd->stop_src,
2136  TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2137 
2138  if (err)
2139  return 1;
2140 
2141  /* Step 2a : make sure trigger sources are unique */
2142 
2143  err |= cfc_check_trigger_is_unique(cmd->start_src);
2144  err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2145  err |= cfc_check_trigger_is_unique(cmd->convert_src);
2146  err |= cfc_check_trigger_is_unique(cmd->stop_src);
2147 
2148  /* Step 2b : and mutually compatible */
2149 
2150  if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2151  err |= -EINVAL;
2152  if (cmd->stop_src != TRIG_COUNT &&
2153  cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2154  err |= -EINVAL;
2155 
2156  if (err)
2157  return 2;
2158 
2159  /* step 3: make sure arguments are trivially compatible */
2160 
2161  if (cmd->convert_src == TRIG_TIMER) {
2162  if (board(dev)->layout == LAYOUT_4020) {
2163  if (cmd->convert_arg) {
2164  cmd->convert_arg = 0;
2165  err++;
2166  }
2167  } else {
2168  if (cmd->convert_arg < board(dev)->ai_speed) {
2169  cmd->convert_arg = board(dev)->ai_speed;
2170  err++;
2171  }
2172  if (cmd->scan_begin_src == TRIG_TIMER) {
2173  /* if scans are timed faster than conversion rate allows */
2174  if (cmd->convert_arg * cmd->chanlist_len >
2175  cmd->scan_begin_arg) {
2176  cmd->scan_begin_arg =
2177  cmd->convert_arg *
2178  cmd->chanlist_len;
2179  err++;
2180  }
2181  }
2182  }
2183  }
2184 
2185  if (!cmd->chanlist_len) {
2186  cmd->chanlist_len = 1;
2187  err++;
2188  }
2189  if (cmd->scan_end_arg != cmd->chanlist_len) {
2190  cmd->scan_end_arg = cmd->chanlist_len;
2191  err++;
2192  }
2193 
2194  switch (cmd->stop_src) {
2195  case TRIG_EXT:
2196  break;
2197  case TRIG_COUNT:
2198  if (!cmd->stop_arg) {
2199  cmd->stop_arg = 1;
2200  err++;
2201  }
2202  break;
2203  case TRIG_NONE:
2204  if (cmd->stop_arg != 0) {
2205  cmd->stop_arg = 0;
2206  err++;
2207  }
2208  break;
2209  default:
2210  break;
2211  }
2212 
2213  if (err)
2214  return 3;
2215 
2216  /* step 4: fix up any arguments */
2217 
2218  if (cmd->convert_src == TRIG_TIMER) {
2219  tmp_arg = cmd->convert_arg;
2220  tmp_arg2 = cmd->scan_begin_arg;
2221  check_adc_timing(dev, cmd);
2222  if (tmp_arg != cmd->convert_arg)
2223  err++;
2224  if (tmp_arg2 != cmd->scan_begin_arg)
2225  err++;
2226  }
2227 
2228  if (err)
2229  return 4;
2230 
2231  /* make sure user is doesn't change analog reference mid chanlist */
2232  if (cmd->chanlist) {
2233  aref = CR_AREF(cmd->chanlist[0]);
2234  for (i = 1; i < cmd->chanlist_len; i++) {
2235  if (aref != CR_AREF(cmd->chanlist[i])) {
2236  comedi_error(dev,
2237  "all elements in chanlist must use the same analog reference");
2238  err++;
2239  break;
2240  }
2241  }
2242  /* check 4020 chanlist */
2243  if (board(dev)->layout == LAYOUT_4020) {
2244  unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2245  for (i = 1; i < cmd->chanlist_len; i++) {
2246  if (CR_CHAN(cmd->chanlist[i]) !=
2247  first_channel + i) {
2248  comedi_error(dev,
2249  "chanlist must use consecutive channels");
2250  err++;
2251  break;
2252  }
2253  }
2254  if (cmd->chanlist_len == 3) {
2255  comedi_error(dev,
2256  "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2257  err++;
2258  }
2259  }
2260  }
2261 
2262  if (err)
2263  return 5;
2264 
2265  return 0;
2266 }
2267 
2268 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2269 {
2270 /* disable for now until I work out a race */
2271  return 0;
2272 
2273  if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2274  return 1;
2275  else
2276  return 0;
2277 }
2278 
2279 static void setup_sample_counters(struct comedi_device *dev,
2280  struct comedi_cmd *cmd)
2281 {
2282  if (cmd->stop_src == TRIG_COUNT) {
2283  /* set software count */
2284  priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len;
2285  }
2286  /* load hardware conversion counter */
2287  if (use_hw_sample_counter(cmd)) {
2288  writew(cmd->stop_arg & 0xffff,
2289  priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2290  writew((cmd->stop_arg >> 16) & 0xff,
2291  priv(dev)->main_iobase + ADC_COUNT_UPPER_REG);
2292  } else {
2293  writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2294  }
2295 }
2296 
2297 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2298 {
2299  unsigned int num_samples;
2300 
2301  num_samples =
2302  priv(dev)->ai_fifo_segment_length *
2303  board(dev)->ai_fifo->sample_packing_ratio;
2304  if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2305  num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2306 
2307  return num_samples;
2308 }
2309 
2310 static void disable_ai_pacing(struct comedi_device *dev)
2311 {
2312  unsigned long flags;
2313 
2314  disable_ai_interrupts(dev);
2315 
2316  spin_lock_irqsave(&dev->spinlock, flags);
2317  priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2318  writew(priv(dev)->adc_control1_bits,
2319  priv(dev)->main_iobase + ADC_CONTROL1_REG);
2320  spin_unlock_irqrestore(&dev->spinlock, flags);
2321 
2322  /* disable pacing, triggering, etc */
2323  writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2324  priv(dev)->main_iobase + ADC_CONTROL0_REG);
2325 }
2326 
2327 static void disable_ai_interrupts(struct comedi_device *dev)
2328 {
2329  unsigned long flags;
2330 
2331  spin_lock_irqsave(&dev->spinlock, flags);
2332  priv(dev)->intr_enable_bits &=
2333  ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2334  ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2335  ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2336  writew(priv(dev)->intr_enable_bits,
2337  priv(dev)->main_iobase + INTR_ENABLE_REG);
2338  spin_unlock_irqrestore(&dev->spinlock, flags);
2339 
2340  DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2341 }
2342 
2343 static void enable_ai_interrupts(struct comedi_device *dev,
2344  const struct comedi_cmd *cmd)
2345 {
2346  uint32_t bits;
2347  unsigned long flags;
2348 
2349  bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2350  EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2351  /* Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2352  if (cmd->flags & TRIG_WAKE_EOS) {
2353  /* 4020 doesn't support pio transfers except for fifo dregs */
2354  if (board(dev)->layout != LAYOUT_4020)
2355  bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2356  }
2357  spin_lock_irqsave(&dev->spinlock, flags);
2358  priv(dev)->intr_enable_bits |= bits;
2359  writew(priv(dev)->intr_enable_bits,
2360  priv(dev)->main_iobase + INTR_ENABLE_REG);
2361  DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2362  spin_unlock_irqrestore(&dev->spinlock, flags);
2363 }
2364 
2365 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2366  const struct comedi_cmd *cmd)
2367 {
2368  /* supposed to load counter with desired divisor minus 3 */
2369  return cmd->convert_arg / TIMER_BASE - 3;
2370 }
2371 
2372 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2373  struct comedi_cmd *cmd)
2374 {
2375  uint32_t count;
2376  /* figure out how long we need to delay at end of scan */
2377  switch (cmd->scan_begin_src) {
2378  case TRIG_TIMER:
2379  count = (cmd->scan_begin_arg -
2380  (cmd->convert_arg * (cmd->chanlist_len - 1)))
2381  / TIMER_BASE;
2382  break;
2383  case TRIG_FOLLOW:
2384  count = cmd->convert_arg / TIMER_BASE;
2385  break;
2386  default:
2387  return 0;
2388  break;
2389  }
2390  return count - 3;
2391 }
2392 
2393 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2394  struct comedi_cmd *cmd)
2395 {
2396  unsigned int divisor;
2397 
2398  switch (cmd->scan_begin_src) {
2399  case TRIG_TIMER:
2400  divisor = cmd->scan_begin_arg / TIMER_BASE;
2401  break;
2402  case TRIG_OTHER:
2403  divisor = priv(dev)->ext_clock.divisor;
2404  break;
2405  default: /* should never happen */
2406  comedi_error(dev, "bug! failed to set ai pacing!");
2407  divisor = 1000;
2408  break;
2409  }
2410 
2411  /* supposed to load counter with desired divisor minus 2 for 4020 */
2412  return divisor - 2;
2413 }
2414 
2415 static void select_master_clock_4020(struct comedi_device *dev,
2416  const struct comedi_cmd *cmd)
2417 {
2418  /* select internal/external master clock */
2419  priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2420  if (cmd->scan_begin_src == TRIG_OTHER) {
2421  int chanspec = priv(dev)->ext_clock.chanspec;
2422 
2423  if (CR_CHAN(chanspec))
2424  priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS;
2425  else
2426  priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS;
2427  } else {
2428  priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2429  }
2430  writew(priv(dev)->hw_config_bits,
2431  priv(dev)->main_iobase + HW_CONFIG_REG);
2432 }
2433 
2434 static void select_master_clock(struct comedi_device *dev,
2435  const struct comedi_cmd *cmd)
2436 {
2437  switch (board(dev)->layout) {
2438  case LAYOUT_4020:
2439  select_master_clock_4020(dev, cmd);
2440  break;
2441  default:
2442  break;
2443  }
2444 }
2445 
2446 static inline void dma_start_sync(struct comedi_device *dev,
2447  unsigned int channel)
2448 {
2449  unsigned long flags;
2450 
2451  /* spinlock for plx dma control/status reg */
2452  spin_lock_irqsave(&dev->spinlock, flags);
2453  if (channel)
2454  writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2455  PLX_CLEAR_DMA_INTR_BIT,
2456  priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2457  else
2458  writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2459  PLX_CLEAR_DMA_INTR_BIT,
2460  priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2461  spin_unlock_irqrestore(&dev->spinlock, flags);
2462 }
2463 
2464 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2465 {
2466  uint32_t convert_counter = 0, scan_counter = 0;
2467 
2468  check_adc_timing(dev, cmd);
2469 
2470  select_master_clock(dev, cmd);
2471 
2472  if (board(dev)->layout == LAYOUT_4020) {
2473  convert_counter = ai_convert_counter_4020(dev, cmd);
2474  } else {
2475  convert_counter = ai_convert_counter_6xxx(dev, cmd);
2476  scan_counter = ai_scan_counter_6xxx(dev, cmd);
2477  }
2478 
2479  /* load lower 16 bits of convert interval */
2480  writew(convert_counter & 0xffff,
2481  priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2482  DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2483  /* load upper 8 bits of convert interval */
2484  writew((convert_counter >> 16) & 0xff,
2485  priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2486  /* load lower 16 bits of scan delay */
2487  writew(scan_counter & 0xffff,
2488  priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2489  /* load upper 8 bits of scan delay */
2490  writew((scan_counter >> 16) & 0xff,
2491  priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2492  DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2493 }
2494 
2495 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2496 {
2497  int i;
2498  for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2499  if (CR_CHAN(cmd->chanlist[i + 1]) !=
2500  CR_CHAN(cmd->chanlist[i]) + 1)
2501  return 0;
2502  if (CR_RANGE(cmd->chanlist[i + 1]) !=
2503  CR_RANGE(cmd->chanlist[i]))
2504  return 0;
2505  if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2506  return 0;
2507  }
2508  return 1;
2509 }
2510 
2511 static int setup_channel_queue(struct comedi_device *dev,
2512  const struct comedi_cmd *cmd)
2513 {
2514  unsigned short bits;
2515  int i;
2516 
2517  if (board(dev)->layout != LAYOUT_4020) {
2518  if (use_internal_queue_6xxx(cmd)) {
2519  priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
2520  writew(priv(dev)->hw_config_bits,
2521  priv(dev)->main_iobase + HW_CONFIG_REG);
2522  bits = 0;
2523  /* set channel */
2524  bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2525  /* set gain */
2526  bits |= ai_range_bits_6xxx(dev,
2527  CR_RANGE(cmd->chanlist[0]));
2528  /* set single-ended / differential */
2529  bits |= se_diff_bit_6xxx(dev,
2530  CR_AREF(cmd->chanlist[0]) ==
2531  AREF_DIFF);
2532  if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2533  bits |= ADC_COMMON_BIT;
2534  /* set stop channel */
2535  writew(adc_chan_bits
2536  (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2537  priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2538  /* set start channel, and rest of settings */
2539  writew(bits,
2540  priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2541  } else {
2542  /* use external queue */
2543  if (dev->write_subdev && dev->write_subdev->busy) {
2544  warn_external_queue(dev);
2545  return -EBUSY;
2546  }
2547  priv(dev)->hw_config_bits |= EXT_QUEUE_BIT;
2548  writew(priv(dev)->hw_config_bits,
2549  priv(dev)->main_iobase + HW_CONFIG_REG);
2550  /* clear DAC buffer to prevent weird interactions */
2551  writew(0,
2552  priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
2553  /* clear queue pointer */
2554  writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2555  /* load external queue */
2556  for (i = 0; i < cmd->chanlist_len; i++) {
2557  bits = 0;
2558  /* set channel */
2559  bits |=
2560  adc_chan_bits(CR_CHAN(cmd->chanlist[i]));
2561  /* set gain */
2562  bits |= ai_range_bits_6xxx(dev,
2563  CR_RANGE(cmd->
2564  chanlist
2565  [i]));
2566  /* set single-ended / differential */
2567  bits |= se_diff_bit_6xxx(dev,
2568  CR_AREF(cmd->
2569  chanlist[i]) ==
2570  AREF_DIFF);
2571  if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2572  bits |= ADC_COMMON_BIT;
2573  /* mark end of queue */
2574  if (i == cmd->chanlist_len - 1)
2575  bits |= QUEUE_EOSCAN_BIT |
2576  QUEUE_EOSEQ_BIT;
2577  writew(bits,
2578  priv(dev)->main_iobase +
2579  ADC_QUEUE_FIFO_REG);
2580  DEBUG_PRINT
2581  ("wrote 0x%x to external channel queue\n",
2582  bits);
2583  }
2584  /* doing a queue clear is not specified in board docs,
2585  * but required for reliable operation */
2586  writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2587  /* prime queue holding register */
2588  writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2589  }
2590  } else {
2591  unsigned short old_cal_range_bits =
2592  priv(dev)->i2c_cal_range_bits;
2593 
2594  priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2595  /* select BNC inputs */
2596  priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2597  /* select ranges */
2598  for (i = 0; i < cmd->chanlist_len; i++) {
2599  unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2600  unsigned int range = CR_RANGE(cmd->chanlist[i]);
2601 
2602  if (range == 0)
2603  priv(dev)->i2c_cal_range_bits |=
2604  attenuate_bit(channel);
2605  else
2606  priv(dev)->i2c_cal_range_bits &=
2607  ~attenuate_bit(channel);
2608  }
2609  /* update calibration/range i2c register only if necessary, as it is very slow */
2610  if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2611  uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2612  i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2613  sizeof(i2c_data));
2614  }
2615  }
2616  return 0;
2617 }
2618 
2619 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2620  unsigned int dma_channel,
2621  unsigned int descriptor_bits)
2622 {
2623  /* The transfer size, pci address, and local address registers
2624  * are supposedly unused during chained dma,
2625  * but I have found that left over values from last operation
2626  * occasionally cause problems with transfer of first dma
2627  * block. Initializing them to zero seems to fix the problem. */
2628  if (dma_channel) {
2629  writel(0,
2630  priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2631  writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2632  writel(0,
2633  priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2634  writel(descriptor_bits,
2635  priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2636  } else {
2637  writel(0,
2638  priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2639  writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2640  writel(0,
2641  priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2642  writel(descriptor_bits,
2643  priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2644  }
2645 }
2646 
2647 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2648 {
2649  struct comedi_async *async = s->async;
2650  struct comedi_cmd *cmd = &async->cmd;
2651  uint32_t bits;
2652  unsigned int i;
2653  unsigned long flags;
2654  int retval;
2655 
2656  disable_ai_pacing(dev);
2657  abort_dma(dev, 1);
2658 
2659  retval = setup_channel_queue(dev, cmd);
2660  if (retval < 0)
2661  return retval;
2662 
2663  /* make sure internal calibration source is turned off */
2664  writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
2665 
2666  set_ai_pacing(dev, cmd);
2667 
2668  setup_sample_counters(dev, cmd);
2669 
2670  enable_ai_interrupts(dev, cmd);
2671 
2672  spin_lock_irqsave(&dev->spinlock, flags);
2673  /* set mode, allow conversions through software gate */
2674  priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT;
2675  priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
2676  if (board(dev)->layout != LAYOUT_4020) {
2677  priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK;
2678  if (cmd->convert_src == TRIG_EXT)
2679  priv(dev)->adc_control1_bits |= adc_mode_bits(13); /* good old mode 13 */
2680  else
2681  priv(dev)->adc_control1_bits |= adc_mode_bits(8); /* mode 8. What else could you need? */
2682  } else {
2683  priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2684  if (cmd->chanlist_len == 4)
2685  priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2686  else if (cmd->chanlist_len == 2)
2687  priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2688  priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2689  priv(dev)->adc_control1_bits |=
2690  adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2691  priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2692  priv(dev)->adc_control1_bits |=
2693  adc_hi_chan_4020_bits(CR_CHAN
2694  (cmd->
2695  chanlist[cmd->chanlist_len - 1]));
2696  }
2697  writew(priv(dev)->adc_control1_bits,
2698  priv(dev)->main_iobase + ADC_CONTROL1_REG);
2699  DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits);
2700  spin_unlock_irqrestore(&dev->spinlock, flags);
2701 
2702  /* clear adc buffer */
2703  writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2704 
2705  if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2706  board(dev)->layout == LAYOUT_4020) {
2707  priv(dev)->ai_dma_index = 0;
2708 
2709  /* set dma transfer size */
2710  for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2711  priv(dev)->ai_dma_desc[i].transfer_size =
2712  cpu_to_le32(dma_transfer_size(dev) *
2713  sizeof(uint16_t));
2714 
2715  /* give location of first dma descriptor */
2716  load_first_dma_descriptor(dev, 1,
2717  priv(dev)->ai_dma_desc_bus_addr |
2718  PLX_DESC_IN_PCI_BIT |
2719  PLX_INTR_TERM_COUNT |
2720  PLX_XFER_LOCAL_TO_PCI);
2721 
2722  dma_start_sync(dev, 1);
2723  }
2724 
2725  if (board(dev)->layout == LAYOUT_4020) {
2726  /* set source for external triggers */
2727  bits = 0;
2728  if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2729  bits |= EXT_START_TRIG_BNC_BIT;
2730  if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2731  bits |= EXT_STOP_TRIG_BNC_BIT;
2732  writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2733  }
2734 
2735  spin_lock_irqsave(&dev->spinlock, flags);
2736 
2737  /* enable pacing, triggering, etc */
2738  bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2739  if (cmd->flags & TRIG_WAKE_EOS)
2740  bits |= ADC_DMA_DISABLE_BIT;
2741  /* set start trigger */
2742  if (cmd->start_src == TRIG_EXT) {
2743  bits |= ADC_START_TRIG_EXT_BITS;
2744  if (cmd->start_arg & CR_INVERT)
2745  bits |= ADC_START_TRIG_FALLING_BIT;
2746  } else if (cmd->start_src == TRIG_NOW)
2747  bits |= ADC_START_TRIG_SOFT_BITS;
2748  if (use_hw_sample_counter(cmd))
2749  bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2750  writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG);
2751  DEBUG_PRINT("control0 bits 0x%x\n", bits);
2752 
2753  priv(dev)->ai_cmd_running = 1;
2754 
2755  spin_unlock_irqrestore(&dev->spinlock, flags);
2756 
2757  /* start acquisition */
2758  if (cmd->start_src == TRIG_NOW) {
2759  writew(0, priv(dev)->main_iobase + ADC_START_REG);
2760  DEBUG_PRINT("soft trig\n");
2761  }
2762 
2763  return 0;
2764 }
2765 
2766 /* read num_samples from 16 bit wide ai fifo */
2767 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2768 {
2769  struct comedi_subdevice *s = dev->read_subdev;
2770  struct comedi_async *async = s->async;
2771  struct comedi_cmd *cmd = &async->cmd;
2772  unsigned int i;
2773  uint16_t prepost_bits;
2774  int read_segment, read_index, write_segment, write_index;
2775  int num_samples;
2776 
2777  do {
2778  /* get least significant 15 bits */
2779  read_index =
2780  readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2781  write_index =
2782  readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2783  /* Get most significant bits (grey code). Different boards use different code
2784  * so use a scheme that doesn't depend on encoding. This read must
2785  * occur after reading least significant 15 bits to avoid race
2786  * with fifo switching to next segment. */
2787  prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG);
2788 
2789  /* if read and write pointers are not on the same fifo segment, read to the
2790  * end of the read segment */
2791  read_segment = adc_upper_read_ptr_code(prepost_bits);
2792  write_segment = adc_upper_write_ptr_code(prepost_bits);
2793 
2794  DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2795  read_segment, write_segment, read_index,
2796  write_index);
2797 
2798  if (read_segment != write_segment)
2799  num_samples =
2800  priv(dev)->ai_fifo_segment_length - read_index;
2801  else
2802  num_samples = write_index - read_index;
2803 
2804  if (cmd->stop_src == TRIG_COUNT) {
2805  if (priv(dev)->ai_count == 0)
2806  break;
2807  if (num_samples > priv(dev)->ai_count)
2808  num_samples = priv(dev)->ai_count;
2809 
2810  priv(dev)->ai_count -= num_samples;
2811  }
2812 
2813  if (num_samples < 0) {
2814  dev_err(dev->class_dev,
2815  "cb_pcidas64: bug! num_samples < 0\n");
2816  break;
2817  }
2818 
2819  DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2820 
2821  for (i = 0; i < num_samples; i++) {
2822  cfc_write_to_buffer(s,
2823  readw(priv(dev)->main_iobase +
2824  ADC_FIFO_REG));
2825  }
2826 
2827  } while (read_segment != write_segment);
2828 }
2829 
2830 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2831  * The pci-4020 hardware only supports
2832  * dma transfers (it only supports the use of pio for draining the last remaining
2833  * points from the fifo when a data acquisition operation has completed).
2834  */
2835 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2836 {
2837  struct comedi_subdevice *s = dev->read_subdev;
2838  struct comedi_async *async = s->async;
2839  struct comedi_cmd *cmd = &async->cmd;
2840  unsigned int i;
2841  unsigned int max_transfer = 100000;
2842  uint32_t fifo_data;
2843  int write_code =
2844  readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2845  int read_code =
2846  readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2847 
2848  if (cmd->stop_src == TRIG_COUNT) {
2849  if (max_transfer > priv(dev)->ai_count)
2850  max_transfer = priv(dev)->ai_count;
2851 
2852  }
2853  for (i = 0; read_code != write_code && i < max_transfer;) {
2854  fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG);
2855  cfc_write_to_buffer(s, fifo_data & 0xffff);
2856  i++;
2857  if (i < max_transfer) {
2858  cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2859  i++;
2860  }
2861  read_code =
2862  readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2863  }
2864  priv(dev)->ai_count -= i;
2865 }
2866 
2867 /* empty fifo */
2868 static void pio_drain_ai_fifo(struct comedi_device *dev)
2869 {
2870  if (board(dev)->layout == LAYOUT_4020)
2871  pio_drain_ai_fifo_32(dev);
2872  else
2873  pio_drain_ai_fifo_16(dev);
2874 }
2875 
2876 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2877 {
2878  struct comedi_async *async = dev->read_subdev->async;
2879  uint32_t next_transfer_addr;
2880  int j;
2881  int num_samples = 0;
2882  void __iomem *pci_addr_reg;
2883 
2884  if (channel)
2885  pci_addr_reg =
2886  priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2887  else
2888  pci_addr_reg =
2889  priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2890 
2891  /* loop until we have read all the full buffers */
2892  for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2893  (next_transfer_addr <
2894  priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index]
2895  || next_transfer_addr >=
2896  priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] +
2897  DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) {
2898  /* transfer data from dma buffer to comedi buffer */
2899  num_samples = dma_transfer_size(dev);
2900  if (async->cmd.stop_src == TRIG_COUNT) {
2901  if (num_samples > priv(dev)->ai_count)
2902  num_samples = priv(dev)->ai_count;
2903  priv(dev)->ai_count -= num_samples;
2904  }
2905  cfc_write_array_to_buffer(dev->read_subdev,
2906  priv(dev)->ai_buffer[priv(dev)->
2907  ai_dma_index],
2908  num_samples * sizeof(uint16_t));
2909  priv(dev)->ai_dma_index =
2910  (priv(dev)->ai_dma_index +
2911  1) % ai_dma_ring_count(board(dev));
2912 
2913  DEBUG_PRINT("next buffer addr 0x%lx\n",
2914  (unsigned long)priv(dev)->
2915  ai_buffer_bus_addr[priv(dev)->ai_dma_index]);
2916  DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2917  }
2918  /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
2919  * unused buffer) */
2920 }
2921 
2922 static void handle_ai_interrupt(struct comedi_device *dev,
2923  unsigned short status,
2924  unsigned int plx_status)
2925 {
2926  struct comedi_subdevice *s = dev->read_subdev;
2927  struct comedi_async *async = s->async;
2928  struct comedi_cmd *cmd = &async->cmd;
2929  uint8_t dma1_status;
2930  unsigned long flags;
2931 
2932  /* check for fifo overrun */
2933  if (status & ADC_OVERRUN_BIT) {
2934  comedi_error(dev, "fifo overrun");
2935  async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2936  }
2937  /* spin lock makes sure no one else changes plx dma control reg */
2938  spin_lock_irqsave(&dev->spinlock, flags);
2939  dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2940  if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
2941  writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2942  priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2943  DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2944 
2945  if (dma1_status & PLX_DMA_EN_BIT)
2946  drain_dma_buffers(dev, 1);
2947 
2948  DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2949  }
2950  spin_unlock_irqrestore(&dev->spinlock, flags);
2951 
2952  if (status & ADC_DONE_BIT)
2953  DEBUG_PRINT("adc done interrupt\n");
2954 
2955  /* drain fifo with pio */
2956  if ((status & ADC_DONE_BIT) ||
2957  ((cmd->flags & TRIG_WAKE_EOS) &&
2958  (status & ADC_INTR_PENDING_BIT) &&
2959  (board(dev)->layout != LAYOUT_4020))) {
2960  DEBUG_PRINT("pio fifo drain\n");
2961  spin_lock_irqsave(&dev->spinlock, flags);
2962  if (priv(dev)->ai_cmd_running) {
2963  spin_unlock_irqrestore(&dev->spinlock, flags);
2964  pio_drain_ai_fifo(dev);
2965  } else
2966  spin_unlock_irqrestore(&dev->spinlock, flags);
2967  }
2968  /* if we are have all the data, then quit */
2969  if ((cmd->stop_src == TRIG_COUNT && (int)priv(dev)->ai_count <= 0) ||
2970  (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2971  async->events |= COMEDI_CB_EOA;
2972  }
2973 
2974  cfc_handle_events(dev, s);
2975 }
2976 
2977 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2978 {
2979  unsigned int buffer_index;
2980 
2981  if (priv(dev)->ao_dma_index == 0)
2982  buffer_index = AO_DMA_RING_COUNT - 1;
2983  else
2984  buffer_index = priv(dev)->ao_dma_index - 1;
2985  return buffer_index;
2986 }
2987 
2988 static int last_ao_dma_load_completed(struct comedi_device *dev)
2989 {
2990  unsigned int buffer_index;
2991  unsigned int transfer_address;
2992  unsigned short dma_status;
2993 
2994  buffer_index = prev_ao_dma_index(dev);
2995  dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2996  if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2997  return 0;
2998 
2999  transfer_address =
3000  readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3001  if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index])
3002  return 0;
3003 
3004  return 1;
3005 }
3006 
3007 static int ao_stopped_by_error(struct comedi_device *dev,
3008  const struct comedi_cmd *cmd)
3009 {
3010  if (cmd->stop_src == TRIG_NONE)
3011  return 1;
3012  if (cmd->stop_src == TRIG_COUNT) {
3013  if (priv(dev)->ao_count)
3014  return 1;
3015  if (last_ao_dma_load_completed(dev) == 0)
3016  return 1;
3017  }
3018  return 0;
3019 }
3020 
3021 static inline int ao_dma_needs_restart(struct comedi_device *dev,
3022  unsigned short dma_status)
3023 {
3024  if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3025  (dma_status & PLX_DMA_EN_BIT) == 0)
3026  return 0;
3027  if (last_ao_dma_load_completed(dev))
3028  return 0;
3029 
3030  return 1;
3031 }
3032 
3033 static void restart_ao_dma(struct comedi_device *dev)
3034 {
3035  unsigned int dma_desc_bits;
3036 
3037  dma_desc_bits =
3038  readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3039  dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3040  DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3041  load_first_dma_descriptor(dev, 0, dma_desc_bits);
3042 
3043  dma_start_sync(dev, 0);
3044 }
3045 
3046 static void handle_ao_interrupt(struct comedi_device *dev,
3047  unsigned short status, unsigned int plx_status)
3048 {
3049  struct comedi_subdevice *s = dev->write_subdev;
3050  struct comedi_async *async;
3051  struct comedi_cmd *cmd;
3052  uint8_t dma0_status;
3053  unsigned long flags;
3054 
3055  /* board might not support ao, in which case write_subdev is NULL */
3056  if (s == NULL)
3057  return;
3058  async = s->async;
3059  cmd = &async->cmd;
3060 
3061  /* spin lock makes sure no one else changes plx dma control reg */
3062  spin_lock_irqsave(&dev->spinlock, flags);
3063  dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3064  if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
3065  if ((dma0_status & PLX_DMA_EN_BIT)
3066  && !(dma0_status & PLX_DMA_DONE_BIT))
3067  writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3068  priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3069  else
3070  writeb(PLX_CLEAR_DMA_INTR_BIT,
3071  priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3072  spin_unlock_irqrestore(&dev->spinlock, flags);
3073  DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3074  if (dma0_status & PLX_DMA_EN_BIT) {
3075  load_ao_dma(dev, cmd);
3076  /* try to recover from dma end-of-chain event */
3077  if (ao_dma_needs_restart(dev, dma0_status))
3078  restart_ao_dma(dev);
3079  }
3080  DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3081  } else
3082  spin_unlock_irqrestore(&dev->spinlock, flags);
3083 
3084  if ((status & DAC_DONE_BIT)) {
3085  async->events |= COMEDI_CB_EOA;
3086  if (ao_stopped_by_error(dev, cmd))
3087  async->events |= COMEDI_CB_ERROR;
3088  DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3089  readl(priv(dev)->plx9080_iobase +
3090  PLX_DMA0_DESCRIPTOR_REG));
3091  DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3092  readl(priv(dev)->plx9080_iobase +
3093  PLX_DMA0_PCI_ADDRESS_REG));
3094  }
3095  cfc_handle_events(dev, s);
3096 }
3097 
3098 static irqreturn_t handle_interrupt(int irq, void *d)
3099 {
3100  struct comedi_device *dev = d;
3101  unsigned short status;
3102  uint32_t plx_status;
3103  uint32_t plx_bits;
3104 
3105  plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
3106  status = readw(priv(dev)->main_iobase + HW_STATUS_REG);
3107 
3108  DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3109  DEBUG_PRINT("plx status 0x%x\n", plx_status);
3110 
3111  /* an interrupt before all the postconfig stuff gets done could
3112  * cause a NULL dereference if we continue through the
3113  * interrupt handler */
3114  if (dev->attached == 0) {
3115  DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3116  status);
3117  return IRQ_HANDLED;
3118  }
3119  handle_ai_interrupt(dev, status, plx_status);
3120  handle_ao_interrupt(dev, status, plx_status);
3121 
3122  /* clear possible plx9080 interrupt sources */
3123  if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
3124  plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3125  writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3126  DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3127  }
3128 
3129  DEBUG_PRINT("exiting handler\n");
3130 
3131  return IRQ_HANDLED;
3132 }
3133 
3134 static void abort_dma(struct comedi_device *dev, unsigned int channel)
3135 {
3136  unsigned long flags;
3137 
3138  /* spinlock for plx dma control/status reg */
3139  spin_lock_irqsave(&dev->spinlock, flags);
3140 
3141  plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
3142 
3143  spin_unlock_irqrestore(&dev->spinlock, flags);
3144 }
3145 
3146 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3147 {
3148  unsigned long flags;
3149 
3150  spin_lock_irqsave(&dev->spinlock, flags);
3151  if (priv(dev)->ai_cmd_running == 0) {
3152  spin_unlock_irqrestore(&dev->spinlock, flags);
3153  return 0;
3154  }
3155  priv(dev)->ai_cmd_running = 0;
3156  spin_unlock_irqrestore(&dev->spinlock, flags);
3157 
3158  disable_ai_pacing(dev);
3159 
3160  abort_dma(dev, 1);
3161 
3162  DEBUG_PRINT("ai canceled\n");
3163  return 0;
3164 }
3165 
3166 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3167  struct comedi_insn *insn, unsigned int *data)
3168 {
3169  int chan = CR_CHAN(insn->chanspec);
3170  int range = CR_RANGE(insn->chanspec);
3171 
3172  /* do some initializing */
3173  writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3174 
3175  /* set range */
3176  set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range);
3177  writew(priv(dev)->dac_control1_bits,
3178  priv(dev)->main_iobase + DAC_CONTROL1_REG);
3179 
3180  /* write to channel */
3181  if (board(dev)->layout == LAYOUT_4020) {
3182  writew(data[0] & 0xff,
3183  priv(dev)->main_iobase + dac_lsb_4020_reg(chan));
3184  writew((data[0] >> 8) & 0xf,
3185  priv(dev)->main_iobase + dac_msb_4020_reg(chan));
3186  } else {
3187  writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan));
3188  }
3189 
3190  /* remember output value */
3191  priv(dev)->ao_value[chan] = data[0];
3192 
3193  return 1;
3194 }
3195 
3196 static int ao_readback_insn(struct comedi_device *dev,
3197  struct comedi_subdevice *s,
3198  struct comedi_insn *insn, unsigned int *data)
3199 {
3200  data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)];
3201 
3202  return 1;
3203 }
3204 
3205 static void set_dac_control0_reg(struct comedi_device *dev,
3206  const struct comedi_cmd *cmd)
3207 {
3208  unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3209  WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3210 
3211  if (cmd->start_src == TRIG_EXT) {
3212  bits |= WAVEFORM_TRIG_EXT_BITS;
3213  if (cmd->start_arg & CR_INVERT)
3214  bits |= WAVEFORM_TRIG_FALLING_BIT;
3215  } else {
3216  bits |= WAVEFORM_TRIG_SOFT_BITS;
3217  }
3218  if (cmd->scan_begin_src == TRIG_EXT) {
3219  bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3220  if (cmd->scan_begin_arg & CR_INVERT)
3221  bits |= DAC_EXT_UPDATE_FALLING_BIT;
3222  }
3223  writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3224 }
3225 
3226 static void set_dac_control1_reg(struct comedi_device *dev,
3227  const struct comedi_cmd *cmd)
3228 {
3229  int i;
3230 
3231  for (i = 0; i < cmd->chanlist_len; i++) {
3232  int channel, range;
3233 
3234  channel = CR_CHAN(cmd->chanlist[i]);
3235  range = CR_RANGE(cmd->chanlist[i]);
3236  set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel,
3237  range);
3238  }
3239  priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT;
3240  writew(priv(dev)->dac_control1_bits,
3241  priv(dev)->main_iobase + DAC_CONTROL1_REG);
3242 }
3243 
3244 static void set_dac_select_reg(struct comedi_device *dev,
3245  const struct comedi_cmd *cmd)
3246 {
3247  uint16_t bits;
3248  unsigned int first_channel, last_channel;
3249 
3250  first_channel = CR_CHAN(cmd->chanlist[0]);
3251  last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3252  if (last_channel < first_channel)
3253  comedi_error(dev, "bug! last ao channel < first ao channel");
3254 
3255  bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3256 
3257  writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG);
3258 }
3259 
3260 static void set_dac_interval_regs(struct comedi_device *dev,
3261  const struct comedi_cmd *cmd)
3262 {
3263  unsigned int divisor;
3264 
3265  if (cmd->scan_begin_src != TRIG_TIMER)
3266  return;
3267 
3268  divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3269  if (divisor > max_counter_value) {
3270  comedi_error(dev, "bug! ao divisor too big");
3271  divisor = max_counter_value;
3272  }
3273  writew(divisor & 0xffff,
3274  priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3275  writew((divisor >> 16) & 0xff,
3276  priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3277 }
3278 
3279 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
3280  const struct comedi_cmd *cmd)
3281 {
3282  unsigned int num_bytes, buffer_index, prev_buffer_index;
3283  unsigned int next_bits;
3284 
3285  buffer_index = priv(dev)->ao_dma_index;
3286  prev_buffer_index = prev_ao_dma_index(dev);
3287 
3288  DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3289  priv(dev)->ao_buffer_bus_addr[buffer_index]);
3290 
3291  num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3292  if (num_bytes > DMA_BUFFER_SIZE)
3293  num_bytes = DMA_BUFFER_SIZE;
3294  if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count)
3295  num_bytes = priv(dev)->ao_count;
3296  num_bytes -= num_bytes % bytes_in_sample;
3297 
3298  if (num_bytes == 0)
3299  return 0;
3300 
3301  DEBUG_PRINT("loading %i bytes\n", num_bytes);
3302 
3303  num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3304  priv(dev)->
3305  ao_buffer[buffer_index],
3306  num_bytes);
3307  priv(dev)->ao_dma_desc[buffer_index].transfer_size =
3308  cpu_to_le32(num_bytes);
3309  /* set end of chain bit so we catch underruns */
3310  next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next);
3311  next_bits |= PLX_END_OF_CHAIN_BIT;
3312  priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3313  /* clear end of chain bit on previous buffer now that we have set it
3314  * for the last buffer */
3315  next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next);
3316  next_bits &= ~PLX_END_OF_CHAIN_BIT;
3317  priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3318 
3319  priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3320  priv(dev)->ao_count -= num_bytes;
3321 
3322  return num_bytes;
3323 }
3324 
3325 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3326 {
3327  unsigned int num_bytes;
3328  unsigned int next_transfer_addr;
3329  void __iomem *pci_addr_reg =
3330  priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3331  unsigned int buffer_index;
3332 
3333  do {
3334  buffer_index = priv(dev)->ao_dma_index;
3335  /* don't overwrite data that hasn't been transferred yet */
3336  next_transfer_addr = readl(pci_addr_reg);
3337  if (next_transfer_addr >=
3338  priv(dev)->ao_buffer_bus_addr[buffer_index]
3339  && next_transfer_addr <
3340  priv(dev)->ao_buffer_bus_addr[buffer_index] +
3341  DMA_BUFFER_SIZE)
3342  return;
3343  num_bytes = load_ao_dma_buffer(dev, cmd);
3344  } while (num_bytes >= DMA_BUFFER_SIZE);
3345 }
3346 
3347 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3348 {
3349  unsigned int num_bytes;
3350  int i;
3351 
3352  /* clear queue pointer too, since external queue has
3353  * weird interactions with ao fifo */
3354  writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
3355  writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
3356 
3357  num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3358  if (cmd->stop_src == TRIG_COUNT &&
3359  num_bytes / bytes_in_sample > priv(dev)->ao_count)
3360  num_bytes = priv(dev)->ao_count * bytes_in_sample;
3361  num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3362  priv(dev)->ao_bounce_buffer,
3363  num_bytes);
3364  for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3365  writew(priv(dev)->ao_bounce_buffer[i],
3366  priv(dev)->main_iobase + DAC_FIFO_REG);
3367  }
3368  priv(dev)->ao_count -= num_bytes / bytes_in_sample;
3369  if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0)
3370  return 0;
3371  num_bytes = load_ao_dma_buffer(dev, cmd);
3372  if (num_bytes == 0)
3373  return -1;
3374  if (num_bytes >= DMA_BUFFER_SIZE) ;
3375  load_ao_dma(dev, cmd);
3376 
3377  dma_start_sync(dev, 0);
3378 
3379  return 0;
3380 }
3381 
3382 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3383 {
3384  if (dev->read_subdev->busy)
3385  return 0;
3386  if (board(dev)->layout == LAYOUT_4020)
3387  return 0;
3388  else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3389  return 0;
3390  return 1;
3391 }
3392 
3393 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3394 {
3395  struct comedi_cmd *cmd = &s->async->cmd;
3396 
3397  if (external_ai_queue_in_use(dev)) {
3398  warn_external_queue(dev);
3399  return -EBUSY;
3400  }
3401  /* disable analog output system during setup */
3402  writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3403 
3404  priv(dev)->ao_dma_index = 0;
3405  priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len;
3406 
3407  set_dac_select_reg(dev, cmd);
3408  set_dac_interval_regs(dev, cmd);
3409  load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr |
3410  PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3411 
3412  set_dac_control1_reg(dev, cmd);
3413  s->async->inttrig = ao_inttrig;
3414 
3415  return 0;
3416 }
3417 
3418 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3419  unsigned int trig_num)
3420 {
3421  struct comedi_cmd *cmd = &s->async->cmd;
3422  int retval;
3423 
3424  if (trig_num != 0)
3425  return -EINVAL;
3426 
3427  retval = prep_ao_dma(dev, cmd);
3428  if (retval < 0)
3429  return -EPIPE;
3430 
3431  set_dac_control0_reg(dev, cmd);
3432 
3433  if (cmd->start_src == TRIG_INT)
3434  writew(0, priv(dev)->main_iobase + DAC_START_REG);
3435 
3436  s->async->inttrig = NULL;
3437 
3438  return 0;
3439 }
3440 
3441 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3442  struct comedi_cmd *cmd)
3443 {
3444  int err = 0;
3445  unsigned int tmp_arg;
3446  int i;
3447 
3448  /* Step 1 : check if triggers are trivially valid */
3449 
3450  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3451  err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3452  TRIG_TIMER | TRIG_EXT);
3453  err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3454  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3455  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3456 
3457  if (err)
3458  return 1;
3459 
3460  /* Step 2a : make sure trigger sources are unique */
3461 
3462  err |= cfc_check_trigger_is_unique(cmd->start_src);
3463  err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3464 
3465  /* Step 2b : and mutually compatible */
3466 
3467  if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3468  err |= -EINVAL;
3469  if (cmd->stop_src != TRIG_COUNT &&
3470  cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3471  err |= -EINVAL;
3472 
3473  if (err)
3474  return 2;
3475 
3476  /* step 3: make sure arguments are trivially compatible */
3477 
3478  if (cmd->scan_begin_src == TRIG_TIMER) {
3479  if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3480  cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3481  err++;
3482  }
3483  if (get_ao_divisor(cmd->scan_begin_arg,
3484  cmd->flags) > max_counter_value) {
3485  cmd->scan_begin_arg =
3486  (max_counter_value + 2) * TIMER_BASE;
3487  err++;
3488  }
3489  }
3490 
3491  if (!cmd->chanlist_len) {
3492  cmd->chanlist_len = 1;
3493  err++;
3494  }
3495  if (cmd->scan_end_arg != cmd->chanlist_len) {
3496  cmd->scan_end_arg = cmd->chanlist_len;
3497  err++;
3498  }
3499 
3500  if (err)
3501  return 3;
3502 
3503  /* step 4: fix up any arguments */
3504 
3505  if (cmd->scan_begin_src == TRIG_TIMER) {
3506  tmp_arg = cmd->scan_begin_arg;
3507  cmd->scan_begin_arg =
3508  get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE;
3509  if (tmp_arg != cmd->scan_begin_arg)
3510  err++;
3511  }
3512 
3513  if (err)
3514  return 4;
3515 
3516  if (cmd->chanlist) {
3517  unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3518  for (i = 1; i < cmd->chanlist_len; i++) {
3519  if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3520  comedi_error(dev,
3521  "chanlist must use consecutive channels");
3522  err++;
3523  break;
3524  }
3525  }
3526  }
3527 
3528  if (err)
3529  return 5;
3530 
3531  return 0;
3532 }
3533 
3534 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3535 {
3536  writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3537  abort_dma(dev, 0);
3538  return 0;
3539 }
3540 
3541 static int dio_callback(int dir, int port, int data, unsigned long arg)
3542 {
3543  void __iomem *iobase = (void __iomem *)arg;
3544  if (dir) {
3545  writeb(data, iobase + port);
3546  DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3547  return 0;
3548  } else {
3549  return readb(iobase + port);
3550  }
3551 }
3552 
3553 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3554 {
3555  void __iomem *iobase = (void __iomem *)arg;
3556  if (dir) {
3557  writew(data, iobase + 2 * port);
3558  return 0;
3559  } else {
3560  return readw(iobase + 2 * port);
3561  }
3562 }
3563 
3564 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3565  struct comedi_insn *insn, unsigned int *data)
3566 {
3567  unsigned int bits;
3568 
3569  bits = readb(priv(dev)->dio_counter_iobase + DI_REG);
3570  bits &= 0xf;
3571  data[1] = bits;
3572  data[0] = 0;
3573 
3574  return insn->n;
3575 }
3576 
3577 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3578  struct comedi_insn *insn, unsigned int *data)
3579 {
3580  data[0] &= 0xf;
3581  /* zero bits we are going to change */
3582  s->state &= ~data[0];
3583  /* set new bits */
3584  s->state |= data[0] & data[1];
3585 
3586  writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG);
3587 
3588  data[1] = s->state;
3589 
3590  return insn->n;
3591 }
3592 
3593 static int dio_60xx_config_insn(struct comedi_device *dev,
3594  struct comedi_subdevice *s,
3595  struct comedi_insn *insn, unsigned int *data)
3596 {
3597  unsigned int mask;
3598 
3599  mask = 1 << CR_CHAN(insn->chanspec);
3600 
3601  switch (data[0]) {
3602  case INSN_CONFIG_DIO_INPUT:
3603  s->io_bits &= ~mask;
3604  break;
3605  case INSN_CONFIG_DIO_OUTPUT:
3606  s->io_bits |= mask;
3607  break;
3608  case INSN_CONFIG_DIO_QUERY:
3609  data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3610  return 2;
3611  default:
3612  return -EINVAL;
3613  }
3614 
3615  writeb(s->io_bits,
3616  priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3617 
3618  return 1;
3619 }
3620 
3621 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3622  struct comedi_insn *insn, unsigned int *data)
3623 {
3624  if (data[0]) {
3625  s->state &= ~data[0];
3626  s->state |= (data[0] & data[1]);
3627  writeb(s->state,
3628  priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3629  }
3630 
3631  data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3632 
3633  return insn->n;
3634 }
3635 
3636 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3637  unsigned int value)
3638 {
3639  priv(dev)->caldac_state[channel] = value;
3640 
3641  switch (board(dev)->layout) {
3642  case LAYOUT_60XX:
3643  case LAYOUT_64XX:
3644  caldac_8800_write(dev, channel, value);
3645  break;
3646  case LAYOUT_4020:
3647  caldac_i2c_write(dev, channel, value);
3648  break;
3649  default:
3650  break;
3651  }
3652 }
3653 
3654 static int calib_write_insn(struct comedi_device *dev,
3655  struct comedi_subdevice *s,
3656  struct comedi_insn *insn, unsigned int *data)
3657 {
3658  int channel = CR_CHAN(insn->chanspec);
3659 
3660  /* return immediately if setting hasn't changed, since
3661  * programming these things is slow */
3662  if (priv(dev)->caldac_state[channel] == data[0])
3663  return 1;
3664 
3665  caldac_write(dev, channel, data[0]);
3666 
3667  return 1;
3668 }
3669 
3670 static int calib_read_insn(struct comedi_device *dev,
3671  struct comedi_subdevice *s, struct comedi_insn *insn,
3672  unsigned int *data)
3673 {
3674  unsigned int channel = CR_CHAN(insn->chanspec);
3675 
3676  data[0] = priv(dev)->caldac_state[channel];
3677 
3678  return 1;
3679 }
3680 
3681 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3682  unsigned int value)
3683 {
3684  static const int bitstream_length = 10;
3685  unsigned int bit, register_bits;
3686  unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3687  static const int ad8402_udelay = 1;
3688 
3689  priv(dev)->ad8402_state[channel] = value;
3690 
3691  register_bits = SELECT_8402_64XX_BIT;
3692  udelay(ad8402_udelay);
3693  writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3694 
3695  for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3696  if (bitstream & bit)
3697  register_bits |= SERIAL_DATA_IN_BIT;
3698  else
3699  register_bits &= ~SERIAL_DATA_IN_BIT;
3700  udelay(ad8402_udelay);
3701  writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3702  udelay(ad8402_udelay);
3703  writew(register_bits | SERIAL_CLOCK_BIT,
3704  priv(dev)->main_iobase + CALIBRATION_REG);
3705  }
3706 
3707  udelay(ad8402_udelay);
3708  writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3709 }
3710 
3711 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3712 static int ad8402_write_insn(struct comedi_device *dev,
3713  struct comedi_subdevice *s,
3714  struct comedi_insn *insn, unsigned int *data)
3715 {
3716  int channel = CR_CHAN(insn->chanspec);
3717 
3718  /* return immediately if setting hasn't changed, since
3719  * programming these things is slow */
3720  if (priv(dev)->ad8402_state[channel] == data[0])
3721  return 1;
3722 
3723  priv(dev)->ad8402_state[channel] = data[0];
3724 
3725  ad8402_write(dev, channel, data[0]);
3726 
3727  return 1;
3728 }
3729 
3730 static int ad8402_read_insn(struct comedi_device *dev,
3731  struct comedi_subdevice *s,
3732  struct comedi_insn *insn, unsigned int *data)
3733 {
3734  unsigned int channel = CR_CHAN(insn->chanspec);
3735 
3736  data[0] = priv(dev)->ad8402_state[channel];
3737 
3738  return 1;
3739 }
3740 
3741 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3742 {
3743  static const int bitstream_length = 11;
3744  static const int read_command = 0x6;
3745  unsigned int bitstream = (read_command << 8) | address;
3746  unsigned int bit;
3747  void __iomem * const plx_control_addr =
3748  priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
3749  uint16_t value;
3750  static const int value_length = 16;
3751  static const int eeprom_udelay = 1;
3752 
3753  udelay(eeprom_udelay);
3754  priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3755  /* make sure we don't send anything to the i2c bus on 4020 */
3756  priv(dev)->plx_control_bits |= CTL_USERO;
3757  writel(priv(dev)->plx_control_bits, plx_control_addr);
3758  /* activate serial eeprom */
3759  udelay(eeprom_udelay);
3760  priv(dev)->plx_control_bits |= CTL_EE_CS;
3761  writel(priv(dev)->plx_control_bits, plx_control_addr);
3762 
3763  /* write read command and desired memory address */
3764  for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3765  /* set bit to be written */
3766  udelay(eeprom_udelay);
3767  if (bitstream & bit)
3768  priv(dev)->plx_control_bits |= CTL_EE_W;
3769  else
3770  priv(dev)->plx_control_bits &= ~CTL_EE_W;
3771  writel(priv(dev)->plx_control_bits, plx_control_addr);
3772  /* clock in bit */
3773  udelay(eeprom_udelay);
3774  priv(dev)->plx_control_bits |= CTL_EE_CLK;
3775  writel(priv(dev)->plx_control_bits, plx_control_addr);
3776  udelay(eeprom_udelay);
3777  priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3778  writel(priv(dev)->plx_control_bits, plx_control_addr);
3779  }
3780  /* read back value from eeprom memory location */
3781  value = 0;
3782  for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3783  /* clock out bit */
3784  udelay(eeprom_udelay);
3785  priv(dev)->plx_control_bits |= CTL_EE_CLK;
3786  writel(priv(dev)->plx_control_bits, plx_control_addr);
3787  udelay(eeprom_udelay);
3788  priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3789  writel(priv(dev)->plx_control_bits, plx_control_addr);
3790  udelay(eeprom_udelay);
3791  if (readl(plx_control_addr) & CTL_EE_R)
3792  value |= bit;
3793  }
3794 
3795  /* deactivate eeprom serial input */
3796  udelay(eeprom_udelay);
3797  priv(dev)->plx_control_bits &= ~CTL_EE_CS;
3798  writel(priv(dev)->plx_control_bits, plx_control_addr);
3799 
3800  return value;
3801 }
3802 
3803 static int eeprom_read_insn(struct comedi_device *dev,
3804  struct comedi_subdevice *s,
3805  struct comedi_insn *insn, unsigned int *data)
3806 {
3807  data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3808 
3809  return 1;
3810 }
3811 
3812 /* utility function that rounds desired timing to an achievable time, and
3813  * sets cmd members appropriately.
3814  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3815  */
3816 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3817 {
3818  unsigned int convert_divisor = 0, scan_divisor;
3819  static const int min_convert_divisor = 3;
3820  static const int max_convert_divisor =
3821  max_counter_value + min_convert_divisor;
3822  static const int min_scan_divisor_4020 = 2;
3823  unsigned long long max_scan_divisor, min_scan_divisor;
3824 
3825  if (cmd->convert_src == TRIG_TIMER) {
3826  if (board(dev)->layout == LAYOUT_4020) {
3827  cmd->convert_arg = 0;
3828  } else {
3829  convert_divisor =
3830  get_divisor(cmd->convert_arg, cmd->flags);
3831  if (convert_divisor > max_convert_divisor)
3832  convert_divisor = max_convert_divisor;
3833  if (convert_divisor < min_convert_divisor)
3834  convert_divisor = min_convert_divisor;
3835  cmd->convert_arg = convert_divisor * TIMER_BASE;
3836  }
3837  } else if (cmd->convert_src == TRIG_NOW)
3838  cmd->convert_arg = 0;
3839 
3840  if (cmd->scan_begin_src == TRIG_TIMER) {
3841  scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3842  if (cmd->convert_src == TRIG_TIMER) {
3843  /* XXX check for integer overflows */
3844  min_scan_divisor = convert_divisor * cmd->chanlist_len;
3845  max_scan_divisor =
3846  (convert_divisor * cmd->chanlist_len - 1) +
3847  max_counter_value;
3848  } else {
3849  min_scan_divisor = min_scan_divisor_4020;
3850  max_scan_divisor = max_counter_value + min_scan_divisor;
3851  }
3852  if (scan_divisor > max_scan_divisor)
3853  scan_divisor = max_scan_divisor;
3854  if (scan_divisor < min_scan_divisor)
3855  scan_divisor = min_scan_divisor;
3856  cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3857  }
3858 
3859  return;
3860 }
3861 
3862 /* Gets nearest achievable timing given master clock speed, does not
3863  * take into account possible minimum/maximum divisor values. Used
3864  * by other timing checking functions. */
3865 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3866 {
3867  unsigned int divisor;
3868 
3869  switch (flags & TRIG_ROUND_MASK) {
3870  case TRIG_ROUND_UP:
3871  divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
3872  break;
3873  case TRIG_ROUND_DOWN:
3874  divisor = ns / TIMER_BASE;
3875  break;
3876  case TRIG_ROUND_NEAREST:
3877  default:
3878  divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
3879  break;
3880  }
3881  return divisor;
3882 }
3883 
3884 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3885 {
3886  return get_divisor(ns, flags) - 2;
3887 }
3888 
3889 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
3890 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
3891 {
3892  unsigned int num_fifo_entries;
3893  int retval;
3894  const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3895 
3896  num_fifo_entries = num_samples / fifo->sample_packing_ratio;
3897 
3898  retval = set_ai_fifo_segment_length(dev,
3899  num_fifo_entries /
3900  fifo->num_segments);
3901  if (retval < 0)
3902  return retval;
3903 
3904  num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
3905 
3906  DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
3907 
3908  return num_samples;
3909 }
3910 
3911 /* query length of fifo */
3912 static unsigned int ai_fifo_size(struct comedi_device *dev)
3913 {
3914  return priv(dev)->ai_fifo_segment_length *
3915  board(dev)->ai_fifo->num_segments *
3916  board(dev)->ai_fifo->sample_packing_ratio;
3917 }
3918 
3919 static int set_ai_fifo_segment_length(struct comedi_device *dev,
3920  unsigned int num_entries)
3921 {
3922  static const int increment_size = 0x100;
3923  const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3924  unsigned int num_increments;
3925  uint16_t bits;
3926 
3927  if (num_entries < increment_size)
3928  num_entries = increment_size;
3929  if (num_entries > fifo->max_segment_length)
3930  num_entries = fifo->max_segment_length;
3931 
3932  /* 1 == 256 entries, 2 == 512 entries, etc */
3933  num_increments = (num_entries + increment_size / 2) / increment_size;
3934 
3935  bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
3936  priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
3937  priv(dev)->fifo_size_bits |= bits;
3938  writew(priv(dev)->fifo_size_bits,
3939  priv(dev)->main_iobase + FIFO_SIZE_REG);
3940 
3941  priv(dev)->ai_fifo_segment_length = num_increments * increment_size;
3942 
3943  DEBUG_PRINT("set hardware fifo segment length to %i\n",
3944  priv(dev)->ai_fifo_segment_length);
3945 
3946  return priv(dev)->ai_fifo_segment_length;
3947 }
3948 
3949 /* pci-6025 8800 caldac:
3950  * address 0 == dac channel 0 offset
3951  * address 1 == dac channel 0 gain
3952  * address 2 == dac channel 1 offset
3953  * address 3 == dac channel 1 gain
3954  * address 4 == fine adc offset
3955  * address 5 == coarse adc offset
3956  * address 6 == coarse adc gain
3957  * address 7 == fine adc gain
3958  */
3959 /* pci-6402/16 uses all 8 channels for dac:
3960  * address 0 == dac channel 0 fine gain
3961  * address 1 == dac channel 0 coarse gain
3962  * address 2 == dac channel 0 coarse offset
3963  * address 3 == dac channel 1 coarse offset
3964  * address 4 == dac channel 1 fine gain
3965  * address 5 == dac channel 1 coarse gain
3966  * address 6 == dac channel 0 fine offset
3967  * address 7 == dac channel 1 fine offset
3968 */
3969 
3970 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3971  uint8_t value)
3972 {
3973  static const int num_caldac_channels = 8;
3974  static const int bitstream_length = 11;
3975  unsigned int bitstream = ((address & 0x7) << 8) | value;
3976  unsigned int bit, register_bits;
3977  static const int caldac_8800_udelay = 1;
3978 
3979  if (address >= num_caldac_channels) {
3980  comedi_error(dev, "illegal caldac channel");
3981  return -1;
3982  }
3983  for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3984  register_bits = 0;
3985  if (bitstream & bit)
3986  register_bits |= SERIAL_DATA_IN_BIT;
3987  udelay(caldac_8800_udelay);
3988  writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3989  register_bits |= SERIAL_CLOCK_BIT;
3990  udelay(caldac_8800_udelay);
3991  writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3992  }
3993  udelay(caldac_8800_udelay);
3994  writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
3995  udelay(caldac_8800_udelay);
3996  writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3997  udelay(caldac_8800_udelay);
3998  return 0;
3999 }
4000 
4001 /* 4020 caldacs */
4002 static int caldac_i2c_write(struct comedi_device *dev,
4003  unsigned int caldac_channel, unsigned int value)
4004 {
4005  uint8_t serial_bytes[3];
4006  uint8_t i2c_addr;
4007  enum pointer_bits {
4008  /* manual has gain and offset bits switched */
4009  OFFSET_0_2 = 0x1,
4010  GAIN_0_2 = 0x2,
4011  OFFSET_1_3 = 0x4,
4012  GAIN_1_3 = 0x8,
4013  };
4014  enum data_bits {
4015  NOT_CLEAR_REGISTERS = 0x20,
4016  };
4017 
4018  switch (caldac_channel) {
4019  case 0: /* chan 0 offset */
4020  i2c_addr = CALDAC0_I2C_ADDR;
4021  serial_bytes[0] = OFFSET_0_2;
4022  break;
4023  case 1: /* chan 1 offset */
4024  i2c_addr = CALDAC0_I2C_ADDR;
4025  serial_bytes[0] = OFFSET_1_3;
4026  break;
4027  case 2: /* chan 2 offset */
4028  i2c_addr = CALDAC1_I2C_ADDR;
4029  serial_bytes[0] = OFFSET_0_2;
4030  break;
4031  case 3: /* chan 3 offset */
4032  i2c_addr = CALDAC1_I2C_ADDR;
4033  serial_bytes[0] = OFFSET_1_3;
4034  break;
4035  case 4: /* chan 0 gain */
4036  i2c_addr = CALDAC0_I2C_ADDR;
4037  serial_bytes[0] = GAIN_0_2;
4038  break;
4039  case 5: /* chan 1 gain */
4040  i2c_addr = CALDAC0_I2C_ADDR;
4041  serial_bytes[0] = GAIN_1_3;
4042  break;
4043  case 6: /* chan 2 gain */
4044  i2c_addr = CALDAC1_I2C_ADDR;
4045  serial_bytes[0] = GAIN_0_2;
4046  break;
4047  case 7: /* chan 3 gain */
4048  i2c_addr = CALDAC1_I2C_ADDR;
4049  serial_bytes[0] = GAIN_1_3;
4050  break;
4051  default:
4052  comedi_error(dev, "invalid caldac channel\n");
4053  return -1;
4054  break;
4055  }
4056  serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4057  serial_bytes[2] = value & 0xff;
4058  i2c_write(dev, i2c_addr, serial_bytes, 3);
4059  return 0;
4060 }
4061 
4062 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4063 static const int i2c_high_udelay = 1000;
4064 static const int i2c_low_udelay = 10;
4065 
4066 /* set i2c data line high or low */
4067 static void i2c_set_sda(struct comedi_device *dev, int state)
4068 {
4069  static const int data_bit = CTL_EE_W;
4070  void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4071  PLX_CONTROL_REG;
4072 
4073  if (state) {
4074  /* set data line high */
4075  priv(dev)->plx_control_bits &= ~data_bit;
4076  writel(priv(dev)->plx_control_bits, plx_control_addr);
4077  udelay(i2c_high_udelay);
4078  } else { /* set data line low */
4079 
4080  priv(dev)->plx_control_bits |= data_bit;
4081  writel(priv(dev)->plx_control_bits, plx_control_addr);
4082  udelay(i2c_low_udelay);
4083  }
4084 }
4085 
4086 /* set i2c clock line high or low */
4087 static void i2c_set_scl(struct comedi_device *dev, int state)
4088 {
4089  static const int clock_bit = CTL_USERO;
4090  void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4091  PLX_CONTROL_REG;
4092 
4093  if (state) {
4094  /* set clock line high */
4095  priv(dev)->plx_control_bits &= ~clock_bit;
4096  writel(priv(dev)->plx_control_bits, plx_control_addr);
4097  udelay(i2c_high_udelay);
4098  } else { /* set clock line low */
4099 
4100  priv(dev)->plx_control_bits |= clock_bit;
4101  writel(priv(dev)->plx_control_bits, plx_control_addr);
4102  udelay(i2c_low_udelay);
4103  }
4104 }
4105 
4106 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
4107 {
4108  uint8_t bit;
4109  unsigned int num_bits = 8;
4110 
4111  DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4112 
4113  for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4114  i2c_set_scl(dev, 0);
4115  if ((byte & bit))
4116  i2c_set_sda(dev, 1);
4117  else
4118  i2c_set_sda(dev, 0);
4119  i2c_set_scl(dev, 1);
4120  }
4121 }
4122 
4123 /* we can't really read the lines, so fake it */
4124 static int i2c_read_ack(struct comedi_device *dev)
4125 {
4126  i2c_set_scl(dev, 0);
4127  i2c_set_sda(dev, 1);
4128  i2c_set_scl(dev, 1);
4129 
4130  return 0; /* return fake acknowledge bit */
4131 }
4132 
4133 /* send start bit */
4134 static void i2c_start(struct comedi_device *dev)
4135 {
4136  i2c_set_scl(dev, 1);
4137  i2c_set_sda(dev, 1);
4138  i2c_set_sda(dev, 0);
4139 }
4140 
4141 /* send stop bit */
4142 static void i2c_stop(struct comedi_device *dev)
4143 {
4144  i2c_set_scl(dev, 0);
4145  i2c_set_sda(dev, 0);
4146  i2c_set_scl(dev, 1);
4147  i2c_set_sda(dev, 1);
4148 }
4149 
4150 static void i2c_write(struct comedi_device *dev, unsigned int address,
4151  const uint8_t *data, unsigned int length)
4152 {
4153  unsigned int i;
4154  uint8_t bitstream;
4155  static const int read_bit = 0x1;
4156 
4157 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4158 
4159  /* make sure we dont send anything to eeprom */
4160  priv(dev)->plx_control_bits &= ~CTL_EE_CS;
4161 
4162  i2c_stop(dev);
4163  i2c_start(dev);
4164 
4165  /* send address and write bit */
4166  bitstream = (address << 1) & ~read_bit;
4167  i2c_write_byte(dev, bitstream);
4168 
4169  /* get acknowledge */
4170  if (i2c_read_ack(dev) != 0) {
4171  comedi_error(dev, "i2c write failed: no acknowledge");
4172  i2c_stop(dev);
4173  return;
4174  }
4175  /* write data bytes */
4176  for (i = 0; i < length; i++) {
4177  i2c_write_byte(dev, data[i]);
4178  if (i2c_read_ack(dev) != 0) {
4179  comedi_error(dev, "i2c write failed: no acknowledge");
4180  i2c_stop(dev);
4181  return;
4182  }
4183  }
4184  i2c_stop(dev);
4185 }
4186 
4187 static struct comedi_driver cb_pcidas64_driver = {
4188  .driver_name = "cb_pcidas64",
4189  .module = THIS_MODULE,
4190  .attach = attach,
4191  .detach = detach,
4192 };
4193 
4194 static int __devinit cb_pcidas64_pci_probe(struct pci_dev *dev,
4195  const struct pci_device_id *ent)
4196 {
4197  return comedi_pci_auto_config(dev, &cb_pcidas64_driver);
4198 }
4199 
4200 static void __devexit cb_pcidas64_pci_remove(struct pci_dev *dev)
4201 {
4202  comedi_pci_auto_unconfig(dev);
4203 }
4204 
4205 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4206  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d) },
4207  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e) },
4208  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035) },
4209  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036) },
4210  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037) },
4211  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052) },
4212  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d) },
4213  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e) },
4214  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f) },
4215  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061) },
4216  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062) },
4217  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063) },
4218  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064) },
4219  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066) },
4220  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067) },
4221  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068) },
4222  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f) },
4223  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078) },
4224  { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079) },
4225  { 0 }
4226 };
4227 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4228 
4229 static struct pci_driver cb_pcidas64_pci_driver = {
4230  .name = "cb_pcidas64",
4231  .id_table = cb_pcidas64_pci_table,
4232  .probe = cb_pcidas64_pci_probe,
4233  .remove = __devexit_p(cb_pcidas64_pci_remove),
4234 };
4235 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4236 
4237 MODULE_AUTHOR("Comedi http://www.comedi.org");
4238 MODULE_DESCRIPTION("Comedi low-level driver");
4239 MODULE_LICENSE("GPL");
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