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#define CCISS_BOARD_NOT_READY_ITERATIONS |
#define CCISS_BOARD_NOT_READY_WAIT_SECS (100) |
#define CCISS_BOARD_READY_ITERATIONS |
#define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100) |
#define CCISS_BOARD_READY_WAIT_SECS (120) |
#define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ |
#define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (4000) |
#define CCISS_POST_RESET_NOOP_RETRIES (12) |
#define CCISS_POST_RESET_NOOP_TIMEOUT_MSECS (10000) |
#define CCISS_POST_RESET_PAUSE_MSECS (3000) |
#define CISS_ERROR_BIT 0x02 |
#define FIFO_EMPTY 0xffffffff |
#define SA5_CTCFG_OFFSET 0xB4 |
#define SA5_CTMEM_OFFSET 0xB8 |
#define SA5_DOORBELL 0x20 |
#define SA5_INTR_OFF 0x08 |
#define SA5_INTR_PENDING 0x08 |
#define SA5_INTR_STATUS 0x30 |
#define SA5_OUTDB_CLEAR 0xA0 |
#define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
#define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
#define SA5_OUTDB_STATUS 0x9C |
#define SA5_OUTDB_STATUS_PERF_BIT 0x01 |
#define SA5_PERF_INTR_OFF 0x05 |
#define SA5_PERF_INTR_PENDING 0x04 |
#define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
#define SA5_REPLY_PORT_OFFSET 0x44 |
#define SA5_REQUEST_PORT_OFFSET 0x40 |
#define SA5_SCRATCHPAD_OFFSET 0xB0 |
#define SA5B_INTR_OFF 0x04 |
#define SA5B_INTR_PENDING 0x04 |
#define SIMPLE_MODE_INT 2 |