Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
clock-exynos5.c
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3  * http://www.samsung.com
4  *
5  * Clock support for EXYNOS5 SoCs
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10 */
11 
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/syscore_ops.h>
16 
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
19 #include <plat/cpu.h>
20 #include <plat/pll.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
23 #include <plat/pm.h>
24 
25 #include <mach/map.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
28 
29 #include "common.h"
30 
31 #ifdef CONFIG_PM_SLEEP
32 static struct sleep_save exynos5_clock_save[] = {
33  SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
34  SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
35  SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
36  SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
37  SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
38  SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
39  SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
40  SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
41  SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
42  SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
43  SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
44  SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
45  SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
46  SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
47  SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
48  SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
49  SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
50  SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
51  SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
52  SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
53  SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
54  SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
55  SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
56  SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
57  SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
58  SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
59  SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
60  SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
61  SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
62  SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
63  SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
64  SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
65  SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
66  SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
67  SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
68  SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
69  SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
70  SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
71  SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
72  SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
73  SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
74  SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
75  SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
76  SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
77  SAVE_ITEM(EXYNOS5_EPLL_CON0),
78  SAVE_ITEM(EXYNOS5_EPLL_CON1),
79  SAVE_ITEM(EXYNOS5_EPLL_CON2),
80  SAVE_ITEM(EXYNOS5_VPLL_CON0),
81  SAVE_ITEM(EXYNOS5_VPLL_CON1),
82  SAVE_ITEM(EXYNOS5_VPLL_CON2),
83 };
84 #endif
85 
86 static struct clk exynos5_clk_sclk_dptxphy = {
87  .name = "sclk_dptx",
88 };
89 
90 static struct clk exynos5_clk_sclk_hdmi24m = {
91  .name = "sclk_hdmi24m",
92  .rate = 24000000,
93 };
94 
95 static struct clk exynos5_clk_sclk_hdmi27m = {
96  .name = "sclk_hdmi27m",
97  .rate = 27000000,
98 };
99 
100 static struct clk exynos5_clk_sclk_hdmiphy = {
101  .name = "sclk_hdmiphy",
102 };
103 
104 static struct clk exynos5_clk_sclk_usbphy = {
105  .name = "sclk_usbphy",
106  .rate = 48000000,
107 };
108 
109 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
110 {
111  return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
112 }
113 
114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
115 {
116  return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
117 }
118 
119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
120 {
121  return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
122 }
123 
124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
125 {
126  return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
127 }
128 
129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
130 {
131  return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
132 }
133 
134 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
135 {
136  return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
137 }
138 
139 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
140 {
141  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
142 }
143 
144 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
145 {
146  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
147 }
148 
149 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
150 {
151  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
152 }
153 
154 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
155 {
156  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
157 }
158 
159 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
160 {
161  return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
162 }
163 
164 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
165 {
166  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
167 }
168 
169 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
170 {
171  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
172 }
173 
174 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
175 {
176  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
177 }
178 
179 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
180 {
181  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
182 }
183 
184 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
185 {
186  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
187 }
188 
189 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
190 {
191  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
192 }
193 
194 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
195 {
196  return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
197 }
198 
199 /* Core list of CMU_CPU side */
200 
201 static struct clksrc_clk exynos5_clk_mout_apll = {
202  .clk = {
203  .name = "mout_apll",
204  },
205  .sources = &clk_src_apll,
206  .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
207 };
208 
209 static struct clksrc_clk exynos5_clk_sclk_apll = {
210  .clk = {
211  .name = "sclk_apll",
212  .parent = &exynos5_clk_mout_apll.clk,
213  },
214  .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
215 };
216 
217 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
218  .clk = {
219  .name = "mout_bpll_fout",
220  },
221  .sources = &clk_src_bpll_fout,
222  .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
223 };
224 
225 static struct clk *exynos5_clk_src_bpll_list[] = {
226  [0] = &clk_fin_bpll,
227  [1] = &exynos5_clk_mout_bpll_fout.clk,
228 };
229 
230 static struct clksrc_sources exynos5_clk_src_bpll = {
231  .sources = exynos5_clk_src_bpll_list,
232  .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
233 };
234 
235 static struct clksrc_clk exynos5_clk_mout_bpll = {
236  .clk = {
237  .name = "mout_bpll",
238  },
239  .sources = &exynos5_clk_src_bpll,
240  .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
241 };
242 
243 static struct clk *exynos5_clk_src_bpll_user_list[] = {
244  [0] = &clk_fin_mpll,
245  [1] = &exynos5_clk_mout_bpll.clk,
246 };
247 
248 static struct clksrc_sources exynos5_clk_src_bpll_user = {
249  .sources = exynos5_clk_src_bpll_user_list,
250  .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
251 };
252 
253 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
254  .clk = {
255  .name = "mout_bpll_user",
256  },
257  .sources = &exynos5_clk_src_bpll_user,
258  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
259 };
260 
261 static struct clksrc_clk exynos5_clk_mout_cpll = {
262  .clk = {
263  .name = "mout_cpll",
264  },
265  .sources = &clk_src_cpll,
266  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
267 };
268 
269 static struct clksrc_clk exynos5_clk_mout_epll = {
270  .clk = {
271  .name = "mout_epll",
272  },
273  .sources = &clk_src_epll,
274  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
275 };
276 
277 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
278  .clk = {
279  .name = "mout_mpll_fout",
280  },
281  .sources = &clk_src_mpll_fout,
282  .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
283 };
284 
285 static struct clk *exynos5_clk_src_mpll_list[] = {
286  [0] = &clk_fin_mpll,
287  [1] = &exynos5_clk_mout_mpll_fout.clk,
288 };
289 
290 static struct clksrc_sources exynos5_clk_src_mpll = {
291  .sources = exynos5_clk_src_mpll_list,
292  .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
293 };
294 
295 struct clksrc_clk exynos5_clk_mout_mpll = {
296  .clk = {
297  .name = "mout_mpll",
298  },
299  .sources = &exynos5_clk_src_mpll,
300  .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
301 };
302 
303 static struct clk *exynos_clkset_vpllsrc_list[] = {
304  [0] = &clk_fin_vpll,
305  [1] = &exynos5_clk_sclk_hdmi27m,
306 };
307 
308 static struct clksrc_sources exynos5_clkset_vpllsrc = {
309  .sources = exynos_clkset_vpllsrc_list,
310  .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
311 };
312 
313 static struct clksrc_clk exynos5_clk_vpllsrc = {
314  .clk = {
315  .name = "vpll_src",
316  .enable = exynos5_clksrc_mask_top_ctrl,
317  .ctrlbit = (1 << 0),
318  },
319  .sources = &exynos5_clkset_vpllsrc,
320  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
321 };
322 
323 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
324  [0] = &exynos5_clk_vpllsrc.clk,
325  [1] = &clk_fout_vpll,
326 };
327 
328 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
329  .sources = exynos5_clkset_sclk_vpll_list,
330  .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
331 };
332 
333 static struct clksrc_clk exynos5_clk_sclk_vpll = {
334  .clk = {
335  .name = "sclk_vpll",
336  },
337  .sources = &exynos5_clkset_sclk_vpll,
338  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
339 };
340 
341 static struct clksrc_clk exynos5_clk_sclk_pixel = {
342  .clk = {
343  .name = "sclk_pixel",
344  .parent = &exynos5_clk_sclk_vpll.clk,
345  },
346  .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
347 };
348 
349 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
350  [0] = &exynos5_clk_sclk_pixel.clk,
351  [1] = &exynos5_clk_sclk_hdmiphy,
352 };
353 
354 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
355  .sources = exynos5_clkset_sclk_hdmi_list,
356  .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
357 };
358 
359 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
360  .clk = {
361  .name = "sclk_hdmi",
362  .enable = exynos5_clksrc_mask_disp1_0_ctrl,
363  .ctrlbit = (1 << 20),
364  },
365  .sources = &exynos5_clkset_sclk_hdmi,
366  .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
367 };
368 
369 static struct clksrc_clk *exynos5_sclk_tv[] = {
370  &exynos5_clk_sclk_pixel,
371  &exynos5_clk_sclk_hdmi,
372 };
373 
374 static struct clk *exynos5_clk_src_mpll_user_list[] = {
375  [0] = &clk_fin_mpll,
376  [1] = &exynos5_clk_mout_mpll.clk,
377 };
378 
379 static struct clksrc_sources exynos5_clk_src_mpll_user = {
380  .sources = exynos5_clk_src_mpll_user_list,
381  .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
382 };
383 
384 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
385  .clk = {
386  .name = "mout_mpll_user",
387  },
388  .sources = &exynos5_clk_src_mpll_user,
389  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
390 };
391 
392 static struct clk *exynos5_clkset_mout_cpu_list[] = {
393  [0] = &exynos5_clk_mout_apll.clk,
394  [1] = &exynos5_clk_mout_mpll.clk,
395 };
396 
397 static struct clksrc_sources exynos5_clkset_mout_cpu = {
398  .sources = exynos5_clkset_mout_cpu_list,
399  .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
400 };
401 
402 static struct clksrc_clk exynos5_clk_mout_cpu = {
403  .clk = {
404  .name = "mout_cpu",
405  },
406  .sources = &exynos5_clkset_mout_cpu,
407  .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
408 };
409 
410 static struct clksrc_clk exynos5_clk_dout_armclk = {
411  .clk = {
412  .name = "dout_armclk",
413  .parent = &exynos5_clk_mout_cpu.clk,
414  },
415  .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
416 };
417 
418 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
419  .clk = {
420  .name = "dout_arm2clk",
421  .parent = &exynos5_clk_dout_armclk.clk,
422  },
423  .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
424 };
425 
426 static struct clk exynos5_clk_armclk = {
427  .name = "armclk",
428  .parent = &exynos5_clk_dout_arm2clk.clk,
429 };
430 
431 /* Core list of CMU_CDREX side */
432 
433 static struct clk *exynos5_clkset_cdrex_list[] = {
434  [0] = &exynos5_clk_mout_mpll.clk,
435  [1] = &exynos5_clk_mout_bpll.clk,
436 };
437 
438 static struct clksrc_sources exynos5_clkset_cdrex = {
439  .sources = exynos5_clkset_cdrex_list,
440  .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
441 };
442 
443 static struct clksrc_clk exynos5_clk_cdrex = {
444  .clk = {
445  .name = "clk_cdrex",
446  },
447  .sources = &exynos5_clkset_cdrex,
448  .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
449  .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
450 };
451 
452 static struct clksrc_clk exynos5_clk_aclk_acp = {
453  .clk = {
454  .name = "aclk_acp",
455  .parent = &exynos5_clk_mout_mpll.clk,
456  },
457  .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
458 };
459 
460 static struct clksrc_clk exynos5_clk_pclk_acp = {
461  .clk = {
462  .name = "pclk_acp",
463  .parent = &exynos5_clk_aclk_acp.clk,
464  },
465  .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
466 };
467 
468 /* Core list of CMU_TOP side */
469 
470 struct clk *exynos5_clkset_aclk_top_list[] = {
471  [0] = &exynos5_clk_mout_mpll_user.clk,
472  [1] = &exynos5_clk_mout_bpll_user.clk,
473 };
474 
475 struct clksrc_sources exynos5_clkset_aclk = {
476  .sources = exynos5_clkset_aclk_top_list,
477  .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
478 };
479 
480 static struct clksrc_clk exynos5_clk_aclk_400 = {
481  .clk = {
482  .name = "aclk_400",
483  },
484  .sources = &exynos5_clkset_aclk,
485  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
486  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
487 };
488 
489 struct clk *exynos5_clkset_aclk_333_166_list[] = {
490  [0] = &exynos5_clk_mout_cpll.clk,
491  [1] = &exynos5_clk_mout_mpll_user.clk,
492 };
493 
494 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
495  .sources = exynos5_clkset_aclk_333_166_list,
496  .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
497 };
498 
499 static struct clksrc_clk exynos5_clk_aclk_333 = {
500  .clk = {
501  .name = "aclk_333",
502  },
503  .sources = &exynos5_clkset_aclk_333_166,
504  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
505  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
506 };
507 
508 static struct clksrc_clk exynos5_clk_aclk_166 = {
509  .clk = {
510  .name = "aclk_166",
511  },
512  .sources = &exynos5_clkset_aclk_333_166,
513  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
514  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
515 };
516 
517 static struct clksrc_clk exynos5_clk_aclk_266 = {
518  .clk = {
519  .name = "aclk_266",
520  .parent = &exynos5_clk_mout_mpll_user.clk,
521  },
522  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
523 };
524 
525 static struct clksrc_clk exynos5_clk_aclk_200 = {
526  .clk = {
527  .name = "aclk_200",
528  },
529  .sources = &exynos5_clkset_aclk,
530  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
531  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
532 };
533 
534 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
535  .clk = {
536  .name = "aclk_66_pre",
537  .parent = &exynos5_clk_mout_mpll_user.clk,
538  },
539  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
540 };
541 
542 static struct clksrc_clk exynos5_clk_aclk_66 = {
543  .clk = {
544  .name = "aclk_66",
545  .parent = &exynos5_clk_aclk_66_pre.clk,
546  },
547  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
548 };
549 
550 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
551  .clk = {
552  .name = "mout_aclk_300_gscl_mid",
553  },
554  .sources = &exynos5_clkset_aclk,
555  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
556 };
557 
558 static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
559  [0] = &exynos5_clk_sclk_vpll.clk,
560  [1] = &exynos5_clk_mout_cpll.clk,
561 };
562 
563 static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
564  .sources = exynos5_clkset_aclk_300_mid1_list,
565  .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
566 };
567 
568 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
569  .clk = {
570  .name = "mout_aclk_300_gscl_mid1",
571  },
572  .sources = &exynos5_clkset_aclk_300_gscl_mid1,
573  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
574 };
575 
576 static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
577  [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
578  [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
579 };
580 
581 static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
582  .sources = exynos5_clkset_aclk_300_gscl_list,
583  .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
584 };
585 
586 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
587  .clk = {
588  .name = "mout_aclk_300_gscl",
589  },
590  .sources = &exynos5_clkset_aclk_300_gscl,
591  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
592 };
593 
594 static struct clk *exynos5_clk_src_gscl_300_list[] = {
595  [0] = &clk_ext_xtal_mux,
596  [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
597 };
598 
599 static struct clksrc_sources exynos5_clk_src_gscl_300 = {
600  .sources = exynos5_clk_src_gscl_300_list,
601  .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
602 };
603 
604 static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
605  .clk = {
606  .name = "aclk_300_gscl",
607  },
608  .sources = &exynos5_clk_src_gscl_300,
609  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
610 };
611 
612 static struct clk exynos5_init_clocks_off[] = {
613  {
614  .name = "timers",
615  .parent = &exynos5_clk_aclk_66.clk,
616  .enable = exynos5_clk_ip_peric_ctrl,
617  .ctrlbit = (1 << 24),
618  }, {
619  .name = "rtc",
620  .parent = &exynos5_clk_aclk_66.clk,
621  .enable = exynos5_clk_ip_peris_ctrl,
622  .ctrlbit = (1 << 20),
623  }, {
624  .name = "watchdog",
625  .parent = &exynos5_clk_aclk_66.clk,
626  .enable = exynos5_clk_ip_peris_ctrl,
627  .ctrlbit = (1 << 19),
628  }, {
629  .name = "biu", /* bus interface unit clock */
630  .devname = "dw_mmc.0",
631  .parent = &exynos5_clk_aclk_200.clk,
632  .enable = exynos5_clk_ip_fsys_ctrl,
633  .ctrlbit = (1 << 12),
634  }, {
635  .name = "biu",
636  .devname = "dw_mmc.1",
637  .parent = &exynos5_clk_aclk_200.clk,
638  .enable = exynos5_clk_ip_fsys_ctrl,
639  .ctrlbit = (1 << 13),
640  }, {
641  .name = "biu",
642  .devname = "dw_mmc.2",
643  .parent = &exynos5_clk_aclk_200.clk,
644  .enable = exynos5_clk_ip_fsys_ctrl,
645  .ctrlbit = (1 << 14),
646  }, {
647  .name = "biu",
648  .devname = "dw_mmc.3",
649  .parent = &exynos5_clk_aclk_200.clk,
650  .enable = exynos5_clk_ip_fsys_ctrl,
651  .ctrlbit = (1 << 15),
652  }, {
653  .name = "sata",
654  .devname = "ahci",
655  .enable = exynos5_clk_ip_fsys_ctrl,
656  .ctrlbit = (1 << 6),
657  }, {
658  .name = "sata_phy",
659  .enable = exynos5_clk_ip_fsys_ctrl,
660  .ctrlbit = (1 << 24),
661  }, {
662  .name = "sata_phy_i2c",
663  .enable = exynos5_clk_ip_fsys_ctrl,
664  .ctrlbit = (1 << 25),
665  }, {
666  .name = "mfc",
667  .devname = "s5p-mfc",
668  .enable = exynos5_clk_ip_mfc_ctrl,
669  .ctrlbit = (1 << 0),
670  }, {
671  .name = "hdmi",
672  .devname = "exynos4-hdmi",
673  .enable = exynos5_clk_ip_disp1_ctrl,
674  .ctrlbit = (1 << 6),
675  }, {
676  .name = "mixer",
677  .devname = "s5p-mixer",
678  .enable = exynos5_clk_ip_disp1_ctrl,
679  .ctrlbit = (1 << 5),
680  }, {
681  .name = "jpeg",
682  .enable = exynos5_clk_ip_gen_ctrl,
683  .ctrlbit = (1 << 2),
684  }, {
685  .name = "dsim0",
686  .enable = exynos5_clk_ip_disp1_ctrl,
687  .ctrlbit = (1 << 3),
688  }, {
689  .name = "iis",
690  .devname = "samsung-i2s.1",
691  .enable = exynos5_clk_ip_peric_ctrl,
692  .ctrlbit = (1 << 20),
693  }, {
694  .name = "iis",
695  .devname = "samsung-i2s.2",
696  .enable = exynos5_clk_ip_peric_ctrl,
697  .ctrlbit = (1 << 21),
698  }, {
699  .name = "pcm",
700  .devname = "samsung-pcm.1",
701  .enable = exynos5_clk_ip_peric_ctrl,
702  .ctrlbit = (1 << 22),
703  }, {
704  .name = "pcm",
705  .devname = "samsung-pcm.2",
706  .enable = exynos5_clk_ip_peric_ctrl,
707  .ctrlbit = (1 << 23),
708  }, {
709  .name = "spdif",
710  .devname = "samsung-spdif",
711  .enable = exynos5_clk_ip_peric_ctrl,
712  .ctrlbit = (1 << 26),
713  }, {
714  .name = "ac97",
715  .devname = "samsung-ac97",
716  .enable = exynos5_clk_ip_peric_ctrl,
717  .ctrlbit = (1 << 27),
718  }, {
719  .name = "usbhost",
720  .enable = exynos5_clk_ip_fsys_ctrl ,
721  .ctrlbit = (1 << 18),
722  }, {
723  .name = "usbotg",
724  .enable = exynos5_clk_ip_fsys_ctrl,
725  .ctrlbit = (1 << 7),
726  }, {
727  .name = "nfcon",
728  .enable = exynos5_clk_ip_fsys_ctrl,
729  .ctrlbit = (1 << 22),
730  }, {
731  .name = "iop",
732  .enable = exynos5_clk_ip_fsys_ctrl,
733  .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
734  }, {
735  .name = "core_iop",
736  .enable = exynos5_clk_ip_core_ctrl,
737  .ctrlbit = ((1 << 21) | (1 << 3)),
738  }, {
739  .name = "mcu_iop",
740  .enable = exynos5_clk_ip_fsys_ctrl,
741  .ctrlbit = (1 << 0),
742  }, {
743  .name = "i2c",
744  .devname = "s3c2440-i2c.0",
745  .parent = &exynos5_clk_aclk_66.clk,
746  .enable = exynos5_clk_ip_peric_ctrl,
747  .ctrlbit = (1 << 6),
748  }, {
749  .name = "i2c",
750  .devname = "s3c2440-i2c.1",
751  .parent = &exynos5_clk_aclk_66.clk,
752  .enable = exynos5_clk_ip_peric_ctrl,
753  .ctrlbit = (1 << 7),
754  }, {
755  .name = "i2c",
756  .devname = "s3c2440-i2c.2",
757  .parent = &exynos5_clk_aclk_66.clk,
758  .enable = exynos5_clk_ip_peric_ctrl,
759  .ctrlbit = (1 << 8),
760  }, {
761  .name = "i2c",
762  .devname = "s3c2440-i2c.3",
763  .parent = &exynos5_clk_aclk_66.clk,
764  .enable = exynos5_clk_ip_peric_ctrl,
765  .ctrlbit = (1 << 9),
766  }, {
767  .name = "i2c",
768  .devname = "s3c2440-i2c.4",
769  .parent = &exynos5_clk_aclk_66.clk,
770  .enable = exynos5_clk_ip_peric_ctrl,
771  .ctrlbit = (1 << 10),
772  }, {
773  .name = "i2c",
774  .devname = "s3c2440-i2c.5",
775  .parent = &exynos5_clk_aclk_66.clk,
776  .enable = exynos5_clk_ip_peric_ctrl,
777  .ctrlbit = (1 << 11),
778  }, {
779  .name = "i2c",
780  .devname = "s3c2440-i2c.6",
781  .parent = &exynos5_clk_aclk_66.clk,
782  .enable = exynos5_clk_ip_peric_ctrl,
783  .ctrlbit = (1 << 12),
784  }, {
785  .name = "i2c",
786  .devname = "s3c2440-i2c.7",
787  .parent = &exynos5_clk_aclk_66.clk,
788  .enable = exynos5_clk_ip_peric_ctrl,
789  .ctrlbit = (1 << 13),
790  }, {
791  .name = "i2c",
792  .devname = "s3c2440-hdmiphy-i2c",
793  .parent = &exynos5_clk_aclk_66.clk,
794  .enable = exynos5_clk_ip_peric_ctrl,
795  .ctrlbit = (1 << 14),
796  }, {
797  .name = "spi",
798  .devname = "exynos4210-spi.0",
799  .parent = &exynos5_clk_aclk_66.clk,
800  .enable = exynos5_clk_ip_peric_ctrl,
801  .ctrlbit = (1 << 16),
802  }, {
803  .name = "spi",
804  .devname = "exynos4210-spi.1",
805  .parent = &exynos5_clk_aclk_66.clk,
806  .enable = exynos5_clk_ip_peric_ctrl,
807  .ctrlbit = (1 << 17),
808  }, {
809  .name = "spi",
810  .devname = "exynos4210-spi.2",
811  .parent = &exynos5_clk_aclk_66.clk,
812  .enable = exynos5_clk_ip_peric_ctrl,
813  .ctrlbit = (1 << 18),
814  }, {
815  .name = "gscl",
816  .devname = "exynos-gsc.0",
817  .enable = exynos5_clk_ip_gscl_ctrl,
818  .ctrlbit = (1 << 0),
819  }, {
820  .name = "gscl",
821  .devname = "exynos-gsc.1",
822  .enable = exynos5_clk_ip_gscl_ctrl,
823  .ctrlbit = (1 << 1),
824  }, {
825  .name = "gscl",
826  .devname = "exynos-gsc.2",
827  .enable = exynos5_clk_ip_gscl_ctrl,
828  .ctrlbit = (1 << 2),
829  }, {
830  .name = "gscl",
831  .devname = "exynos-gsc.3",
832  .enable = exynos5_clk_ip_gscl_ctrl,
833  .ctrlbit = (1 << 3),
834  }, {
835  .name = SYSMMU_CLOCK_NAME,
836  .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
837  .enable = &exynos5_clk_ip_mfc_ctrl,
838  .ctrlbit = (1 << 1),
839  }, {
840  .name = SYSMMU_CLOCK_NAME,
841  .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
842  .enable = &exynos5_clk_ip_mfc_ctrl,
843  .ctrlbit = (1 << 2),
844  }, {
845  .name = SYSMMU_CLOCK_NAME,
846  .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
847  .enable = &exynos5_clk_ip_disp1_ctrl,
848  .ctrlbit = (1 << 9)
849  }, {
850  .name = SYSMMU_CLOCK_NAME,
851  .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
852  .enable = &exynos5_clk_ip_gen_ctrl,
853  .ctrlbit = (1 << 7),
854  }, {
855  .name = SYSMMU_CLOCK_NAME,
856  .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
857  .enable = &exynos5_clk_ip_gen_ctrl,
858  .ctrlbit = (1 << 6)
859  }, {
860  .name = SYSMMU_CLOCK_NAME,
861  .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
862  .enable = &exynos5_clk_ip_gscl_ctrl,
863  .ctrlbit = (1 << 7),
864  }, {
865  .name = SYSMMU_CLOCK_NAME,
866  .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
867  .enable = &exynos5_clk_ip_gscl_ctrl,
868  .ctrlbit = (1 << 8),
869  }, {
870  .name = SYSMMU_CLOCK_NAME,
871  .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
872  .enable = &exynos5_clk_ip_gscl_ctrl,
873  .ctrlbit = (1 << 9),
874  }, {
875  .name = SYSMMU_CLOCK_NAME,
876  .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
877  .enable = &exynos5_clk_ip_gscl_ctrl,
878  .ctrlbit = (1 << 10),
879  }, {
880  .name = SYSMMU_CLOCK_NAME,
881  .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
882  .enable = &exynos5_clk_ip_isp0_ctrl,
883  .ctrlbit = (0x3F << 8),
884  }, {
885  .name = SYSMMU_CLOCK_NAME2,
886  .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
887  .enable = &exynos5_clk_ip_isp1_ctrl,
888  .ctrlbit = (0xF << 4),
889  }, {
890  .name = SYSMMU_CLOCK_NAME,
891  .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
892  .enable = &exynos5_clk_ip_gscl_ctrl,
893  .ctrlbit = (1 << 11),
894  }, {
895  .name = SYSMMU_CLOCK_NAME,
896  .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
897  .enable = &exynos5_clk_ip_gscl_ctrl,
898  .ctrlbit = (1 << 12),
899  }, {
900  .name = SYSMMU_CLOCK_NAME,
901  .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
902  .enable = &exynos5_clk_ip_acp_ctrl,
903  .ctrlbit = (1 << 7)
904  }
905 };
906 
907 static struct clk exynos5_init_clocks_on[] = {
908  {
909  .name = "uart",
910  .devname = "s5pv210-uart.0",
911  .enable = exynos5_clk_ip_peric_ctrl,
912  .ctrlbit = (1 << 0),
913  }, {
914  .name = "uart",
915  .devname = "s5pv210-uart.1",
916  .enable = exynos5_clk_ip_peric_ctrl,
917  .ctrlbit = (1 << 1),
918  }, {
919  .name = "uart",
920  .devname = "s5pv210-uart.2",
921  .enable = exynos5_clk_ip_peric_ctrl,
922  .ctrlbit = (1 << 2),
923  }, {
924  .name = "uart",
925  .devname = "s5pv210-uart.3",
926  .enable = exynos5_clk_ip_peric_ctrl,
927  .ctrlbit = (1 << 3),
928  }, {
929  .name = "uart",
930  .devname = "s5pv210-uart.4",
931  .enable = exynos5_clk_ip_peric_ctrl,
932  .ctrlbit = (1 << 4),
933  }, {
934  .name = "uart",
935  .devname = "s5pv210-uart.5",
936  .enable = exynos5_clk_ip_peric_ctrl,
937  .ctrlbit = (1 << 5),
938  }
939 };
940 
941 static struct clk exynos5_clk_pdma0 = {
942  .name = "dma",
943  .devname = "dma-pl330.0",
944  .enable = exynos5_clk_ip_fsys_ctrl,
945  .ctrlbit = (1 << 1),
946 };
947 
948 static struct clk exynos5_clk_pdma1 = {
949  .name = "dma",
950  .devname = "dma-pl330.1",
951  .enable = exynos5_clk_ip_fsys_ctrl,
952  .ctrlbit = (1 << 2),
953 };
954 
955 static struct clk exynos5_clk_mdma1 = {
956  .name = "dma",
957  .devname = "dma-pl330.2",
958  .enable = exynos5_clk_ip_gen_ctrl,
959  .ctrlbit = (1 << 4),
960 };
961 
962 static struct clk exynos5_clk_fimd1 = {
963  .name = "fimd",
964  .devname = "exynos5-fb.1",
965  .enable = exynos5_clk_ip_disp1_ctrl,
966  .ctrlbit = (1 << 0),
967 };
968 
969 struct clk *exynos5_clkset_group_list[] = {
970  [0] = &clk_ext_xtal_mux,
971  [1] = NULL,
972  [2] = &exynos5_clk_sclk_hdmi24m,
973  [3] = &exynos5_clk_sclk_dptxphy,
974  [4] = &exynos5_clk_sclk_usbphy,
975  [5] = &exynos5_clk_sclk_hdmiphy,
976  [6] = &exynos5_clk_mout_mpll_user.clk,
977  [7] = &exynos5_clk_mout_epll.clk,
978  [8] = &exynos5_clk_sclk_vpll.clk,
979  [9] = &exynos5_clk_mout_cpll.clk,
980 };
981 
982 struct clksrc_sources exynos5_clkset_group = {
983  .sources = exynos5_clkset_group_list,
984  .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
985 };
986 
987 /* Possible clock sources for aclk_266_gscl_sub Mux */
988 static struct clk *clk_src_gscl_266_list[] = {
989  [0] = &clk_ext_xtal_mux,
990  [1] = &exynos5_clk_aclk_266.clk,
991 };
992 
993 static struct clksrc_sources clk_src_gscl_266 = {
994  .sources = clk_src_gscl_266_list,
995  .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
996 };
997 
998 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
999  .clk = {
1000  .name = "dout_mmc0",
1001  },
1002  .sources = &exynos5_clkset_group,
1003  .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1004  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1005 };
1006 
1007 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1008  .clk = {
1009  .name = "dout_mmc1",
1010  },
1011  .sources = &exynos5_clkset_group,
1012  .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1013  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1014 };
1015 
1016 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1017  .clk = {
1018  .name = "dout_mmc2",
1019  },
1020  .sources = &exynos5_clkset_group,
1021  .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1022  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1023 };
1024 
1025 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1026  .clk = {
1027  .name = "dout_mmc3",
1028  },
1029  .sources = &exynos5_clkset_group,
1030  .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1031  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1032 };
1033 
1034 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1035  .clk = {
1036  .name = "dout_mmc4",
1037  },
1038  .sources = &exynos5_clkset_group,
1039  .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1040  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1041 };
1042 
1043 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1044  .clk = {
1045  .name = "uclk1",
1046  .devname = "exynos4210-uart.0",
1047  .enable = exynos5_clksrc_mask_peric0_ctrl,
1048  .ctrlbit = (1 << 0),
1049  },
1050  .sources = &exynos5_clkset_group,
1051  .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1052  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1053 };
1054 
1055 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1056  .clk = {
1057  .name = "uclk1",
1058  .devname = "exynos4210-uart.1",
1059  .enable = exynos5_clksrc_mask_peric0_ctrl,
1060  .ctrlbit = (1 << 4),
1061  },
1062  .sources = &exynos5_clkset_group,
1063  .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1064  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1065 };
1066 
1067 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1068  .clk = {
1069  .name = "uclk1",
1070  .devname = "exynos4210-uart.2",
1071  .enable = exynos5_clksrc_mask_peric0_ctrl,
1072  .ctrlbit = (1 << 8),
1073  },
1074  .sources = &exynos5_clkset_group,
1075  .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1076  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1077 };
1078 
1079 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1080  .clk = {
1081  .name = "uclk1",
1082  .devname = "exynos4210-uart.3",
1083  .enable = exynos5_clksrc_mask_peric0_ctrl,
1084  .ctrlbit = (1 << 12),
1085  },
1086  .sources = &exynos5_clkset_group,
1087  .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1088  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1089 };
1090 
1091 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1092  .clk = {
1093  .name = "ciu", /* card interface unit clock */
1094  .devname = "dw_mmc.0",
1095  .parent = &exynos5_clk_dout_mmc0.clk,
1096  .enable = exynos5_clksrc_mask_fsys_ctrl,
1097  .ctrlbit = (1 << 0),
1098  },
1099  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1100 };
1101 
1102 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1103  .clk = {
1104  .name = "ciu",
1105  .devname = "dw_mmc.1",
1106  .parent = &exynos5_clk_dout_mmc1.clk,
1107  .enable = exynos5_clksrc_mask_fsys_ctrl,
1108  .ctrlbit = (1 << 4),
1109  },
1110  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1111 };
1112 
1113 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1114  .clk = {
1115  .name = "ciu",
1116  .devname = "dw_mmc.2",
1117  .parent = &exynos5_clk_dout_mmc2.clk,
1118  .enable = exynos5_clksrc_mask_fsys_ctrl,
1119  .ctrlbit = (1 << 8),
1120  },
1121  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1122 };
1123 
1124 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1125  .clk = {
1126  .name = "ciu",
1127  .devname = "dw_mmc.3",
1128  .parent = &exynos5_clk_dout_mmc3.clk,
1129  .enable = exynos5_clksrc_mask_fsys_ctrl,
1130  .ctrlbit = (1 << 12),
1131  },
1132  .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1133 };
1134 
1135 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1136  .clk = {
1137  .name = "mdout_spi",
1138  .devname = "exynos4210-spi.0",
1139  },
1140  .sources = &exynos5_clkset_group,
1141  .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1142  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1143 };
1144 
1145 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1146  .clk = {
1147  .name = "mdout_spi",
1148  .devname = "exynos4210-spi.1",
1149  },
1150  .sources = &exynos5_clkset_group,
1151  .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1152  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1153 };
1154 
1155 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1156  .clk = {
1157  .name = "mdout_spi",
1158  .devname = "exynos4210-spi.2",
1159  },
1160  .sources = &exynos5_clkset_group,
1161  .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1162  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1163 };
1164 
1165 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1166  .clk = {
1167  .name = "sclk_spi",
1168  .devname = "exynos4210-spi.0",
1169  .parent = &exynos5_clk_mdout_spi0.clk,
1170  .enable = exynos5_clksrc_mask_peric1_ctrl,
1171  .ctrlbit = (1 << 16),
1172  },
1173  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1174 };
1175 
1176 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1177  .clk = {
1178  .name = "sclk_spi",
1179  .devname = "exynos4210-spi.1",
1180  .parent = &exynos5_clk_mdout_spi1.clk,
1181  .enable = exynos5_clksrc_mask_peric1_ctrl,
1182  .ctrlbit = (1 << 20),
1183  },
1184  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1185 };
1186 
1187 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1188  .clk = {
1189  .name = "sclk_spi",
1190  .devname = "exynos4210-spi.2",
1191  .parent = &exynos5_clk_mdout_spi2.clk,
1192  .enable = exynos5_clksrc_mask_peric1_ctrl,
1193  .ctrlbit = (1 << 24),
1194  },
1195  .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1196 };
1197 
1198 struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1199  .clk = {
1200  .name = "sclk_fimd",
1201  .devname = "exynos5-fb.1",
1202  .enable = exynos5_clksrc_mask_disp1_0_ctrl,
1203  .ctrlbit = (1 << 0),
1204  },
1205  .sources = &exynos5_clkset_group,
1206  .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1207  .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1208 };
1209 
1210 static struct clksrc_clk exynos5_clksrcs[] = {
1211  {
1212  .clk = {
1213  .name = "aclk_266_gscl",
1214  },
1215  .sources = &clk_src_gscl_266,
1216  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1217  }, {
1218  .clk = {
1219  .name = "sclk_g3d",
1220  .devname = "mali-t604.0",
1221  .enable = exynos5_clk_block_ctrl,
1222  .ctrlbit = (1 << 1),
1223  },
1224  .sources = &exynos5_clkset_aclk,
1225  .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1226  .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1227  }, {
1228  .clk = {
1229  .name = "sclk_gscl_wrap",
1230  .devname = "s5p-mipi-csis.0",
1231  .enable = exynos5_clksrc_mask_gscl_ctrl,
1232  .ctrlbit = (1 << 24),
1233  },
1234  .sources = &exynos5_clkset_group,
1235  .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1236  .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1237  }, {
1238  .clk = {
1239  .name = "sclk_gscl_wrap",
1240  .devname = "s5p-mipi-csis.1",
1241  .enable = exynos5_clksrc_mask_gscl_ctrl,
1242  .ctrlbit = (1 << 28),
1243  },
1244  .sources = &exynos5_clkset_group,
1245  .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1246  .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1247  }, {
1248  .clk = {
1249  .name = "sclk_cam0",
1250  .enable = exynos5_clksrc_mask_gscl_ctrl,
1251  .ctrlbit = (1 << 16),
1252  },
1253  .sources = &exynos5_clkset_group,
1254  .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1255  .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1256  }, {
1257  .clk = {
1258  .name = "sclk_cam1",
1259  .enable = exynos5_clksrc_mask_gscl_ctrl,
1260  .ctrlbit = (1 << 20),
1261  },
1262  .sources = &exynos5_clkset_group,
1263  .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1264  .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1265  }, {
1266  .clk = {
1267  .name = "sclk_jpeg",
1268  .parent = &exynos5_clk_mout_cpll.clk,
1269  },
1270  .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1271  },
1272 };
1273 
1274 /* Clock initialization code */
1275 static struct clksrc_clk *exynos5_sysclks[] = {
1276  &exynos5_clk_mout_apll,
1277  &exynos5_clk_sclk_apll,
1278  &exynos5_clk_mout_bpll,
1279  &exynos5_clk_mout_bpll_fout,
1280  &exynos5_clk_mout_bpll_user,
1281  &exynos5_clk_mout_cpll,
1282  &exynos5_clk_mout_epll,
1283  &exynos5_clk_mout_mpll,
1284  &exynos5_clk_mout_mpll_fout,
1285  &exynos5_clk_mout_mpll_user,
1286  &exynos5_clk_vpllsrc,
1287  &exynos5_clk_sclk_vpll,
1288  &exynos5_clk_mout_cpu,
1289  &exynos5_clk_dout_armclk,
1290  &exynos5_clk_dout_arm2clk,
1291  &exynos5_clk_cdrex,
1292  &exynos5_clk_aclk_400,
1293  &exynos5_clk_aclk_333,
1294  &exynos5_clk_aclk_266,
1295  &exynos5_clk_aclk_200,
1296  &exynos5_clk_aclk_166,
1297  &exynos5_clk_aclk_300_gscl,
1298  &exynos5_clk_mout_aclk_300_gscl,
1299  &exynos5_clk_mout_aclk_300_gscl_mid,
1300  &exynos5_clk_mout_aclk_300_gscl_mid1,
1301  &exynos5_clk_aclk_66_pre,
1302  &exynos5_clk_aclk_66,
1303  &exynos5_clk_dout_mmc0,
1304  &exynos5_clk_dout_mmc1,
1305  &exynos5_clk_dout_mmc2,
1306  &exynos5_clk_dout_mmc3,
1307  &exynos5_clk_dout_mmc4,
1308  &exynos5_clk_aclk_acp,
1309  &exynos5_clk_pclk_acp,
1310  &exynos5_clk_sclk_spi0,
1311  &exynos5_clk_sclk_spi1,
1312  &exynos5_clk_sclk_spi2,
1313  &exynos5_clk_mdout_spi0,
1314  &exynos5_clk_mdout_spi1,
1315  &exynos5_clk_mdout_spi2,
1316  &exynos5_clk_sclk_fimd1,
1317 };
1318 
1319 static struct clk *exynos5_clk_cdev[] = {
1320  &exynos5_clk_pdma0,
1321  &exynos5_clk_pdma1,
1322  &exynos5_clk_mdma1,
1323  &exynos5_clk_fimd1,
1324 };
1325 
1326 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1327  &exynos5_clk_sclk_uart0,
1328  &exynos5_clk_sclk_uart1,
1329  &exynos5_clk_sclk_uart2,
1330  &exynos5_clk_sclk_uart3,
1331  &exynos5_clk_sclk_mmc0,
1332  &exynos5_clk_sclk_mmc1,
1333  &exynos5_clk_sclk_mmc2,
1334  &exynos5_clk_sclk_mmc3,
1335 };
1336 
1337 static struct clk_lookup exynos5_clk_lookup[] = {
1338  CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1339  CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1340  CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1341  CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1342  CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1343  CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1344  CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1345  CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1346  CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1347  CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1348  CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1349  CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1350  CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1351  CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1352  CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1353 };
1354 
1355 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1356 {
1357  return clk->rate;
1358 }
1359 
1360 static struct clk *exynos5_clks[] __initdata = {
1361  &exynos5_clk_sclk_hdmi27m,
1362  &exynos5_clk_sclk_hdmiphy,
1363  &clk_fout_bpll,
1364  &clk_fout_bpll_div2,
1365  &clk_fout_cpll,
1366  &clk_fout_mpll_div2,
1367  &exynos5_clk_armclk,
1368 };
1369 
1370 static u32 epll_div[][6] = {
1371  { 192000000, 0, 48, 3, 1, 0 },
1372  { 180000000, 0, 45, 3, 1, 0 },
1373  { 73728000, 1, 73, 3, 3, 47710 },
1374  { 67737600, 1, 90, 4, 3, 20762 },
1375  { 49152000, 0, 49, 3, 3, 9961 },
1376  { 45158400, 0, 45, 3, 3, 10381 },
1377  { 180633600, 0, 45, 3, 1, 10381 },
1378 };
1379 
1380 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1381 {
1382  unsigned int epll_con, epll_con_k;
1383  unsigned int i;
1384  unsigned int tmp;
1385  unsigned int epll_rate;
1386  unsigned int locktime;
1387  unsigned int lockcnt;
1388 
1389  /* Return if nothing changed */
1390  if (clk->rate == rate)
1391  return 0;
1392 
1393  if (clk->parent)
1394  epll_rate = clk_get_rate(clk->parent);
1395  else
1396  epll_rate = clk_ext_xtal_mux.rate;
1397 
1398  if (epll_rate != 24000000) {
1399  pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1400  return -EINVAL;
1401  }
1402 
1403  epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1404  epll_con &= ~(0x1 << 27 | \
1405  PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1406  PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1407  PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1408 
1409  for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1410  if (epll_div[i][0] == rate) {
1411  epll_con_k = epll_div[i][5] << 0;
1412  epll_con |= epll_div[i][1] << 27;
1413  epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1414  epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1415  epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1416  break;
1417  }
1418  }
1419 
1420  if (i == ARRAY_SIZE(epll_div)) {
1421  printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1422  __func__);
1423  return -EINVAL;
1424  }
1425 
1426  epll_rate /= 1000000;
1427 
1428  /* 3000 max_cycls : specification data */
1429  locktime = 3000 / epll_rate * epll_div[i][3];
1430  lockcnt = locktime * 10000 / (10000 / epll_rate);
1431 
1432  __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1433 
1434  __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1435  __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1436 
1437  do {
1438  tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1439  } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1440 
1441  clk->rate = rate;
1442 
1443  return 0;
1444 }
1445 
1446 static struct clk_ops exynos5_epll_ops = {
1447  .get_rate = exynos5_epll_get_rate,
1448  .set_rate = exynos5_epll_set_rate,
1449 };
1450 
1451 static int xtal_rate;
1452 
1453 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1454 {
1455  return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1456 }
1457 
1458 static struct clk_ops exynos5_fout_apll_ops = {
1459  .get_rate = exynos5_fout_apll_get_rate,
1460 };
1461 
1462 #ifdef CONFIG_PM
1463 static int exynos5_clock_suspend(void)
1464 {
1465  s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1466 
1467  return 0;
1468 }
1469 
1470 static void exynos5_clock_resume(void)
1471 {
1472  s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1473 }
1474 #else
1475 #define exynos5_clock_suspend NULL
1476 #define exynos5_clock_resume NULL
1477 #endif
1478 
1479 struct syscore_ops exynos5_clock_syscore_ops = {
1480  .suspend = exynos5_clock_suspend,
1481  .resume = exynos5_clock_resume,
1482 };
1483 
1484 void __init_or_cpufreq exynos5_setup_clocks(void)
1485 {
1486  struct clk *xtal_clk;
1487  unsigned long apll;
1488  unsigned long bpll;
1489  unsigned long cpll;
1490  unsigned long mpll;
1491  unsigned long epll;
1492  unsigned long vpll;
1493  unsigned long vpllsrc;
1494  unsigned long xtal;
1495  unsigned long armclk;
1496  unsigned long mout_cdrex;
1497  unsigned long aclk_400;
1498  unsigned long aclk_333;
1499  unsigned long aclk_266;
1500  unsigned long aclk_200;
1501  unsigned long aclk_166;
1502  unsigned long aclk_66;
1503  unsigned int ptr;
1504 
1505  printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1506 
1507  xtal_clk = clk_get(NULL, "xtal");
1508  BUG_ON(IS_ERR(xtal_clk));
1509 
1510  xtal = clk_get_rate(xtal_clk);
1511 
1512  xtal_rate = xtal;
1513 
1514  clk_put(xtal_clk);
1515 
1516  printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1517 
1518  apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1519  bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1520  cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1521  mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1522  epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1523  __raw_readl(EXYNOS5_EPLL_CON1));
1524 
1525  vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1526  vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1527  __raw_readl(EXYNOS5_VPLL_CON1));
1528 
1529  clk_fout_apll.ops = &exynos5_fout_apll_ops;
1530  clk_fout_bpll.rate = bpll;
1531  clk_fout_bpll_div2.rate = bpll >> 1;
1532  clk_fout_cpll.rate = cpll;
1533  clk_fout_mpll.rate = mpll;
1534  clk_fout_mpll_div2.rate = mpll >> 1;
1535  clk_fout_epll.rate = epll;
1536  clk_fout_vpll.rate = vpll;
1537 
1538  printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1539  "M=%ld, E=%ld V=%ld",
1540  apll, bpll, cpll, mpll, epll, vpll);
1541 
1542  armclk = clk_get_rate(&exynos5_clk_armclk);
1543  mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1544 
1545  aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1546  aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1547  aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1548  aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1549  aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1550  aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1551 
1552  printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1553  "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1554  "ACLK166=%ld, ACLK66=%ld\n",
1555  armclk, mout_cdrex, aclk_400,
1556  aclk_333, aclk_266, aclk_200,
1557  aclk_166, aclk_66);
1558 
1559 
1560  clk_fout_epll.ops = &exynos5_epll_ops;
1561 
1562  if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1563  printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1564  clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1565 
1566  clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1567  clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1568 
1569  clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1570  clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1571 
1572  for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1573  s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1574 }
1575 
1576 void __init exynos5_register_clocks(void)
1577 {
1578  int ptr;
1579 
1580  s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1581 
1582  for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1583  s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1584 
1585  for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1586  s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1587 
1588  for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1589  s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1590 
1591  s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1592  s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1593 
1594  s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1595  for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1596  s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1597 
1598  s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1599  s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1600  clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1601 
1602  register_syscore_ops(&exynos5_clock_syscore_ops);
1603  s3c_pwmclk_init();
1604 }
Generated on Thu Jan 10 2013 12:58:55 for Linux Kernel by   doxygen 1.8.2