Macros
#define	CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */

#define	CNS3XXX_FLASH_SIZE SZ_256M

#define	CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */

#define	CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */

#define	CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */

#define	CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000

#define	CNS3XXX_PPE_BASE 0x70001000 /* HANT */

#define	CNS3XXX_PPE_BASE_VIRT 0xFFF50000

#define	CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */

#define	CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000

#define	CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */

#define	CNS3XXX_SSP_BASE_VIRT 0xFFF01000

#define	CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */

#define	CNS3XXX_DMC_BASE_VIRT 0xFFF02000

#define	CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */

#define	CNS3XXX_SMC_BASE_VIRT 0xFFF03000

#define	SMC_MEMC_STATUS_OFFSET 0x000

#define	SMC_MEMIF_CFG_OFFSET 0x004

#define	SMC_MEMC_CFG_SET_OFFSET 0x008

#define	SMC_MEMC_CFG_CLR_OFFSET 0x00C

#define	SMC_DIRECT_CMD_OFFSET 0x010

#define	SMC_SET_CYCLES_OFFSET 0x014

#define	SMC_SET_OPMODE_OFFSET 0x018

#define	SMC_REFRESH_PERIOD_0_OFFSET 0x020

#define	SMC_REFRESH_PERIOD_1_OFFSET 0x024

#define	SMC_SRAM_CYCLES0_0_OFFSET 0x100

#define	SMC_NAND_CYCLES0_0_OFFSET 0x100

#define	SMC_OPMODE0_0_OFFSET 0x104

#define	SMC_SRAM_CYCLES0_1_OFFSET 0x120

#define	SMC_NAND_CYCLES0_1_OFFSET 0x120

#define	SMC_OPMODE0_1_OFFSET 0x124

#define	SMC_USER_STATUS_OFFSET 0x200

#define	SMC_USER_CONFIG_OFFSET 0x204

#define	SMC_ECC_STATUS_OFFSET 0x300

#define	SMC_ECC_MEMCFG_OFFSET 0x304

#define	SMC_ECC_MEMCOMMAND1_OFFSET 0x308

#define	SMC_ECC_MEMCOMMAND2_OFFSET 0x30C

#define	SMC_ECC_ADDR0_OFFSET 0x310

#define	SMC_ECC_ADDR1_OFFSET 0x314

#define	SMC_ECC_VALUE0_OFFSET 0x318

#define	SMC_ECC_VALUE1_OFFSET 0x31C

#define	SMC_ECC_VALUE2_OFFSET 0x320

#define	SMC_ECC_VALUE3_OFFSET 0x324

#define	SMC_PERIPH_ID_0_OFFSET 0xFE0

#define	SMC_PERIPH_ID_1_OFFSET 0xFE4

#define	SMC_PERIPH_ID_2_OFFSET 0xFE8

#define	SMC_PERIPH_ID_3_OFFSET 0xFEC

#define	SMC_PCELL_ID_0_OFFSET 0xFF0

#define	SMC_PCELL_ID_1_OFFSET 0xFF4

#define	SMC_PCELL_ID_2_OFFSET 0xFF8

#define	SMC_PCELL_ID_3_OFFSET 0xFFC

#define	CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */

#define	CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000

#define	CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */

#define	CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000

#define	CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */

#define	CNS3XXX_RTC_BASE_VIRT 0xFFF06000

#define	RTC_SEC_OFFSET 0x00

#define	RTC_MIN_OFFSET 0x04

#define	RTC_HOUR_OFFSET 0x08

#define	RTC_DAY_OFFSET 0x0C

#define	RTC_SEC_ALM_OFFSET 0x10

#define	RTC_MIN_ALM_OFFSET 0x14

#define	RTC_HOUR_ALM_OFFSET 0x18

#define	RTC_REC_OFFSET 0x1C

#define	RTC_CTRL_OFFSET 0x20

#define	RTC_INTR_STS_OFFSET 0x34

#define	CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */

#define	CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */

#define	CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */

#define	CNS3XXX_PM_BASE_VIRT 0xFFF08000

#define	PM_CLK_GATE_OFFSET 0x00

#define	PM_SOFT_RST_OFFSET 0x04

#define	PM_HS_CFG_OFFSET 0x08

#define	PM_CACTIVE_STA_OFFSET 0x0C

#define	PM_PWR_STA_OFFSET 0x10

#define	PM_SYS_CLK_CTRL_OFFSET 0x14

#define	PM_PLL_LCD_I2S_CTRL_OFFSET 0x18

#define	PM_PLL_HM_PD_OFFSET 0x1C

#define	CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */

#define	CNS3XXX_UART0_BASE_VIRT 0xFFF09000

#define	CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */

#define	CNS3XXX_UART1_BASE_VIRT 0xFFF0A000

#define	CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */

#define	CNS3XXX_UART2_BASE_VIRT 0xFFF0B000

#define	CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */

#define	CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000

#define	CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */

#define	CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000

#define	CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */

#define	CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000

#define	CNS3XXX_I2S_BASE 0x7C000000 /* I2S */

#define	CNS3XXX_I2S_BASE_VIRT 0xFFF10000

#define	CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */

#define	CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800

#define	TIMER1_COUNTER_OFFSET 0x00

#define	TIMER1_AUTO_RELOAD_OFFSET 0x04

#define	TIMER1_MATCH_V1_OFFSET 0x08

#define	TIMER1_MATCH_V2_OFFSET 0x0C

#define	TIMER2_COUNTER_OFFSET 0x10

#define	TIMER2_AUTO_RELOAD_OFFSET 0x14

#define	TIMER2_MATCH_V1_OFFSET 0x18

#define	TIMER2_MATCH_V2_OFFSET 0x1C

#define	TIMER1_2_CONTROL_OFFSET 0x30

#define	TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34

#define	TIMER1_2_INTERRUPT_MASK_OFFSET 0x38

#define	TIMER_FREERUN_OFFSET 0x40

#define	TIMER_FREERUN_CONTROL_OFFSET 0x44

#define	CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */

#define	CNS3XXX_HCIE_BASE_VIRT 0xFFF30000

#define	CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */

#define	CNS3XXX_RAID_BASE_VIRT 0xFFF12000

#define	CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */

#define	CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000

#define	CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */

#define	CNS3XXX_CLCD_BASE_VIRT 0xFFF14000

#define	CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */

#define	CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000

#define	CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */

#define	CNS3XXX_SATA2_BASE 0x83000000 /* SATA */

#define	CNS3XXX_SATA2_SIZE SZ_16M

#define	CNS3XXX_SATA2_BASE_VIRT 0xFFF17000

#define	CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */

#define	CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000

#define	CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */

#define	CNS3XXX_SDIO_BASE_VIRT 0xFFF19000

#define	CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */

#define	CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000

#define	CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */

#define	CNS3XXX_2DG_BASE_VIRT 0xFFF1B000

#define	CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */

#define	CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */

#define	CNS3XXX_L2C_BASE_VIRT 0xFFF27000

#define	CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */

#define	CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000

#define	CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */

#define	CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000

#define	CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */

#define	CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000

#define	CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */

#define	CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000

#define	CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */

#define	CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000

#define	CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */

#define	CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000

#define	CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */

#define	CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000

#define	CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */

#define	CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000

#define	CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */

#define	CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000

#define	CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */

#define	CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000

#define	CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */

#define	CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000

#define	CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */

#define	CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000

#define	CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */

#define	CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000

#define	CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */

#define	CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100

#define	CNS3XXX_TC11MP_TWD_BASE 0x90000600

#define	CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600

#define	CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */

#define	CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000

#define	CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */

#define	CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000

#define	MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))

#define	MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)

#define	MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)

#define	MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)

#define	MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)

#define	MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)

#define	MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)

#define	MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)

#define	MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)

#define	MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)

#define	MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)

#define	MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)

#define	MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)

#define	MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)

#define	MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)

#define	MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)

#define	MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)

#define	MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)

#define	MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)

#define	MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)

#define	MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)

#define	MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)

#define	MISC_USB_CFG_REG MISC_MEM_MAP(0x800)

#define	MISC_USB_STS_REG MISC_MEM_MAP(0x804)

#define	MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)

#define	MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)

#define	MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)

#define	MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)

#define	MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)

#define	MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)

#define	MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)

#define	MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)

#define	MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)

#define	MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)

#define	MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)

#define	MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)

#define	MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)

#define	MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)

#define	MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)

#define	MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)

#define	MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)

#define	MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)

#define	MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)

#define	MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)

#define	MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)

#define	PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))

#define	PM_CLK_GATE_REG PMU_MEM_MAP(0x000)

#define	PM_SOFT_RST_REG PMU_MEM_MAP(0x004)

#define	PM_HS_CFG_REG PMU_MEM_MAP(0x008)

#define	PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)

#define	PM_PWR_STA_REG PMU_MEM_MAP(0x010)

#define	PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)

#define	PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)

#define	PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)

#define	PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)

#define	PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)

#define	PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)

#define	PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)

#define	PM_CSR_REG PMU_MEM_MAP(0x030)

#define	PM_CLK_GATE_REG_OFFSET_SDIO (25)

#define	PM_CLK_GATE_REG_OFFSET_GPU (24)

#define	PM_CLK_GATE_REG_OFFSET_CIM (23)

#define	PM_CLK_GATE_REG_OFFSET_LCDC (22)

#define	PM_CLK_GATE_REG_OFFSET_I2S (21)

#define	PM_CLK_GATE_REG_OFFSET_RAID (20)

#define	PM_CLK_GATE_REG_OFFSET_SATA (19)

#define	PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))

#define	PM_CLK_GATE_REG_OFFSET_USB_HOST (16)

#define	PM_CLK_GATE_REG_OFFSET_USB_OTG (15)

#define	PM_CLK_GATE_REG_OFFSET_TIMER (14)

#define	PM_CLK_GATE_REG_OFFSET_CRYPTO (13)

#define	PM_CLK_GATE_REG_OFFSET_HCIE (12)

#define	PM_CLK_GATE_REG_OFFSET_SWITCH (11)

#define	PM_CLK_GATE_REG_OFFSET_GPIO (10)

#define	PM_CLK_GATE_REG_OFFSET_UART3 (9)

#define	PM_CLK_GATE_REG_OFFSET_UART2 (8)

#define	PM_CLK_GATE_REG_OFFSET_UART1 (7)

#define	PM_CLK_GATE_REG_OFFSET_RTC (5)

#define	PM_CLK_GATE_REG_OFFSET_GDMA (4)

#define	PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)

#define	PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)

#define	PM_CLK_GATE_REG_MASK (0x03FFFFBA)

#define	PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)

#define	PM_SOFT_RST_REG_OFFST_CPU1 (29)

#define	PM_SOFT_RST_REG_OFFST_CPU0 (28)

#define	PM_SOFT_RST_REG_OFFST_SDIO (25)

#define	PM_SOFT_RST_REG_OFFST_GPU (24)

#define	PM_SOFT_RST_REG_OFFST_CIM (23)

#define	PM_SOFT_RST_REG_OFFST_LCDC (22)

#define	PM_SOFT_RST_REG_OFFST_I2S (21)

#define	PM_SOFT_RST_REG_OFFST_RAID (20)

#define	PM_SOFT_RST_REG_OFFST_SATA (19)

#define	PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))

#define	PM_SOFT_RST_REG_OFFST_USB_HOST (16)

#define	PM_SOFT_RST_REG_OFFST_USB_OTG (15)

#define	PM_SOFT_RST_REG_OFFST_TIMER (14)

#define	PM_SOFT_RST_REG_OFFST_CRYPTO (13)

#define	PM_SOFT_RST_REG_OFFST_HCIE (12)

#define	PM_SOFT_RST_REG_OFFST_SWITCH (11)

#define	PM_SOFT_RST_REG_OFFST_GPIO (10)

#define	PM_SOFT_RST_REG_OFFST_UART3 (9)

#define	PM_SOFT_RST_REG_OFFST_UART2 (8)

#define	PM_SOFT_RST_REG_OFFST_UART1 (7)

#define	PM_SOFT_RST_REG_OFFST_RTC (5)

#define	PM_SOFT_RST_REG_OFFST_GDMA (4)

#define	PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)

#define	PM_SOFT_RST_REG_OFFST_DMC (2)

#define	PM_SOFT_RST_REG_OFFST_SMC_NFI (1)

#define	PM_SOFT_RST_REG_OFFST_GLOBAL (0)

#define	PM_SOFT_RST_REG_MASK (0xF3FFFFBF)

#define	PM_HS_CFG_REG_OFFSET_SDIO (25)

#define	PM_HS_CFG_REG_OFFSET_GPU (24)

#define	PM_HS_CFG_REG_OFFSET_CIM (23)

#define	PM_HS_CFG_REG_OFFSET_LCDC (22)

#define	PM_HS_CFG_REG_OFFSET_I2S (21)

#define	PM_HS_CFG_REG_OFFSET_RAID (20)

#define	PM_HS_CFG_REG_OFFSET_SATA (19)

#define	PM_HS_CFG_REG_OFFSET_PCIE1 (18)

#define	PM_HS_CFG_REG_OFFSET_PCIE0 (17)

#define	PM_HS_CFG_REG_OFFSET_USB_HOST (16)

#define	PM_HS_CFG_REG_OFFSET_USB_OTG (15)

#define	PM_HS_CFG_REG_OFFSET_TIMER (14)

#define	PM_HS_CFG_REG_OFFSET_CRYPTO (13)

#define	PM_HS_CFG_REG_OFFSET_HCIE (12)

#define	PM_HS_CFG_REG_OFFSET_SWITCH (11)

#define	PM_HS_CFG_REG_OFFSET_GPIO (10)

#define	PM_HS_CFG_REG_OFFSET_UART3 (9)

#define	PM_HS_CFG_REG_OFFSET_UART2 (8)

#define	PM_HS_CFG_REG_OFFSET_UART1 (7)

#define	PM_HS_CFG_REG_OFFSET_RTC (5)

#define	PM_HS_CFG_REG_OFFSET_GDMA (4)

#define	PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)

#define	PM_HS_CFG_REG_OFFSET_DMC (2)

#define	PM_HS_CFG_REG_OFFSET_SMC_NFI (1)

#define	PM_HS_CFG_REG_MASK (0x03FFFFBE)

#define	PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)

#define	PM_CACTIVE_STA_REG_OFFSET_SDIO (25)

#define	PM_CACTIVE_STA_REG_OFFSET_GPU (24)

#define	PM_CACTIVE_STA_REG_OFFSET_CIM (23)

#define	PM_CACTIVE_STA_REG_OFFSET_LCDC (22)

#define	PM_CACTIVE_STA_REG_OFFSET_I2S (21)

#define	PM_CACTIVE_STA_REG_OFFSET_RAID (20)

#define	PM_CACTIVE_STA_REG_OFFSET_SATA (19)

#define	PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)

#define	PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)

#define	PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)

#define	PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)

#define	PM_CACTIVE_STA_REG_OFFSET_TIMER (14)

#define	PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)

#define	PM_CACTIVE_STA_REG_OFFSET_HCIE (12)

#define	PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)

#define	PM_CACTIVE_STA_REG_OFFSET_GPIO (10)

#define	PM_CACTIVE_STA_REG_OFFSET_UART3 (9)

#define	PM_CACTIVE_STA_REG_OFFSET_UART2 (8)

#define	PM_CACTIVE_STA_REG_OFFSET_UART1 (7)

#define	PM_CACTIVE_STA_REG_OFFSET_RTC (5)

#define	PM_CACTIVE_STA_REG_OFFSET_GDMA (4)

#define	PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)

#define	PM_CACTIVE_STA_REG_OFFSET_DMC (2)

#define	PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)

#define	PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)

#define	PM_PWR_STA_REG_REG_OFFSET_SDIO (25)

#define	PM_PWR_STA_REG_REG_OFFSET_GPU (24)

#define	PM_PWR_STA_REG_REG_OFFSET_CIM (23)

#define	PM_PWR_STA_REG_REG_OFFSET_LCDC (22)

#define	PM_PWR_STA_REG_REG_OFFSET_I2S (21)

#define	PM_PWR_STA_REG_REG_OFFSET_RAID (20)

#define	PM_PWR_STA_REG_REG_OFFSET_SATA (19)

#define	PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)

#define	PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)

#define	PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)

#define	PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)

#define	PM_PWR_STA_REG_REG_OFFSET_TIMER (14)

#define	PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)

#define	PM_PWR_STA_REG_REG_OFFSET_HCIE (12)

#define	PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)

#define	PM_PWR_STA_REG_REG_OFFSET_GPIO (10)

#define	PM_PWR_STA_REG_REG_OFFSET_UART3 (9)

#define	PM_PWR_STA_REG_REG_OFFSET_UART2 (8)

#define	PM_PWR_STA_REG_REG_OFFSET_UART1 (7)

#define	PM_PWR_STA_REG_REG_OFFSET_RTC (5)

#define	PM_PWR_STA_REG_REG_OFFSET_GDMA (4)

#define	PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)

#define	PM_PWR_STA_REG_REG_OFFSET_DMC (2)

#define	PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)

#define	PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)

#define	PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)

#define	PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)

#define	PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)

#define	PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)

#define	PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)

#define	PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)

#define	PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)

#define	PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)

#define	PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)

#define	PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)

#define	PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)

#define	PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)

#define	PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)

#define	PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)

#define	PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)

#define	PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)

#define	PM_CPU_CLK_DIV(DIV)

#define	PM_PLL_CPU_SEL(CPU)

#define	PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)

#define	PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)

#define	PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)

#define	PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)

#define	PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)

#define	PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)

#define	PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)

#define	PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)

#define	PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)

#define	PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)

#define	PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)

#define	PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)

#define	PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)

#define	PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)

#define	PM_CSR_REG_OFFSET_CSR_EN (30)

#define	PM_CSR_REG_OFFSET_CSR_NUM (0)

#define	CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)

#define	CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)

#define	CNS3XXX_PWR_CPU_MODE_DFS (0)

#define	CNS3XXX_PWR_CPU_MODE_IDLE (1)

#define	CNS3XXX_PWR_CPU_MODE_HALT (2)

#define	CNS3XXX_PWR_CPU_MODE_DOZE (3)

#define	CNS3XXX_PWR_CPU_MODE_SLEEP (4)

#define	CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)

#define	CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)

#define	CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK

#define	CNS3XXX_PWR_PLL_CPU_300MHZ (0)

#define	CNS3XXX_PWR_PLL_CPU_333MHZ (1)

#define	CNS3XXX_PWR_PLL_CPU_366MHZ (2)

#define	CNS3XXX_PWR_PLL_CPU_400MHZ (3)

#define	CNS3XXX_PWR_PLL_CPU_433MHZ (4)

#define	CNS3XXX_PWR_PLL_CPU_466MHZ (5)

#define	CNS3XXX_PWR_PLL_CPU_500MHZ (6)

#define	CNS3XXX_PWR_PLL_CPU_533MHZ (7)

#define	CNS3XXX_PWR_PLL_CPU_566MHZ (8)

#define	CNS3XXX_PWR_PLL_CPU_600MHZ (9)

#define	CNS3XXX_PWR_PLL_CPU_633MHZ (10)

#define	CNS3XXX_PWR_PLL_CPU_666MHZ (11)

#define	CNS3XXX_PWR_PLL_CPU_700MHZ (12)

#define	CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)

#define	CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)

#define	CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)

#define	CNS3XXX_PWR_PLL_DDR2_200MHZ (0)

#define	CNS3XXX_PWR_PLL_DDR2_266MHZ (1)

#define	CNS3XXX_PWR_PLL_DDR2_333MHZ (2)

#define	CNS3XXX_PWR_PLL_DDR2_400MHZ (3)

#define	IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)

#define	IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)

#define	IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)

#define	IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)

#define	IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)

#define	IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)

#define	IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)

#define	IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)

#define	IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)

#define	IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)

#define	IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)

#define	IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)

#define	IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)

#define	IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)

#define	IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)

#define	IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)

#define	IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)

#define	IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)

#define	IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)

#define	IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)

#define	IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)

#define	IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)

#define	IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)

#define	IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)

#define	IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)

#define	IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)

#define	IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)

#define	IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)

#define	IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)

#define	IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)

#define	IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)

#define	IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)

#define	IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)

#define	IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)

#define	IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)

#define	IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)

#define	IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)

#define	IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)

#define	IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)

#define	IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)

#define	IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)

#define	IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)

#define	IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)

#define	IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)

#define	IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)

#define	IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)

#define	IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)

#define	IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)

#define	IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)

#define	IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)

#define	IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)

#define	IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)

#define	IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)

#define	IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)

#define	IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)

#define	IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)

#define	IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)

#define	IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)

#define	IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)

#define	IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)

#define	IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)

#define	IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)

#define	IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)

#define	IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)

#define	NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)

#define	NR_IRQS NR_IRQS_CNS3XXX

Functions
void	cns3xxx_pwr_soft_rst (unsigned int block)

void	cns3xxx_pwr_clk_en (unsigned int block)

int	cns3xxx_cpu_clock (void)

Macro Definition Documentation

#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */

Definition at line 182 of file cns3xxx.h.

#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000

Definition at line 183 of file cns3xxx.h.

#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */

Definition at line 158 of file cns3xxx.h.

#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000

Definition at line 159 of file cns3xxx.h.

#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */

Definition at line 173 of file cns3xxx.h.

#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000

Definition at line 174 of file cns3xxx.h.

#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */

Definition at line 161 of file cns3xxx.h.

#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000

Definition at line 162 of file cns3xxx.h.

#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */

Definition at line 123 of file cns3xxx.h.

#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000

Definition at line 124 of file cns3xxx.h.

#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */

Definition at line 126 of file cns3xxx.h.

#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000

Definition at line 127 of file cns3xxx.h.

#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */

Definition at line 18 of file cns3xxx.h.

#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */

Definition at line 120 of file cns3xxx.h.

#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000

Definition at line 121 of file cns3xxx.h.

#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */

Definition at line 34 of file cns3xxx.h.

#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000

Definition at line 35 of file cns3xxx.h.

#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */

Definition at line 28 of file cns3xxx.h.

#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000

Definition at line 29 of file cns3xxx.h.

#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */

Definition at line 15 of file cns3xxx.h.

#define CNS3XXX_FLASH_SIZE SZ_256M

Definition at line 16 of file cns3xxx.h.

#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */

Definition at line 76 of file cns3xxx.h.

#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000

Definition at line 77 of file cns3xxx.h.

#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */

Definition at line 79 of file cns3xxx.h.

#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000

Definition at line 80 of file cns3xxx.h.

#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */

Definition at line 152 of file cns3xxx.h.

#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000

Definition at line 153 of file cns3xxx.h.

#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */

Definition at line 129 of file cns3xxx.h.

#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000

Definition at line 130 of file cns3xxx.h.

#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */

Definition at line 179 of file cns3xxx.h.

#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000

Definition at line 180 of file cns3xxx.h.

#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */

Definition at line 187 of file cns3xxx.h.

#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000

Definition at line 188 of file cns3xxx.h.

#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */

Definition at line 96 of file cns3xxx.h.

#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */

Definition at line 97 of file cns3xxx.h.

#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */

Definition at line 199 of file cns3xxx.h.

#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000

Definition at line 200 of file cns3xxx.h.

#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */

Definition at line 202 of file cns3xxx.h.

#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000

Definition at line 203 of file cns3xxx.h.

#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */

Definition at line 193 of file cns3xxx.h.

#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000

Definition at line 194 of file cns3xxx.h.

#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */

Definition at line 196 of file cns3xxx.h.

#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000

Definition at line 197 of file cns3xxx.h.

#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */

Definition at line 190 of file cns3xxx.h.

#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000

Definition at line 191 of file cns3xxx.h.

#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */

Definition at line 205 of file cns3xxx.h.

#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000

Definition at line 206 of file cns3xxx.h.

#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */

Definition at line 217 of file cns3xxx.h.

#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000

Definition at line 218 of file cns3xxx.h.

#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */

Definition at line 220 of file cns3xxx.h.

#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000

Definition at line 221 of file cns3xxx.h.

#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */

Definition at line 211 of file cns3xxx.h.

#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000

Definition at line 212 of file cns3xxx.h.

#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */

Definition at line 214 of file cns3xxx.h.

#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000

Definition at line 215 of file cns3xxx.h.

#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */

Definition at line 208 of file cns3xxx.h.

#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000

Definition at line 209 of file cns3xxx.h.

#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */

Definition at line 223 of file cns3xxx.h.

#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000

Definition at line 224 of file cns3xxx.h.

#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */

Definition at line 99 of file cns3xxx.h.

#define CNS3XXX_PM_BASE_VIRT 0xFFF08000

Definition at line 100 of file cns3xxx.h.

#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */

Definition at line 25 of file cns3xxx.h.

#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000

Definition at line 26 of file cns3xxx.h.

#define CNS3XXX_PWR_CLK_EN ( BLOCK ) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)

Definition at line 505 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)

Definition at line 539 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)

Definition at line 540 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)

Definition at line 541 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_MODE_DFS (0)

Definition at line 514 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_MODE_DOZE (3)

Definition at line 517 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_MODE_HALT (2)

Definition at line 516 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)

Definition at line 519 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_MODE_IDLE (1)

Definition at line 515 of file cns3xxx.h.

#define CNS3XXX_PWR_CPU_MODE_SLEEP (4)

Definition at line 518 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL ( BLOCK ) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)

Definition at line 521 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK

Definition at line 522 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_300MHZ (0)

Definition at line 525 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_333MHZ (1)

Definition at line 526 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_366MHZ (2)

Definition at line 527 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_400MHZ (3)

Definition at line 528 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_433MHZ (4)

Definition at line 529 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_466MHZ (5)

Definition at line 530 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_500MHZ (6)

Definition at line 531 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_533MHZ (7)

Definition at line 532 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_566MHZ (8)

Definition at line 533 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_600MHZ (9)

Definition at line 534 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_633MHZ (10)

Definition at line 535 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_666MHZ (11)

Definition at line 536 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_CPU_700MHZ (12)

Definition at line 537 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)

Definition at line 544 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)

Definition at line 545 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)

Definition at line 546 of file cns3xxx.h.

#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)

Definition at line 547 of file cns3xxx.h.

#define CNS3XXX_PWR_SOFTWARE_RST ( BLOCK ) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)

Definition at line 508 of file cns3xxx.h.

#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */

Definition at line 155 of file cns3xxx.h.

#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000

Definition at line 156 of file cns3xxx.h.

#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */

Definition at line 82 of file cns3xxx.h.

#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000

Definition at line 83 of file cns3xxx.h.

#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */

Definition at line 169 of file cns3xxx.h.

#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000

Definition at line 171 of file cns3xxx.h.

#define CNS3XXX_SATA2_SIZE SZ_16M

Definition at line 170 of file cns3xxx.h.

#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */

Definition at line 176 of file cns3xxx.h.

#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000

Definition at line 177 of file cns3xxx.h.

#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */

Definition at line 37 of file cns3xxx.h.

#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000

Definition at line 38 of file cns3xxx.h.

#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */

Definition at line 20 of file cns3xxx.h.

#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */

Definition at line 31 of file cns3xxx.h.

#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000

Definition at line 32 of file cns3xxx.h.

#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */

Definition at line 22 of file cns3xxx.h.

#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000

Definition at line 23 of file cns3xxx.h.

#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */

Definition at line 232 of file cns3xxx.h.

#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100

Definition at line 233 of file cns3xxx.h.

#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */

Definition at line 238 of file cns3xxx.h.

#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000

Definition at line 239 of file cns3xxx.h.

#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */

Definition at line 241 of file cns3xxx.h.

#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000

Definition at line 242 of file cns3xxx.h.

#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */

Definition at line 229 of file cns3xxx.h.

#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000

Definition at line 230 of file cns3xxx.h.

#define CNS3XXX_TC11MP_TWD_BASE 0x90000600

Definition at line 235 of file cns3xxx.h.

#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600

Definition at line 236 of file cns3xxx.h.

#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */

Definition at line 132 of file cns3xxx.h.

#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800

Definition at line 133 of file cns3xxx.h.

#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */

Definition at line 111 of file cns3xxx.h.

#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000

Definition at line 112 of file cns3xxx.h.

#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */

Definition at line 114 of file cns3xxx.h.

#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000

Definition at line 115 of file cns3xxx.h.

#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */

Definition at line 117 of file cns3xxx.h.

#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000

Definition at line 118 of file cns3xxx.h.

#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */

Definition at line 167 of file cns3xxx.h.

#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */

Definition at line 185 of file cns3xxx.h.

#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */

Definition at line 164 of file cns3xxx.h.

#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000

Definition at line 165 of file cns3xxx.h.

#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)

Definition at line 572 of file cns3xxx.h.

#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)

Definition at line 564 of file cns3xxx.h.

#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)

Definition at line 585 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)

Definition at line 596 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)

Definition at line 597 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)

Definition at line 606 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)

Definition at line 607 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)

Definition at line 608 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)

Definition at line 609 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)

Definition at line 610 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)

Definition at line 611 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)

Definition at line 612 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)

Definition at line 613 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)

Definition at line 598 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)

Definition at line 599 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)

Definition at line 600 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)

Definition at line 601 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)

Definition at line 602 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)

Definition at line 603 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)

Definition at line 604 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)

Definition at line 605 of file cns3xxx.h.

#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)

Definition at line 595 of file cns3xxx.h.

#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)

Definition at line 621 of file cns3xxx.h.

#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)

Definition at line 622 of file cns3xxx.h.

#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)

Definition at line 623 of file cns3xxx.h.

#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)

Definition at line 567 of file cns3xxx.h.

#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)

Definition at line 568 of file cns3xxx.h.

#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)

Definition at line 565 of file cns3xxx.h.

#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)

Definition at line 586 of file cns3xxx.h.

#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)

Definition at line 563 of file cns3xxx.h.

#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)

Definition at line 560 of file cns3xxx.h.

#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)

Definition at line 558 of file cns3xxx.h.

#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)

Definition at line 566 of file cns3xxx.h.

#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)

Definition at line 587 of file cns3xxx.h.

#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)

Definition at line 615 of file cns3xxx.h.

#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)

Definition at line 588 of file cns3xxx.h.

#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)

Definition at line 616 of file cns3xxx.h.

#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)

Definition at line 561 of file cns3xxx.h.

#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)

Definition at line 556 of file cns3xxx.h.

#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)

Definition at line 592 of file cns3xxx.h.

#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)

Definition at line 559 of file cns3xxx.h.

#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)

Definition at line 591 of file cns3xxx.h.

#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)

Definition at line 557 of file cns3xxx.h.

#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)

Definition at line 593 of file cns3xxx.h.

#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)

Definition at line 562 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)

Definition at line 583 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)

Definition at line 577 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)

Definition at line 578 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)

Definition at line 576 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)

Definition at line 575 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)

Definition at line 581 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)

Definition at line 582 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)

Definition at line 580 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)

Definition at line 579 of file cns3xxx.h.

#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)

Definition at line 574 of file cns3xxx.h.

#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)

Definition at line 617 of file cns3xxx.h.

#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)

Definition at line 618 of file cns3xxx.h.

#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)

Definition at line 620 of file cns3xxx.h.

#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)

Definition at line 569 of file cns3xxx.h.

#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)

Definition at line 570 of file cns3xxx.h.

#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)

Definition at line 571 of file cns3xxx.h.

#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)

Definition at line 590 of file cns3xxx.h.

#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)

Definition at line 619 of file cns3xxx.h.

#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)

Definition at line 589 of file cns3xxx.h.

#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)

Definition at line 250 of file cns3xxx.h.

#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)

Definition at line 251 of file cns3xxx.h.

#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)

Definition at line 252 of file cns3xxx.h.

#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)

Definition at line 266 of file cns3xxx.h.

#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)

Definition at line 263 of file cns3xxx.h.

#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)

Definition at line 264 of file cns3xxx.h.

#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)

Definition at line 265 of file cns3xxx.h.

#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)

Definition at line 258 of file cns3xxx.h.

#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)

Definition at line 259 of file cns3xxx.h.

#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)

Definition at line 254 of file cns3xxx.h.

#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)

Definition at line 260 of file cns3xxx.h.

#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)

Definition at line 261 of file cns3xxx.h.

#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)

Definition at line 255 of file cns3xxx.h.

#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)

Definition at line 256 of file cns3xxx.h.

#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)

Definition at line 257 of file cns3xxx.h.

#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)

Definition at line 253 of file cns3xxx.h.

#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)

Definition at line 262 of file cns3xxx.h.

#define MISC_MEM_MAP ( offs ) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))

Definition at line 247 of file cns3xxx.h.

#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)

Definition at line 249 of file cns3xxx.h.

#define MISC_PCIE_AXIM_BMISC ( x ) MISC_MEM_MAP(0x958 + (x) * 0x100)

Definition at line 286 of file cns3xxx.h.

#define MISC_PCIE_AXIM_RMISC ( x ) MISC_MEM_MAP(0x954 + (x) * 0x100)

Definition at line 285 of file cns3xxx.h.

#define MISC_PCIE_AXIS_ARMISC ( x ) MISC_MEM_MAP(0x948 + (x) * 0x100)

Definition at line 282 of file cns3xxx.h.

#define MISC_PCIE_AXIS_AWMISC ( x ) MISC_MEM_MAP(0x944 + (x) * 0x100)

Definition at line 281 of file cns3xxx.h.

#define MISC_PCIE_AXIS_BMISC ( x ) MISC_MEM_MAP(0x950 + (x) * 0x100)

Definition at line 284 of file cns3xxx.h.

#define MISC_PCIE_AXIS_RMISC ( x ) MISC_MEM_MAP(0x94C + (x) * 0x100)

Definition at line 283 of file cns3xxx.h.

#define MISC_PCIE_CTRL ( x ) MISC_MEM_MAP(0x95C + (x) * 0x100)

Definition at line 287 of file cns3xxx.h.

#define MISC_PCIE_CXPL_DEBUGH ( x ) MISC_MEM_MAP(0x96C + (x) * 0x100)

Definition at line 291 of file cns3xxx.h.

#define MISC_PCIE_CXPL_DEBUGL ( x ) MISC_MEM_MAP(0x968 + (x) * 0x100)

Definition at line 290 of file cns3xxx.h.

#define MISC_PCIE_DIAG_DEBUGH ( x ) MISC_MEM_MAP(0x970 + (x) * 0x100)

Definition at line 292 of file cns3xxx.h.

#define MISC_PCIE_INT_MASK ( x ) MISC_MEM_MAP(0x978 + (x) * 0x100)

Definition at line 294 of file cns3xxx.h.

#define MISC_PCIE_INT_STATUS ( x ) MISC_MEM_MAP(0x97C + (x) * 0x100)

Definition at line 295 of file cns3xxx.h.

#define MISC_PCIE_PM_DEBUG ( x ) MISC_MEM_MAP(0x960 + (x) * 0x100)

Definition at line 288 of file cns3xxx.h.

#define MISC_PCIE_RFC_DEBUG ( x ) MISC_MEM_MAP(0x964 + (x) * 0x100)

Definition at line 289 of file cns3xxx.h.

#define MISC_PCIE_W1CLR ( x ) MISC_MEM_MAP(0x974 + (x) * 0x100)

Definition at line 293 of file cns3xxx.h.

#define MISC_PCIEPHY_CMCTL ( x ) MISC_MEM_MAP(0x900 + (x) * 0x004)

Definition at line 279 of file cns3xxx.h.

#define MISC_PCIEPHY_CTL ( x ) MISC_MEM_MAP(0x940 + (x) * 0x100)

Definition at line 280 of file cns3xxx.h.

#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)

Definition at line 270 of file cns3xxx.h.

#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)

Definition at line 267 of file cns3xxx.h.

#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)

Definition at line 268 of file cns3xxx.h.

#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)

Definition at line 272 of file cns3xxx.h.

#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)

Definition at line 273 of file cns3xxx.h.

#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)

Definition at line 274 of file cns3xxx.h.

#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)

Definition at line 275 of file cns3xxx.h.

#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)

Definition at line 276 of file cns3xxx.h.

#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)

Definition at line 277 of file cns3xxx.h.

#define NR_IRQS NR_IRQS_CNS3XXX

Definition at line 629 of file cns3xxx.h.

#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)

Definition at line 625 of file cns3xxx.h.

#define PM_CACTIVE_STA_OFFSET 0x0C

Definition at line 105 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)

Definition at line 305 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)

Definition at line 424 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_CIM (23)

Definition at line 402 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)

Definition at line 412 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_DMC (2)

Definition at line 422 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)

Definition at line 420 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)

Definition at line 415 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_GPU (24)

Definition at line 401 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)

Definition at line 413 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_I2S (21)

Definition at line 404 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)

Definition at line 403 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)

Definition at line 408 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)

Definition at line 407 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_RAID (20)

Definition at line 405 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_RTC (5)

Definition at line 419 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_SATA (19)

Definition at line 406 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)

Definition at line 400 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)

Definition at line 423 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)

Definition at line 421 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)

Definition at line 414 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)

Definition at line 411 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)

Definition at line 418 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)

Definition at line 417 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)

Definition at line 416 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)

Definition at line 409 of file cns3xxx.h.

#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)

Definition at line 410 of file cns3xxx.h.

#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)

Definition at line 307 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)

Definition at line 461 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)

Definition at line 462 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)

Definition at line 468 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)

Definition at line 465 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)

Definition at line 464 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)

Definition at line 455 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)

Definition at line 467 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)

Definition at line 454 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)

Definition at line 459 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)

Definition at line 460 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)

Definition at line 463 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)

Definition at line 457 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)

Definition at line 456 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)

Definition at line 469 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)

Definition at line 466 of file cns3xxx.h.

#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)

Definition at line 458 of file cns3xxx.h.

#define PM_CLK_GATE_OFFSET 0x00

Definition at line 102 of file cns3xxx.h.

#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)

Definition at line 302 of file cns3xxx.h.

#define PM_CLK_GATE_REG_MASK (0x03FFFFBA)

Definition at line 339 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_CIM (23)

Definition at line 319 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)

Definition at line 328 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_GDMA (4)

Definition at line 336 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_GPIO (10)

Definition at line 331 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_GPU (24)

Definition at line 318 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_HCIE (12)

Definition at line 329 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_I2S (21)

Definition at line 321 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_LCDC (22)

Definition at line 320 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_PCIE ( x ) (17 + (x))

Definition at line 324 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_RAID (20)

Definition at line 322 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_RTC (5)

Definition at line 335 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_SATA (19)

Definition at line 323 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_SDIO (25)

Definition at line 317 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)

Definition at line 338 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)

Definition at line 337 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)

Definition at line 330 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_TIMER (14)

Definition at line 327 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_UART1 (7)

Definition at line 334 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_UART2 (8)

Definition at line 333 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_UART3 (9)

Definition at line 332 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)

Definition at line 325 of file cns3xxx.h.

#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)

Definition at line 326 of file cns3xxx.h.

#define PM_CPU_CLK_DIV ( DIV )

Value:

{ \
    PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
    PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
}

Definition at line 471 of file cns3xxx.h.

#define PM_CSR_REG PMU_MEM_MAP(0x030)

Definition at line 314 of file cns3xxx.h.

#define PM_CSR_REG_OFFSET_CSR_EN (30)

Definition at line 502 of file cns3xxx.h.

#define PM_CSR_REG_OFFSET_CSR_NUM (0)

Definition at line 503 of file cns3xxx.h.

#define PM_HS_CFG_OFFSET 0x08

Definition at line 104 of file cns3xxx.h.

#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)

Definition at line 304 of file cns3xxx.h.

#define PM_HS_CFG_REG_MASK (0x03FFFFBE)

Definition at line 396 of file cns3xxx.h.

#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)

Definition at line 397 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_CIM (23)

Definition at line 374 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_CRYPTO (13)

Definition at line 384 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_DMC (2)

Definition at line 394 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_GDMA (4)

Definition at line 392 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_GPIO (10)

Definition at line 387 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_GPU (24)

Definition at line 373 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_HCIE (12)

Definition at line 385 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_I2S (21)

Definition at line 376 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_LCDC (22)

Definition at line 375 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_PCIE0 (17)

Definition at line 380 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_PCIE1 (18)

Definition at line 379 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_RAID (20)

Definition at line 377 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_RTC (5)

Definition at line 391 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_SATA (19)

Definition at line 378 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_SDIO (25)

Definition at line 372 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)

Definition at line 395 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)

Definition at line 393 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_SWITCH (11)

Definition at line 386 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_TIMER (14)

Definition at line 383 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_UART1 (7)

Definition at line 390 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_UART2 (8)

Definition at line 389 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_UART3 (9)

Definition at line 388 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_USB_HOST (16)

Definition at line 381 of file cns3xxx.h.

#define PM_HS_CFG_REG_OFFSET_USB_OTG (15)

Definition at line 382 of file cns3xxx.h.

#define PM_PLL_CPU_SEL ( CPU )

Value:

{ \
    PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
    PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
}

Definition at line 476 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)

Definition at line 309 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)

Definition at line 496 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)

Definition at line 492 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)

Definition at line 491 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)

Definition at line 493 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)

Definition at line 495 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)

Definition at line 494 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)

Definition at line 490 of file cns3xxx.h.

#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)

Definition at line 489 of file cns3xxx.h.

#define PM_PLL_HM_PD_OFFSET 0x1C

Definition at line 109 of file cns3xxx.h.

#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18

Definition at line 108 of file cns3xxx.h.

#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)

Definition at line 308 of file cns3xxx.h.

#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)

Definition at line 482 of file cns3xxx.h.

#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)

Definition at line 485 of file cns3xxx.h.

#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)

Definition at line 484 of file cns3xxx.h.

#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)

Definition at line 486 of file cns3xxx.h.

#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)

Definition at line 483 of file cns3xxx.h.

#define PM_PWR_STA_OFFSET 0x10

Definition at line 106 of file cns3xxx.h.

#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)

Definition at line 306 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)

Definition at line 451 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_CIM (23)

Definition at line 429 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)

Definition at line 439 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_DMC (2)

Definition at line 449 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)

Definition at line 447 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)

Definition at line 442 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_GPU (24)

Definition at line 428 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)

Definition at line 440 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_I2S (21)

Definition at line 431 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)

Definition at line 430 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)

Definition at line 435 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)

Definition at line 434 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_RAID (20)

Definition at line 432 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_RTC (5)

Definition at line 446 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_SATA (19)

Definition at line 433 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)

Definition at line 427 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)

Definition at line 450 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)

Definition at line 448 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)

Definition at line 441 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)

Definition at line 438 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)

Definition at line 445 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)

Definition at line 444 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)

Definition at line 443 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)

Definition at line 436 of file cns3xxx.h.

#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)

Definition at line 437 of file cns3xxx.h.

#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)

Definition at line 310 of file cns3xxx.h.

#define PM_SOFT_RST_OFFSET 0x04

Definition at line 103 of file cns3xxx.h.

#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)

Definition at line 303 of file cns3xxx.h.

#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)

Definition at line 369 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_CIM (23)

Definition at line 347 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_CPU0 (28)

Definition at line 344 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_CPU1 (29)

Definition at line 343 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_CRYPTO (13)

Definition at line 356 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_DMC (2)

Definition at line 366 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_GDMA (4)

Definition at line 364 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_GLOBAL (0)

Definition at line 368 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_GPIO (10)

Definition at line 359 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_GPU (24)

Definition at line 346 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_HCIE (12)

Definition at line 357 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_I2S (21)

Definition at line 349 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_LCDC (22)

Definition at line 348 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_PCIE ( x ) (17 + (x))

Definition at line 352 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_RAID (20)

Definition at line 350 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_RTC (5)

Definition at line 363 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_SATA (19)

Definition at line 351 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_SDIO (25)

Definition at line 345 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)

Definition at line 367 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)

Definition at line 365 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_SWITCH (11)

Definition at line 358 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_TIMER (14)

Definition at line 355 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_UART1 (7)

Definition at line 362 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_UART2 (8)

Definition at line 361 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_UART3 (9)

Definition at line 360 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_USB_HOST (16)

Definition at line 353 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_USB_OTG (15)

Definition at line 354 of file cns3xxx.h.

#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)

Definition at line 342 of file cns3xxx.h.

#define PM_SYS_CLK_CTRL_OFFSET 0x14

Definition at line 107 of file cns3xxx.h.

#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)

Definition at line 311 of file cns3xxx.h.

#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)

Definition at line 499 of file cns3xxx.h.

#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)

Definition at line 312 of file cns3xxx.h.

#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)

Definition at line 313 of file cns3xxx.h.

#define PMU_MEM_MAP ( offs ) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))

Definition at line 300 of file cns3xxx.h.

#define RTC_CTRL_OFFSET 0x20

Definition at line 93 of file cns3xxx.h.

#define RTC_DAY_OFFSET 0x0C

Definition at line 88 of file cns3xxx.h.

#define RTC_HOUR_ALM_OFFSET 0x18

Definition at line 91 of file cns3xxx.h.

#define RTC_HOUR_OFFSET 0x08

Definition at line 87 of file cns3xxx.h.

#define RTC_INTR_STS_OFFSET 0x34

Definition at line 94 of file cns3xxx.h.

#define RTC_MIN_ALM_OFFSET 0x14

Definition at line 90 of file cns3xxx.h.

#define RTC_MIN_OFFSET 0x04

Definition at line 86 of file cns3xxx.h.

#define RTC_REC_OFFSET 0x1C

Definition at line 92 of file cns3xxx.h.

#define RTC_SEC_ALM_OFFSET 0x10

Definition at line 89 of file cns3xxx.h.

#define RTC_SEC_OFFSET 0x00

Definition at line 85 of file cns3xxx.h.

#define SMC_DIRECT_CMD_OFFSET 0x010

Definition at line 44 of file cns3xxx.h.

#define SMC_ECC_ADDR0_OFFSET 0x310

Definition at line 61 of file cns3xxx.h.

#define SMC_ECC_ADDR1_OFFSET 0x314

Definition at line 62 of file cns3xxx.h.

#define SMC_ECC_MEMCFG_OFFSET 0x304

Definition at line 58 of file cns3xxx.h.

#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308

Definition at line 59 of file cns3xxx.h.

#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C

Definition at line 60 of file cns3xxx.h.

#define SMC_ECC_STATUS_OFFSET 0x300

Definition at line 57 of file cns3xxx.h.

#define SMC_ECC_VALUE0_OFFSET 0x318

Definition at line 63 of file cns3xxx.h.

#define SMC_ECC_VALUE1_OFFSET 0x31C

Definition at line 64 of file cns3xxx.h.

#define SMC_ECC_VALUE2_OFFSET 0x320

Definition at line 65 of file cns3xxx.h.

#define SMC_ECC_VALUE3_OFFSET 0x324

Definition at line 66 of file cns3xxx.h.

#define SMC_MEMC_CFG_CLR_OFFSET 0x00C

Definition at line 43 of file cns3xxx.h.

#define SMC_MEMC_CFG_SET_OFFSET 0x008

Definition at line 42 of file cns3xxx.h.

#define SMC_MEMC_STATUS_OFFSET 0x000

Definition at line 40 of file cns3xxx.h.

#define SMC_MEMIF_CFG_OFFSET 0x004

Definition at line 41 of file cns3xxx.h.

#define SMC_NAND_CYCLES0_0_OFFSET 0x100

Definition at line 50 of file cns3xxx.h.

#define SMC_NAND_CYCLES0_1_OFFSET 0x120

Definition at line 53 of file cns3xxx.h.

#define SMC_OPMODE0_0_OFFSET 0x104

Definition at line 51 of file cns3xxx.h.

#define SMC_OPMODE0_1_OFFSET 0x124

Definition at line 54 of file cns3xxx.h.

#define SMC_PCELL_ID_0_OFFSET 0xFF0

Definition at line 71 of file cns3xxx.h.

#define SMC_PCELL_ID_1_OFFSET 0xFF4

Definition at line 72 of file cns3xxx.h.

#define SMC_PCELL_ID_2_OFFSET 0xFF8

Definition at line 73 of file cns3xxx.h.

#define SMC_PCELL_ID_3_OFFSET 0xFFC

Definition at line 74 of file cns3xxx.h.

#define SMC_PERIPH_ID_0_OFFSET 0xFE0

Definition at line 67 of file cns3xxx.h.

#define SMC_PERIPH_ID_1_OFFSET 0xFE4

Definition at line 68 of file cns3xxx.h.

#define SMC_PERIPH_ID_2_OFFSET 0xFE8

Definition at line 69 of file cns3xxx.h.

#define SMC_PERIPH_ID_3_OFFSET 0xFEC

Definition at line 70 of file cns3xxx.h.

#define SMC_REFRESH_PERIOD_0_OFFSET 0x020

Definition at line 47 of file cns3xxx.h.

#define SMC_REFRESH_PERIOD_1_OFFSET 0x024

Definition at line 48 of file cns3xxx.h.

#define SMC_SET_CYCLES_OFFSET 0x014

Definition at line 45 of file cns3xxx.h.

#define SMC_SET_OPMODE_OFFSET 0x018

Definition at line 46 of file cns3xxx.h.

#define SMC_SRAM_CYCLES0_0_OFFSET 0x100

Definition at line 49 of file cns3xxx.h.

#define SMC_SRAM_CYCLES0_1_OFFSET 0x120

Definition at line 52 of file cns3xxx.h.

#define SMC_USER_CONFIG_OFFSET 0x204

Definition at line 56 of file cns3xxx.h.

#define SMC_USER_STATUS_OFFSET 0x200

Definition at line 55 of file cns3xxx.h.

#define TIMER1_2_CONTROL_OFFSET 0x30

Definition at line 145 of file cns3xxx.h.

#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38

Definition at line 147 of file cns3xxx.h.

#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34

Definition at line 146 of file cns3xxx.h.

#define TIMER1_AUTO_RELOAD_OFFSET 0x04

Definition at line 136 of file cns3xxx.h.

#define TIMER1_COUNTER_OFFSET 0x00

Definition at line 135 of file cns3xxx.h.

#define TIMER1_MATCH_V1_OFFSET 0x08

Definition at line 137 of file cns3xxx.h.

#define TIMER1_MATCH_V2_OFFSET 0x0C

Definition at line 138 of file cns3xxx.h.

#define TIMER2_AUTO_RELOAD_OFFSET 0x14

Definition at line 141 of file cns3xxx.h.

#define TIMER2_COUNTER_OFFSET 0x10

Definition at line 140 of file cns3xxx.h.

#define TIMER2_MATCH_V1_OFFSET 0x18

Definition at line 142 of file cns3xxx.h.

#define TIMER2_MATCH_V2_OFFSET 0x1C

Definition at line 143 of file cns3xxx.h.

#define TIMER_FREERUN_CONTROL_OFFSET 0x44

Definition at line 150 of file cns3xxx.h.

#define TIMER_FREERUN_OFFSET 0x40

Definition at line 149 of file cns3xxx.h.

Function Documentation

int cns3xxx_cpu_clock ( void )

Definition at line 107 of file pm.c.

void cns3xxx_pwr_clk_en ( unsigned int block )

Definition at line 18 of file pm.c.

void cns3xxx_pwr_soft_rst ( unsigned int block )

Definition at line 78 of file pm.c.

Macros

Functions

Macro Definition Documentation

Function Documentation