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cpu-tegra.c
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1 /*
2  * arch/arm/mach-tegra/cpu-tegra.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  * Colin Cross <[email protected]>
8  * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  */
20 
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/sched.h>
25 #include <linux/cpufreq.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/suspend.h>
32 
33 
34 #include <mach/clk.h>
35 
36 /* Frequency table index must be sequential starting at 0 */
37 static struct cpufreq_frequency_table freq_table[] = {
38  { 0, 216000 },
39  { 1, 312000 },
40  { 2, 456000 },
41  { 3, 608000 },
42  { 4, 760000 },
43  { 5, 816000 },
44  { 6, 912000 },
45  { 7, 1000000 },
46  { 8, CPUFREQ_TABLE_END },
47 };
48 
49 #define NUM_CPUS 2
50 
51 static struct clk *cpu_clk;
52 static struct clk *pll_x_clk;
53 static struct clk *pll_p_clk;
54 static struct clk *emc_clk;
55 
56 static unsigned long target_cpu_speed[NUM_CPUS];
57 static DEFINE_MUTEX(tegra_cpu_lock);
58 static bool is_suspended;
59 
60 static int tegra_verify_speed(struct cpufreq_policy *policy)
61 {
62  return cpufreq_frequency_table_verify(policy, freq_table);
63 }
64 
65 static unsigned int tegra_getspeed(unsigned int cpu)
66 {
67  unsigned long rate;
68 
69  if (cpu >= NUM_CPUS)
70  return 0;
71 
72  rate = clk_get_rate(cpu_clk) / 1000;
73  return rate;
74 }
75 
76 static int tegra_cpu_clk_set_rate(unsigned long rate)
77 {
78  int ret;
79 
80  /*
81  * Take an extra reference to the main pll so it doesn't turn
82  * off when we move the cpu off of it
83  */
84  clk_prepare_enable(pll_x_clk);
85 
86  ret = clk_set_parent(cpu_clk, pll_p_clk);
87  if (ret) {
88  pr_err("Failed to switch cpu to clock pll_p\n");
89  goto out;
90  }
91 
92  if (rate == clk_get_rate(pll_p_clk))
93  goto out;
94 
95  ret = clk_set_rate(pll_x_clk, rate);
96  if (ret) {
97  pr_err("Failed to change pll_x to %lu\n", rate);
98  goto out;
99  }
100 
101  ret = clk_set_parent(cpu_clk, pll_x_clk);
102  if (ret) {
103  pr_err("Failed to switch cpu to clock pll_x\n");
104  goto out;
105  }
106 
107 out:
108  clk_disable_unprepare(pll_x_clk);
109  return ret;
110 }
111 
112 static int tegra_update_cpu_speed(unsigned long rate)
113 {
114  int ret = 0;
115  struct cpufreq_freqs freqs;
116 
117  freqs.old = tegra_getspeed(0);
118  freqs.new = rate;
119 
120  if (freqs.old == freqs.new)
121  return ret;
122 
123  /*
124  * Vote on memory bus frequency based on cpu frequency
125  * This sets the minimum frequency, display or avp may request higher
126  */
127  if (rate >= 816000)
128  clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
129  else if (rate >= 456000)
130  clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
131  else
132  clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
133 
134  for_each_online_cpu(freqs.cpu)
136 
137 #ifdef CONFIG_CPU_FREQ_DEBUG
138  printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
139  freqs.old, freqs.new);
140 #endif
141 
142  ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
143  if (ret) {
144  pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
145  freqs.new);
146  return ret;
147  }
148 
149  for_each_online_cpu(freqs.cpu)
151 
152  return 0;
153 }
154 
155 static unsigned long tegra_cpu_highest_speed(void)
156 {
157  unsigned long rate = 0;
158  int i;
159 
161  rate = max(rate, target_cpu_speed[i]);
162  return rate;
163 }
164 
165 static int tegra_target(struct cpufreq_policy *policy,
166  unsigned int target_freq,
167  unsigned int relation)
168 {
169  unsigned int idx;
170  unsigned int freq;
171  int ret = 0;
172 
173  mutex_lock(&tegra_cpu_lock);
174 
175  if (is_suspended) {
176  ret = -EBUSY;
177  goto out;
178  }
179 
180  cpufreq_frequency_table_target(policy, freq_table, target_freq,
181  relation, &idx);
182 
183  freq = freq_table[idx].frequency;
184 
185  target_cpu_speed[policy->cpu] = freq;
186 
187  ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());
188 
189 out:
190  mutex_unlock(&tegra_cpu_lock);
191  return ret;
192 }
193 
194 static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
195  void *dummy)
196 {
197  mutex_lock(&tegra_cpu_lock);
198  if (event == PM_SUSPEND_PREPARE) {
199  is_suspended = true;
200  pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
201  freq_table[0].frequency);
202  tegra_update_cpu_speed(freq_table[0].frequency);
203  } else if (event == PM_POST_SUSPEND) {
204  is_suspended = false;
205  }
206  mutex_unlock(&tegra_cpu_lock);
207 
208  return NOTIFY_OK;
209 }
210 
211 static struct notifier_block tegra_cpu_pm_notifier = {
212  .notifier_call = tegra_pm_notify,
213 };
214 
215 static int tegra_cpu_init(struct cpufreq_policy *policy)
216 {
217  if (policy->cpu >= NUM_CPUS)
218  return -EINVAL;
219 
220  cpu_clk = clk_get_sys(NULL, "cpu");
221  if (IS_ERR(cpu_clk))
222  return PTR_ERR(cpu_clk);
223 
224  pll_x_clk = clk_get_sys(NULL, "pll_x");
225  if (IS_ERR(pll_x_clk))
226  return PTR_ERR(pll_x_clk);
227 
228  pll_p_clk = clk_get_sys(NULL, "pll_p");
229  if (IS_ERR(pll_p_clk))
230  return PTR_ERR(pll_p_clk);
231 
232  emc_clk = clk_get_sys("cpu", "emc");
233  if (IS_ERR(emc_clk)) {
234  clk_put(cpu_clk);
235  return PTR_ERR(emc_clk);
236  }
237 
238  clk_prepare_enable(emc_clk);
239  clk_prepare_enable(cpu_clk);
240 
241  cpufreq_frequency_table_cpuinfo(policy, freq_table);
242  cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
243  policy->cur = tegra_getspeed(policy->cpu);
244  target_cpu_speed[policy->cpu] = policy->cur;
245 
246  /* FIXME: what's the actual transition time? */
247  policy->cpuinfo.transition_latency = 300 * 1000;
248 
250  cpumask_copy(policy->related_cpus, cpu_possible_mask);
251 
252  if (policy->cpu == 0)
253  register_pm_notifier(&tegra_cpu_pm_notifier);
254 
255  return 0;
256 }
257 
258 static int tegra_cpu_exit(struct cpufreq_policy *policy)
259 {
260  cpufreq_frequency_table_cpuinfo(policy, freq_table);
261  clk_disable_unprepare(emc_clk);
262  clk_put(emc_clk);
263  clk_put(cpu_clk);
264  return 0;
265 }
266 
267 static struct freq_attr *tegra_cpufreq_attr[] = {
269  NULL,
270 };
271 
272 static struct cpufreq_driver tegra_cpufreq_driver = {
273  .verify = tegra_verify_speed,
274  .target = tegra_target,
275  .get = tegra_getspeed,
276  .init = tegra_cpu_init,
277  .exit = tegra_cpu_exit,
278  .name = "tegra",
279  .attr = tegra_cpufreq_attr,
280 };
281 
282 static int __init tegra_cpufreq_init(void)
283 {
284  return cpufreq_register_driver(&tegra_cpufreq_driver);
285 }
286 
287 static void __exit tegra_cpufreq_exit(void)
288 {
289  cpufreq_unregister_driver(&tegra_cpufreq_driver);
290 }
291 
292 
293 MODULE_AUTHOR("Colin Cross <[email protected]>");
294 MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
295 MODULE_LICENSE("GPL");
296 module_init(tegra_cpufreq_init);
297 module_exit(tegra_cpufreq_exit);