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crystalhd_hw.h File Reference
#include "crystalhd.h"

Go to the source code of this file.

Data Structures

union  addr_64
 
union  intr_mask_reg
 
union  link_misc_perst_deco_ctrl
 
union  link_misc_perst_clk_ctrl
 
union  link_misc_perst_decoder_ctrl
 
union  desc_low_addr_reg
 
struct  dma_descriptor
 
struct  dma_desc_mem
 
struct  tx_dma_pkt
 
struct  crystalhd_rx_dma_pkt
 
struct  crystalhd_hw_stats
 
struct  crystalhd_hw
 

Macros

#define DMA_ENGINE_CNT   2
 
#define MAX_PIB_Q_DEPTH   64
 
#define MIN_PIB_Q_DEPTH   2
 
#define WR_POINTER_OFF   4
 
#define ASPM_L1_ENABLE   (BC_BIT(27))
 
#define FW_CMD_BUFF_SZ   64
 
#define TS_Host2CpuSnd   0x00000100
 
#define Hst2CpuMbx1   0x00100F00
 
#define Cpu2HstMbx1   0x00100F04
 
#define MbxStat1   0x00100F08
 
#define Stream2Host_Intr_Sts   0x00100F24
 
#define C011_RET_SUCCESS   0x0 /* Reutrn status of firmware command. */
 
#define TS_StreamAFIFOStatus   0x0010044C
 
#define TS_StreamBFIFOStatus   0x0010084C
 
#define UartSelectA   0x00100300
 
#define UartSelectB   0x00100304
 
#define BSVS_UART_DEC_NONE   0x00
 
#define BSVS_UART_DEC_OUTER   0x01
 
#define BSVS_UART_DEC_INNER   0x02
 
#define BSVS_UART_STREAM   0x03
 
#define REG_DecCA_RegCinCTL   0xa00
 
#define REG_DecCA_RegCinBase   0xa0c
 
#define REG_DecCA_RegCinEnd   0xa10
 
#define REG_DecCA_RegCinWrPtr   0xa04
 
#define REG_DecCA_RegCinRdPtr   0xa08
 
#define REG_Dec_TsUser0Base   0x100864
 
#define REG_Dec_TsUser0Rdptr   0x100868
 
#define REG_Dec_TsUser0Wrptr   0x10086C
 
#define REG_Dec_TsUser0End   0x100874
 
#define REG_Dec_TsAudCDB2Base   0x10036c
 
#define REG_Dec_TsAudCDB2Rdptr   0x100378
 
#define REG_Dec_TsAudCDB2Wrptr   0x100374
 
#define REG_Dec_TsAudCDB2End   0x100370
 
#define SDRAM_PARAM   0x00040804
 
#define SDRAM_PRECHARGE   0x000408B0
 
#define SDRAM_EXT_MODE   0x000408A4
 
#define SDRAM_MODE   0x000408A0
 
#define SDRAM_REFRESH   0x00040890
 
#define SDRAM_REF_PARAM   0x00040808
 
#define DecHt_PllACtl   0x34000C
 
#define DecHt_PllBCtl   0x340010
 
#define DecHt_PllCCtl   0x340014
 
#define DecHt_PllDCtl   0x340034
 
#define DecHt_PllECtl   0x340038
 
#define AUD_DSP_MISC_SOFT_RESET   0x00240104
 
#define AIO_MISC_PLL_RESET   0x0026000C
 
#define PCIE_CLK_REQ_REG   0xDC
 
#define PCI_CLK_REQ_ENABLE   (BC_BIT(8))
 
#define BC_FWIMG_ST_ADDR   0x00000000
 
#define rotr32_1(x, n)   (((x) >> n) | ((x) << (32 - n)))
 
#define bswap_32_1(x)   ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))
 
#define DecHt_HostSwReset   0x340000
 
#define BC_DRAM_FW_CFG_ADDR   0x001c2000
 
#define CLOCK_PRESET   175
 
#define DMA_START_BIT   MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK
 
#define GET_RX_INTR_MASK
 
#define GET_Y0_ERR_MSK
 
#define GET_UV0_ERR_MSK
 
#define GET_Y1_ERR_MSK
 
#define GET_UV1_ERR_MSK
 

Enumerations

enum  list_sts {
  sts_free = 0, rx_waiting_y_intr = 0x00000001, rx_y_error = 0x00000004, rx_waiting_uv_intr = 0x0000100,
  rx_uv_error = 0x0000400, rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr), rx_sts_error = (rx_y_error|rx_uv_error), rx_y_mask = 0x000000FF,
  rx_uv_mask = 0x0000FF00
}
 

Functions

enum BC_STATUS crystalhd_download_fw (struct crystalhd_adp *adp, void *buffer, uint32_t sz)
 
enum BC_STATUS crystalhd_do_fw_cmd (struct crystalhd_hw *hw, struct BC_FW_CMD *fw_cmd)
 
bool crystalhd_hw_interrupt (struct crystalhd_adp *adp, struct crystalhd_hw *hw)
 
enum BC_STATUS crystalhd_hw_open (struct crystalhd_hw *, struct crystalhd_adp *)
 
enum BC_STATUS crystalhd_hw_close (struct crystalhd_hw *)
 
enum BC_STATUS crystalhd_hw_setup_dma_rings (struct crystalhd_hw *)
 
enum BC_STATUS crystalhd_hw_free_dma_rings (struct crystalhd_hw *)
 
enum BC_STATUS crystalhd_hw_post_tx (struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, hw_comp_callback call_back, wait_queue_head_t *cb_event, uint32_t *list_id, uint8_t data_flags)
 
enum BC_STATUS crystalhd_hw_pause (struct crystalhd_hw *hw)
 
enum BC_STATUS crystalhd_hw_unpause (struct crystalhd_hw *hw)
 
enum BC_STATUS crystalhd_hw_suspend (struct crystalhd_hw *hw)
 
enum BC_STATUS crystalhd_hw_cancel_tx (struct crystalhd_hw *hw, uint32_t list_id)
 
enum BC_STATUS crystalhd_hw_add_cap_buffer (struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, bool en_post)
 
enum BC_STATUS crystalhd_hw_get_cap_buffer (struct crystalhd_hw *hw, struct BC_PIC_INFO_BLOCK *pib, struct crystalhd_dio_req **ioreq)
 
enum BC_STATUS crystalhd_hw_stop_capture (struct crystalhd_hw *hw)
 
enum BC_STATUS crystalhd_hw_start_capture (struct crystalhd_hw *hw)
 
void crystalhd_hw_stats (struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats)
 
enum BC_STATUS crystalhd_hw_set_core_clock (struct crystalhd_hw *)
 

Macro Definition Documentation

#define AIO_MISC_PLL_RESET   0x0026000C

Definition at line 96 of file crystalhd_hw.h.

#define ASPM_L1_ENABLE   (BC_BIT(27))

Definition at line 38 of file crystalhd_hw.h.

#define AUD_DSP_MISC_SOFT_RESET   0x00240104

Definition at line 95 of file crystalhd_hw.h.

#define BC_DRAM_FW_CFG_ADDR   0x001c2000

Definition at line 109 of file crystalhd_hw.h.

#define BC_FWIMG_ST_ADDR   0x00000000

Definition at line 103 of file crystalhd_hw.h.

#define BSVS_UART_DEC_INNER   0x02

Definition at line 61 of file crystalhd_hw.h.

#define BSVS_UART_DEC_NONE   0x00

Definition at line 59 of file crystalhd_hw.h.

#define BSVS_UART_DEC_OUTER   0x01

Definition at line 60 of file crystalhd_hw.h.

#define BSVS_UART_STREAM   0x03

Definition at line 62 of file crystalhd_hw.h.

#define bswap_32_1 (   x)    ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))

Definition at line 106 of file crystalhd_hw.h.

#define C011_RET_SUCCESS   0x0 /* Reutrn status of firmware command. */

Definition at line 49 of file crystalhd_hw.h.

#define CLOCK_PRESET   175

Definition at line 323 of file crystalhd_hw.h.

#define Cpu2HstMbx1   0x00100F04

Definition at line 46 of file crystalhd_hw.h.

#define DecHt_HostSwReset   0x340000

Definition at line 108 of file crystalhd_hw.h.

#define DecHt_PllACtl   0x34000C

Definition at line 90 of file crystalhd_hw.h.

#define DecHt_PllBCtl   0x340010

Definition at line 91 of file crystalhd_hw.h.

#define DecHt_PllCCtl   0x340014

Definition at line 92 of file crystalhd_hw.h.

#define DecHt_PllDCtl   0x340034

Definition at line 93 of file crystalhd_hw.h.

#define DecHt_PllECtl   0x340038

Definition at line 94 of file crystalhd_hw.h.

#define DMA_ENGINE_CNT   2

Definition at line 33 of file crystalhd_hw.h.

#define DMA_START_BIT   MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK

Definition at line 326 of file crystalhd_hw.h.

#define FW_CMD_BUFF_SZ   64

Definition at line 43 of file crystalhd_hw.h.

#define GET_RX_INTR_MASK
Value:
(INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \
INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \
INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \
INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \
INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \
INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \
INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \
INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK)

Definition at line 328 of file crystalhd_hw.h.

#define GET_UV0_ERR_MSK
Value:
(MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)

Definition at line 342 of file crystalhd_hw.h.

#define GET_UV1_ERR_MSK
Value:
(MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)

Definition at line 352 of file crystalhd_hw.h.

#define GET_Y0_ERR_MSK
Value:
(MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)

Definition at line 337 of file crystalhd_hw.h.

#define GET_Y1_ERR_MSK
Value:
(MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)

Definition at line 347 of file crystalhd_hw.h.

#define Hst2CpuMbx1   0x00100F00

Definition at line 45 of file crystalhd_hw.h.

#define MAX_PIB_Q_DEPTH   64

Definition at line 34 of file crystalhd_hw.h.

#define MbxStat1   0x00100F08

Definition at line 47 of file crystalhd_hw.h.

#define MIN_PIB_Q_DEPTH   2

Definition at line 35 of file crystalhd_hw.h.

#define PCI_CLK_REQ_ENABLE   (BC_BIT(8))

Definition at line 98 of file crystalhd_hw.h.

#define PCIE_CLK_REQ_REG   0xDC

Definition at line 97 of file crystalhd_hw.h.

#define REG_Dec_TsAudCDB2Base   0x10036c

Definition at line 77 of file crystalhd_hw.h.

#define REG_Dec_TsAudCDB2End   0x100370

Definition at line 80 of file crystalhd_hw.h.

#define REG_Dec_TsAudCDB2Rdptr   0x100378

Definition at line 78 of file crystalhd_hw.h.

#define REG_Dec_TsAudCDB2Wrptr   0x100374

Definition at line 79 of file crystalhd_hw.h.

#define REG_Dec_TsUser0Base   0x100864

Definition at line 71 of file crystalhd_hw.h.

#define REG_Dec_TsUser0End   0x100874

Definition at line 74 of file crystalhd_hw.h.

#define REG_Dec_TsUser0Rdptr   0x100868

Definition at line 72 of file crystalhd_hw.h.

#define REG_Dec_TsUser0Wrptr   0x10086C

Definition at line 73 of file crystalhd_hw.h.

#define REG_DecCA_RegCinBase   0xa0c

Definition at line 66 of file crystalhd_hw.h.

#define REG_DecCA_RegCinCTL   0xa00

Definition at line 65 of file crystalhd_hw.h.

#define REG_DecCA_RegCinEnd   0xa10

Definition at line 67 of file crystalhd_hw.h.

#define REG_DecCA_RegCinRdPtr   0xa08

Definition at line 69 of file crystalhd_hw.h.

#define REG_DecCA_RegCinWrPtr   0xa04

Definition at line 68 of file crystalhd_hw.h.

#define rotr32_1 (   x,
  n 
)    (((x) >> n) | ((x) << (32 - n)))

Definition at line 105 of file crystalhd_hw.h.

#define SDRAM_EXT_MODE   0x000408A4

Definition at line 85 of file crystalhd_hw.h.

#define SDRAM_MODE   0x000408A0

Definition at line 86 of file crystalhd_hw.h.

#define SDRAM_PARAM   0x00040804

Definition at line 83 of file crystalhd_hw.h.

#define SDRAM_PRECHARGE   0x000408B0

Definition at line 84 of file crystalhd_hw.h.

#define SDRAM_REF_PARAM   0x00040808

Definition at line 88 of file crystalhd_hw.h.

#define SDRAM_REFRESH   0x00040890

Definition at line 87 of file crystalhd_hw.h.

#define Stream2Host_Intr_Sts   0x00100F24

Definition at line 48 of file crystalhd_hw.h.

#define TS_Host2CpuSnd   0x00000100

Definition at line 44 of file crystalhd_hw.h.

#define TS_StreamAFIFOStatus   0x0010044C

Definition at line 52 of file crystalhd_hw.h.

#define TS_StreamBFIFOStatus   0x0010084C

Definition at line 53 of file crystalhd_hw.h.

#define UartSelectA   0x00100300

Definition at line 56 of file crystalhd_hw.h.

#define UartSelectB   0x00100304

Definition at line 57 of file crystalhd_hw.h.

#define WR_POINTER_OFF   4

Definition at line 36 of file crystalhd_hw.h.

Enumeration Type Documentation

enum list_sts
Enumerator:
sts_free 
rx_waiting_y_intr 
rx_y_error 
rx_waiting_uv_intr 
rx_uv_error 
rx_sts_waiting 
rx_sts_error 
rx_y_mask 
rx_uv_mask 

Definition at line 235 of file crystalhd_hw.h.

Function Documentation

enum BC_STATUS crystalhd_do_fw_cmd ( struct crystalhd_hw *  hw,
struct BC_FW_CMD *  fw_cmd 
)

Definition at line 1716 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_download_fw ( struct crystalhd_adp *  adp,
void *  buffer,
uint32_t  sz 
)

Definition at line 1625 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_add_cap_buffer ( struct crystalhd_hw *  hw,
struct crystalhd_dio_req *  ioreq,
bool  en_post 
)

Definition at line 2136 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_cancel_tx ( struct crystalhd_hw *  hw,
uint32_t  list_id 
)

Definition at line 2123 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_close ( struct crystalhd_hw *  )

Definition at line 1887 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_free_dma_rings ( struct crystalhd_hw *  )

Definition at line 1978 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_get_cap_buffer ( struct crystalhd_hw *  hw,
struct BC_PIC_INFO_BLOCK *  pib,
struct crystalhd_dio_req **  ioreq 
)

Definition at line 2176 of file crystalhd_hw.c.

bool crystalhd_hw_interrupt ( struct crystalhd_adp *  adp,
struct crystalhd_hw *  hw 
)

Definition at line 1796 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_open ( struct crystalhd_hw *  ,
struct crystalhd_adp *   
)

Definition at line 1855 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_pause ( struct crystalhd_hw *  hw)

Definition at line 2257 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_post_tx ( struct crystalhd_hw *  hw,
struct crystalhd_dio_req *  ioreq,
hw_comp_callback  call_back,
wait_queue_head_t *  cb_event,
uint32_t *  list_id,
uint8_t  data_flags 
)

Definition at line 2016 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_set_core_clock ( struct crystalhd_hw *  )

Definition at line 2326 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_setup_dma_rings ( struct crystalhd_hw *  )

Definition at line 1904 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_start_capture ( struct crystalhd_hw *  hw)

Definition at line 2212 of file crystalhd_hw.c.

void crystalhd_hw_stats ( struct crystalhd_hw *  hw,
struct crystalhd_hw_stats *  stats 
)

Definition at line 2308 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_stop_capture ( struct crystalhd_hw *  hw)

Definition at line 2237 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_suspend ( struct crystalhd_hw *  hw)

Definition at line 2285 of file crystalhd_hw.c.

enum BC_STATUS crystalhd_hw_unpause ( struct crystalhd_hw *  hw)

Definition at line 2269 of file crystalhd_hw.c.

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