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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/slab.h>#include <linux/init.h>#include <linux/module.h>#include <linux/delay.h>#include <linux/mtd/mtd.h>#include <linux/mtd/nand.h>#include <linux/mtd/nand_ecc.h>#include <linux/mtd/partitions.h>#include <asm/msr.h>#include <asm/io.h>Go to the source code of this file.
Macros | |
| #define | NR_CS553X_CONTROLLERS 4 |
| #define | MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */ |
| #define | CAP_CS5535 0x2df000ULL |
| #define | CAP_CS5536 0x5df500ULL |
| #define | MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */ |
| #define | MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */ |
| #define | MSR_NANDF_RSVD 0x5140001d /* Reserved */ |
| #define | MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */ |
| #define | MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */ |
| #define | MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */ |
| #define | MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */ |
| #define | FLSH_LBAR_EN (1ULL<<32) |
| #define | FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */ |
| #define | FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */ |
| #define | MSR_DIVIL_BALL_OPTS 0x51400015 |
| #define | PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */ |
| #define | MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */ |
| #define | MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */ |
| #define | MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */ |
| #define | MM_NAND_STS 0x810 |
| #define | MM_NAND_ECC_LSB 0x811 |
| #define | MM_NAND_ECC_MSB 0x812 |
| #define | MM_NAND_ECC_COL 0x813 |
| #define | MM_NAND_LAC 0x814 |
| #define | MM_NAND_ECC_CTL 0x815 |
| #define | IO_NAND_DATA 0x00 /* 0 to 3, in fact */ |
| #define | IO_NAND_CTL 0x04 |
| #define | IO_NAND_IO 0x05 |
| #define | IO_NAND_STS 0x06 |
| #define | IO_NAND_ECC_CTL 0x08 |
| #define | IO_NAND_ECC_LSB 0x09 |
| #define | IO_NAND_ECC_MSB 0x0a |
| #define | IO_NAND_ECC_COL 0x0b |
| #define | IO_NAND_LAC 0x0c |
| #define | CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */ |
| #define | CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */ |
| #define | CS_NAND_CTL_ALE (1<<2) |
| #define | CS_NAND_CTL_CLE (1<<1) |
| #define | CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */ |
| #define | CS_NAND_STS_FLASH_RDY (1<<3) |
| #define | CS_NAND_CTLR_BUSY (1<<2) |
| #define | CS_NAND_CMD_COMP (1<<1) |
| #define | CS_NAND_DIST_ST (1<<0) |
| #define | CS_NAND_ECC_PARITY (1<<2) |
| #define | CS_NAND_ECC_CLRECC (1<<1) |
| #define | CS_NAND_ECC_ENECC (1<<0) |
Functions | |
| module_init (cs553x_init) | |
| module_exit (cs553x_cleanup) | |
| MODULE_LICENSE ("GPL") | |
| MODULE_AUTHOR ("David Woodhouse <[email protected]>") | |
| MODULE_DESCRIPTION ("NAND controller driver for AMD CS5535/CS5536 companion chip") | |
| #define CAP_CS5535 0x2df000ULL |
Definition at line 37 of file cs553x_nand.c.
| #define CAP_CS5536 0x5df500ULL |
Definition at line 38 of file cs553x_nand.c.
| #define CS_NAND_CMD_COMP (1<<1) |
Definition at line 91 of file cs553x_nand.c.
| #define CS_NAND_CTL_ALE (1<<2) |
Definition at line 85 of file cs553x_nand.c.
Definition at line 87 of file cs553x_nand.c.
| #define CS_NAND_CTL_CLE (1<<1) |
Definition at line 86 of file cs553x_nand.c.
| #define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */ |
Definition at line 83 of file cs553x_nand.c.
Definition at line 84 of file cs553x_nand.c.
| #define CS_NAND_CTLR_BUSY (1<<2) |
Definition at line 90 of file cs553x_nand.c.
| #define CS_NAND_DIST_ST (1<<0) |
Definition at line 92 of file cs553x_nand.c.
| #define CS_NAND_ECC_CLRECC (1<<1) |
Definition at line 95 of file cs553x_nand.c.
| #define CS_NAND_ECC_ENECC (1<<0) |
Definition at line 96 of file cs553x_nand.c.
| #define CS_NAND_ECC_PARITY (1<<2) |
Definition at line 94 of file cs553x_nand.c.
| #define CS_NAND_STS_FLASH_RDY (1<<3) |
Definition at line 89 of file cs553x_nand.c.
| #define FLSH_LBAR_EN (1ULL<<32) |
Definition at line 51 of file cs553x_nand.c.
| #define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */ |
Definition at line 53 of file cs553x_nand.c.
| #define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */ |
Definition at line 52 of file cs553x_nand.c.
| #define IO_NAND_CTL 0x04 |
Definition at line 74 of file cs553x_nand.c.
| #define IO_NAND_DATA 0x00 /* 0 to 3, in fact */ |
Definition at line 73 of file cs553x_nand.c.
| #define IO_NAND_ECC_COL 0x0b |
Definition at line 80 of file cs553x_nand.c.
| #define IO_NAND_ECC_CTL 0x08 |
Definition at line 77 of file cs553x_nand.c.
| #define IO_NAND_ECC_LSB 0x09 |
Definition at line 78 of file cs553x_nand.c.
| #define IO_NAND_ECC_MSB 0x0a |
Definition at line 79 of file cs553x_nand.c.
| #define IO_NAND_IO 0x05 |
Definition at line 75 of file cs553x_nand.c.
| #define IO_NAND_LAC 0x0c |
Definition at line 81 of file cs553x_nand.c.
| #define IO_NAND_STS 0x06 |
Definition at line 76 of file cs553x_nand.c.
| #define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */ |
Definition at line 63 of file cs553x_nand.c.
| #define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */ |
Definition at line 62 of file cs553x_nand.c.
| #define MM_NAND_ECC_COL 0x813 |
Definition at line 68 of file cs553x_nand.c.
| #define MM_NAND_ECC_CTL 0x815 |
Definition at line 70 of file cs553x_nand.c.
| #define MM_NAND_ECC_LSB 0x811 |
Definition at line 66 of file cs553x_nand.c.
| #define MM_NAND_ECC_MSB 0x812 |
Definition at line 67 of file cs553x_nand.c.
| #define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */ |
Definition at line 64 of file cs553x_nand.c.
| #define MM_NAND_LAC 0x814 |
Definition at line 69 of file cs553x_nand.c.
| #define MM_NAND_STS 0x810 |
Definition at line 65 of file cs553x_nand.c.
| #define MSR_DIVIL_BALL_OPTS 0x51400015 |
Definition at line 58 of file cs553x_nand.c.
| #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */ |
Definition at line 36 of file cs553x_nand.c.
| #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */ |
Definition at line 46 of file cs553x_nand.c.
| #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */ |
Definition at line 47 of file cs553x_nand.c.
| #define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */ |
Definition at line 48 of file cs553x_nand.c.
| #define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */ |
Definition at line 49 of file cs553x_nand.c.
| #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */ |
Definition at line 42 of file cs553x_nand.c.
| #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */ |
Definition at line 41 of file cs553x_nand.c.
| #define MSR_NANDF_RSVD 0x5140001d /* Reserved */ |
Definition at line 43 of file cs553x_nand.c.
| #define NR_CS553X_CONTROLLERS 4 |
Definition at line 34 of file cs553x_nand.c.
Definition at line 59 of file cs553x_nand.c.
| MODULE_AUTHOR | ( | "David Woodhouse <[email protected]>" | ) |
| MODULE_DESCRIPTION | ( | "NAND controller driver for AMD CS5535/CS5536 companion chip" | ) |
| module_exit | ( | cs553x_cleanup | ) |
| module_init | ( | cs553x_init | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
1.8.2