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ctxnv40.c
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1 /*
2  * Copyright 2009 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 
25 #include <core/gpuobj.h>
26 
27 /* NVIDIA context programs handle a number of other conditions which are
28  * not implemented in our versions. It's not clear why NVIDIA context
29  * programs have this code, nor whether it's strictly necessary for
30  * correct operation. We'll implement additional handling if/when we
31  * discover it's necessary.
32  *
33  * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
34  * flag is set, this gets saved into the context.
35  * - On context save, the context program for all cards load nsource
36  * into a flag register and check for ILLEGAL_MTHD. If it's set,
37  * opcode 0x60000d is called before resuming normal operation.
38  * - Some context programs check more conditions than the above. NV44
39  * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
40  * and calls 0x60000d before resuming normal operation.
41  * - At the very beginning of NVIDIA's context programs, flag 9 is checked
42  * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
43  * and then the ctxprog is aborted. It looks like a complicated NOP,
44  * its purpose is unknown.
45  * - In the section of code that loads the per-vs state, NVIDIA check
46  * flag 10. If it's set, they only transfer the small 0x300 byte block
47  * of state + the state for a single vs as opposed to the state for
48  * all vs units. It doesn't seem likely that it'll occur in normal
49  * operation, especially seeing as it appears NVIDIA may have screwed
50  * up the ctxprogs for some cards and have an invalid instruction
51  * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction.
52  * - There's a number of places where context offset 0 (where we place
53  * the PRAMIN offset of the context) is loaded into either 0x408000,
54  * 0x408004 or 0x408008. Not sure what's up there either.
55  * - The ctxprogs for some cards save 0x400a00 again during the cleanup
56  * path for auto-loadctx.
57  */
58 
59 #define CP_FLAG_CLEAR 0
60 #define CP_FLAG_SET 1
61 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
62 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
63 #define CP_FLAG_SWAP_DIRECTION_SAVE 1
64 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
65 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
66 #define CP_FLAG_USER_SAVE_PENDING 1
67 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
68 #define CP_FLAG_USER_LOAD_NOT_PENDING 0
69 #define CP_FLAG_USER_LOAD_PENDING 1
70 #define CP_FLAG_STATUS ((3 * 32) + 0)
71 #define CP_FLAG_STATUS_IDLE 0
72 #define CP_FLAG_STATUS_BUSY 1
73 #define CP_FLAG_AUTO_SAVE ((3 * 32) + 4)
74 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
75 #define CP_FLAG_AUTO_SAVE_PENDING 1
76 #define CP_FLAG_AUTO_LOAD ((3 * 32) + 5)
77 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
78 #define CP_FLAG_AUTO_LOAD_PENDING 1
79 #define CP_FLAG_UNK54 ((3 * 32) + 6)
80 #define CP_FLAG_UNK54_CLEAR 0
81 #define CP_FLAG_UNK54_SET 1
82 #define CP_FLAG_ALWAYS ((3 * 32) + 8)
83 #define CP_FLAG_ALWAYS_FALSE 0
84 #define CP_FLAG_ALWAYS_TRUE 1
85 #define CP_FLAG_UNK57 ((3 * 32) + 9)
86 #define CP_FLAG_UNK57_CLEAR 0
87 #define CP_FLAG_UNK57_SET 1
88 
89 #define CP_CTX 0x00100000
90 #define CP_CTX_COUNT 0x000fc000
91 #define CP_CTX_COUNT_SHIFT 14
92 #define CP_CTX_REG 0x00003fff
93 #define CP_LOAD_SR 0x00200000
94 #define CP_LOAD_SR_VALUE 0x000fffff
95 #define CP_BRA 0x00400000
96 #define CP_BRA_IP 0x0000ff00
97 #define CP_BRA_IP_SHIFT 8
98 #define CP_BRA_IF_CLEAR 0x00000080
99 #define CP_BRA_FLAG 0x0000007f
100 #define CP_WAIT 0x00500000
101 #define CP_WAIT_SET 0x00000080
102 #define CP_WAIT_FLAG 0x0000007f
103 #define CP_SET 0x00700000
104 #define CP_SET_1 0x00000080
105 #define CP_SET_FLAG 0x0000007f
106 #define CP_NEXT_TO_SWAP 0x00600007
107 #define CP_NEXT_TO_CURRENT 0x00600009
108 #define CP_SET_CONTEXT_POINTER 0x0060000a
109 #define CP_END 0x0060000e
110 #define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */
111 #define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */
112 #define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */
113 
114 #include "nv40.h"
115 #include "ctx.h"
116 
117 /* TODO:
118  * - get vs count from 0x1540
119  */
120 
121 static int
122 nv40_graph_vs_count(struct nouveau_device *device)
123 {
124 
125  switch (device->chipset) {
126  case 0x47:
127  case 0x49:
128  case 0x4b:
129  return 8;
130  case 0x40:
131  return 6;
132  case 0x41:
133  case 0x42:
134  return 5;
135  case 0x43:
136  case 0x44:
137  case 0x46:
138  case 0x4a:
139  return 3;
140  case 0x4c:
141  case 0x4e:
142  case 0x67:
143  default:
144  return 1;
145  }
146 }
147 
148 
149 enum cp_label {
150  cp_check_load = 1,
151  cp_setup_auto_load,
152  cp_setup_load,
153  cp_setup_save,
154  cp_swap_state,
155  cp_swap_state3d_3_is_save,
156  cp_prepare_exit,
157  cp_exit,
158 };
159 
160 static void
161 nv40_graph_construct_general(struct nouveau_grctx *ctx)
162 {
163  struct nouveau_device *device = ctx->device;
164  int i;
165 
166  cp_ctx(ctx, 0x4000a4, 1);
167  gr_def(ctx, 0x4000a4, 0x00000008);
168  cp_ctx(ctx, 0x400144, 58);
169  gr_def(ctx, 0x400144, 0x00000001);
170  cp_ctx(ctx, 0x400314, 1);
171  gr_def(ctx, 0x400314, 0x00000000);
172  cp_ctx(ctx, 0x400400, 10);
173  cp_ctx(ctx, 0x400480, 10);
174  cp_ctx(ctx, 0x400500, 19);
175  gr_def(ctx, 0x400514, 0x00040000);
176  gr_def(ctx, 0x400524, 0x55555555);
177  gr_def(ctx, 0x400528, 0x55555555);
178  gr_def(ctx, 0x40052c, 0x55555555);
179  gr_def(ctx, 0x400530, 0x55555555);
180  cp_ctx(ctx, 0x400560, 6);
181  gr_def(ctx, 0x400568, 0x0000ffff);
182  gr_def(ctx, 0x40056c, 0x0000ffff);
183  cp_ctx(ctx, 0x40057c, 5);
184  cp_ctx(ctx, 0x400710, 3);
185  gr_def(ctx, 0x400710, 0x20010001);
186  gr_def(ctx, 0x400714, 0x0f73ef00);
187  cp_ctx(ctx, 0x400724, 1);
188  gr_def(ctx, 0x400724, 0x02008821);
189  cp_ctx(ctx, 0x400770, 3);
190  if (device->chipset == 0x40) {
191  cp_ctx(ctx, 0x400814, 4);
192  cp_ctx(ctx, 0x400828, 5);
193  cp_ctx(ctx, 0x400840, 5);
194  gr_def(ctx, 0x400850, 0x00000040);
195  cp_ctx(ctx, 0x400858, 4);
196  gr_def(ctx, 0x400858, 0x00000040);
197  gr_def(ctx, 0x40085c, 0x00000040);
198  gr_def(ctx, 0x400864, 0x80000000);
199  cp_ctx(ctx, 0x40086c, 9);
200  gr_def(ctx, 0x40086c, 0x80000000);
201  gr_def(ctx, 0x400870, 0x80000000);
202  gr_def(ctx, 0x400874, 0x80000000);
203  gr_def(ctx, 0x400878, 0x80000000);
204  gr_def(ctx, 0x400888, 0x00000040);
205  gr_def(ctx, 0x40088c, 0x80000000);
206  cp_ctx(ctx, 0x4009c0, 8);
207  gr_def(ctx, 0x4009cc, 0x80000000);
208  gr_def(ctx, 0x4009dc, 0x80000000);
209  } else {
210  cp_ctx(ctx, 0x400840, 20);
211  if (nv44_graph_class(ctx->device)) {
212  for (i = 0; i < 8; i++)
213  gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
214  }
215  gr_def(ctx, 0x400880, 0x00000040);
216  gr_def(ctx, 0x400884, 0x00000040);
217  gr_def(ctx, 0x400888, 0x00000040);
218  cp_ctx(ctx, 0x400894, 11);
219  gr_def(ctx, 0x400894, 0x00000040);
220  if (!nv44_graph_class(ctx->device)) {
221  for (i = 0; i < 8; i++)
222  gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
223  }
224  cp_ctx(ctx, 0x4008e0, 2);
225  cp_ctx(ctx, 0x4008f8, 2);
226  if (device->chipset == 0x4c ||
227  (device->chipset & 0xf0) == 0x60)
228  cp_ctx(ctx, 0x4009f8, 1);
229  }
230  cp_ctx(ctx, 0x400a00, 73);
231  gr_def(ctx, 0x400b0c, 0x0b0b0b0c);
232  cp_ctx(ctx, 0x401000, 4);
233  cp_ctx(ctx, 0x405004, 1);
234  switch (device->chipset) {
235  case 0x47:
236  case 0x49:
237  case 0x4b:
238  cp_ctx(ctx, 0x403448, 1);
239  gr_def(ctx, 0x403448, 0x00001010);
240  break;
241  default:
242  cp_ctx(ctx, 0x403440, 1);
243  switch (device->chipset) {
244  case 0x40:
245  gr_def(ctx, 0x403440, 0x00000010);
246  break;
247  case 0x44:
248  case 0x46:
249  case 0x4a:
250  gr_def(ctx, 0x403440, 0x00003010);
251  break;
252  case 0x41:
253  case 0x42:
254  case 0x43:
255  case 0x4c:
256  case 0x4e:
257  case 0x67:
258  default:
259  gr_def(ctx, 0x403440, 0x00001010);
260  break;
261  }
262  break;
263  }
264 }
265 
266 static void
267 nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
268 {
269  struct nouveau_device *device = ctx->device;
270  int i;
271 
272  if (device->chipset == 0x40) {
273  cp_ctx(ctx, 0x401880, 51);
274  gr_def(ctx, 0x401940, 0x00000100);
275  } else
276  if (device->chipset == 0x46 || device->chipset == 0x47 ||
277  device->chipset == 0x49 || device->chipset == 0x4b) {
278  cp_ctx(ctx, 0x401880, 32);
279  for (i = 0; i < 16; i++)
280  gr_def(ctx, 0x401880 + (i * 4), 0x00000111);
281  if (device->chipset == 0x46)
282  cp_ctx(ctx, 0x401900, 16);
283  cp_ctx(ctx, 0x401940, 3);
284  }
285  cp_ctx(ctx, 0x40194c, 18);
286  gr_def(ctx, 0x401954, 0x00000111);
287  gr_def(ctx, 0x401958, 0x00080060);
288  gr_def(ctx, 0x401974, 0x00000080);
289  gr_def(ctx, 0x401978, 0xffff0000);
290  gr_def(ctx, 0x40197c, 0x00000001);
291  gr_def(ctx, 0x401990, 0x46400000);
292  if (device->chipset == 0x40) {
293  cp_ctx(ctx, 0x4019a0, 2);
294  cp_ctx(ctx, 0x4019ac, 5);
295  } else {
296  cp_ctx(ctx, 0x4019a0, 1);
297  cp_ctx(ctx, 0x4019b4, 3);
298  }
299  gr_def(ctx, 0x4019bc, 0xffff0000);
300  switch (device->chipset) {
301  case 0x46:
302  case 0x47:
303  case 0x49:
304  case 0x4b:
305  cp_ctx(ctx, 0x4019c0, 18);
306  for (i = 0; i < 16; i++)
307  gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888);
308  break;
309  }
310  cp_ctx(ctx, 0x401a08, 8);
311  gr_def(ctx, 0x401a10, 0x0fff0000);
312  gr_def(ctx, 0x401a14, 0x0fff0000);
313  gr_def(ctx, 0x401a1c, 0x00011100);
314  cp_ctx(ctx, 0x401a2c, 4);
315  cp_ctx(ctx, 0x401a44, 26);
316  for (i = 0; i < 16; i++)
317  gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000);
318  gr_def(ctx, 0x401a8c, 0x4b7fffff);
319  if (device->chipset == 0x40) {
320  cp_ctx(ctx, 0x401ab8, 3);
321  } else {
322  cp_ctx(ctx, 0x401ab8, 1);
323  cp_ctx(ctx, 0x401ac0, 1);
324  }
325  cp_ctx(ctx, 0x401ad0, 8);
326  gr_def(ctx, 0x401ad0, 0x30201000);
327  gr_def(ctx, 0x401ad4, 0x70605040);
328  gr_def(ctx, 0x401ad8, 0xb8a89888);
329  gr_def(ctx, 0x401adc, 0xf8e8d8c8);
330  cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1);
331  gr_def(ctx, 0x401b10, 0x40100000);
332  cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5);
333  gr_def(ctx, 0x401b28, device->chipset == 0x40 ?
334  0x00000004 : 0x00000000);
335  cp_ctx(ctx, 0x401b30, 25);
336  gr_def(ctx, 0x401b34, 0x0000ffff);
337  gr_def(ctx, 0x401b68, 0x435185d6);
338  gr_def(ctx, 0x401b6c, 0x2155b699);
339  gr_def(ctx, 0x401b70, 0xfedcba98);
340  gr_def(ctx, 0x401b74, 0x00000098);
341  gr_def(ctx, 0x401b84, 0xffffffff);
342  gr_def(ctx, 0x401b88, 0x00ff7000);
343  gr_def(ctx, 0x401b8c, 0x0000ffff);
344  if (device->chipset != 0x44 && device->chipset != 0x4a &&
345  device->chipset != 0x4e)
346  cp_ctx(ctx, 0x401b94, 1);
347  cp_ctx(ctx, 0x401b98, 8);
348  gr_def(ctx, 0x401b9c, 0x00ff0000);
349  cp_ctx(ctx, 0x401bc0, 9);
350  gr_def(ctx, 0x401be0, 0x00ffff00);
351  cp_ctx(ctx, 0x401c00, 192);
352  for (i = 0; i < 16; i++) { /* fragment texture units */
353  gr_def(ctx, 0x401c40 + (i * 4), 0x00018488);
354  gr_def(ctx, 0x401c80 + (i * 4), 0x00028202);
355  gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4);
356  gr_def(ctx, 0x401d40 + (i * 4), 0x01012000);
357  gr_def(ctx, 0x401d80 + (i * 4), 0x00080008);
358  gr_def(ctx, 0x401e00 + (i * 4), 0x00100008);
359  }
360  for (i = 0; i < 4; i++) { /* vertex texture units */
361  gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80);
362  gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202);
363  gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008);
364  gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008);
365  }
366  cp_ctx(ctx, 0x400f5c, 3);
367  gr_def(ctx, 0x400f5c, 0x00000002);
368  cp_ctx(ctx, 0x400f84, 1);
369 }
370 
371 static void
372 nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
373 {
374  struct nouveau_device *device = ctx->device;
375  int i;
376 
377  cp_ctx(ctx, 0x402000, 1);
378  cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2);
379  switch (device->chipset) {
380  case 0x40:
381  gr_def(ctx, 0x402404, 0x00000001);
382  break;
383  case 0x4c:
384  case 0x4e:
385  case 0x67:
386  gr_def(ctx, 0x402404, 0x00000020);
387  break;
388  case 0x46:
389  case 0x49:
390  case 0x4b:
391  gr_def(ctx, 0x402404, 0x00000421);
392  break;
393  default:
394  gr_def(ctx, 0x402404, 0x00000021);
395  }
396  if (device->chipset != 0x40)
397  gr_def(ctx, 0x402408, 0x030c30c3);
398  switch (device->chipset) {
399  case 0x44:
400  case 0x46:
401  case 0x4a:
402  case 0x4c:
403  case 0x4e:
404  case 0x67:
405  cp_ctx(ctx, 0x402440, 1);
406  gr_def(ctx, 0x402440, 0x00011001);
407  break;
408  default:
409  break;
410  }
411  cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9);
412  gr_def(ctx, 0x402488, 0x3e020200);
413  gr_def(ctx, 0x40248c, 0x00ffffff);
414  switch (device->chipset) {
415  case 0x40:
416  gr_def(ctx, 0x402490, 0x60103f00);
417  break;
418  case 0x47:
419  gr_def(ctx, 0x402490, 0x40103f00);
420  break;
421  case 0x41:
422  case 0x42:
423  case 0x49:
424  case 0x4b:
425  gr_def(ctx, 0x402490, 0x20103f00);
426  break;
427  default:
428  gr_def(ctx, 0x402490, 0x0c103f00);
429  break;
430  }
431  gr_def(ctx, 0x40249c, device->chipset <= 0x43 ?
432  0x00020000 : 0x00040000);
433  cp_ctx(ctx, 0x402500, 31);
434  gr_def(ctx, 0x402530, 0x00008100);
435  if (device->chipset == 0x40)
436  cp_ctx(ctx, 0x40257c, 6);
437  cp_ctx(ctx, 0x402594, 16);
438  cp_ctx(ctx, 0x402800, 17);
439  gr_def(ctx, 0x402800, 0x00000001);
440  switch (device->chipset) {
441  case 0x47:
442  case 0x49:
443  case 0x4b:
444  cp_ctx(ctx, 0x402864, 1);
445  gr_def(ctx, 0x402864, 0x00001001);
446  cp_ctx(ctx, 0x402870, 3);
447  gr_def(ctx, 0x402878, 0x00000003);
448  if (device->chipset != 0x47) { /* belong at end!! */
449  cp_ctx(ctx, 0x402900, 1);
450  cp_ctx(ctx, 0x402940, 1);
451  cp_ctx(ctx, 0x402980, 1);
452  cp_ctx(ctx, 0x4029c0, 1);
453  cp_ctx(ctx, 0x402a00, 1);
454  cp_ctx(ctx, 0x402a40, 1);
455  cp_ctx(ctx, 0x402a80, 1);
456  cp_ctx(ctx, 0x402ac0, 1);
457  }
458  break;
459  case 0x40:
460  cp_ctx(ctx, 0x402844, 1);
461  gr_def(ctx, 0x402844, 0x00000001);
462  cp_ctx(ctx, 0x402850, 1);
463  break;
464  default:
465  cp_ctx(ctx, 0x402844, 1);
466  gr_def(ctx, 0x402844, 0x00001001);
467  cp_ctx(ctx, 0x402850, 2);
468  gr_def(ctx, 0x402854, 0x00000003);
469  break;
470  }
471 
472  cp_ctx(ctx, 0x402c00, 4);
473  gr_def(ctx, 0x402c00, device->chipset == 0x40 ?
474  0x80800001 : 0x00888001);
475  switch (device->chipset) {
476  case 0x47:
477  case 0x49:
478  case 0x4b:
479  cp_ctx(ctx, 0x402c20, 40);
480  for (i = 0; i < 32; i++)
481  gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff);
482  cp_ctx(ctx, 0x4030b8, 13);
483  gr_def(ctx, 0x4030dc, 0x00000005);
484  gr_def(ctx, 0x4030e8, 0x0000ffff);
485  break;
486  default:
487  cp_ctx(ctx, 0x402c10, 4);
488  if (device->chipset == 0x40)
489  cp_ctx(ctx, 0x402c20, 36);
490  else
491  if (device->chipset <= 0x42)
492  cp_ctx(ctx, 0x402c20, 24);
493  else
494  if (device->chipset <= 0x4a)
495  cp_ctx(ctx, 0x402c20, 16);
496  else
497  cp_ctx(ctx, 0x402c20, 8);
498  cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13);
499  gr_def(ctx, 0x402cd4, 0x00000005);
500  if (device->chipset != 0x40)
501  gr_def(ctx, 0x402ce0, 0x0000ffff);
502  break;
503  }
504 
505  cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3);
506  cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3);
507  cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device));
508  for (i = 0; i < nv40_graph_vs_count(ctx->device); i++)
509  gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
510 
511  if (device->chipset != 0x40) {
512  cp_ctx(ctx, 0x403600, 1);
513  gr_def(ctx, 0x403600, 0x00000001);
514  }
515  cp_ctx(ctx, 0x403800, 1);
516 
517  cp_ctx(ctx, 0x403c18, 1);
518  gr_def(ctx, 0x403c18, 0x00000001);
519  switch (device->chipset) {
520  case 0x46:
521  case 0x47:
522  case 0x49:
523  case 0x4b:
524  cp_ctx(ctx, 0x405018, 1);
525  gr_def(ctx, 0x405018, 0x08e00001);
526  cp_ctx(ctx, 0x405c24, 1);
527  gr_def(ctx, 0x405c24, 0x000e3000);
528  break;
529  }
530  if (device->chipset != 0x4e)
531  cp_ctx(ctx, 0x405800, 11);
532  cp_ctx(ctx, 0x407000, 1);
533 }
534 
535 static void
536 nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
537 {
538  int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684;
539 
540  cp_out (ctx, 0x300000);
541  cp_lsr (ctx, len - 4);
542  cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save);
543  cp_lsr (ctx, len);
544  cp_name(ctx, cp_swap_state3d_3_is_save);
545  cp_out (ctx, 0x800001);
546 
547  ctx->ctxvals_pos += len;
548 }
549 
550 static void
551 nv40_graph_construct_shader(struct nouveau_grctx *ctx)
552 {
553  struct nouveau_device *device = ctx->device;
554  struct nouveau_gpuobj *obj = ctx->data;
555  int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
556  int offset, i;
557 
558  vs_nr = nv40_graph_vs_count(ctx->device);
559  vs_nr_b0 = 363;
560  vs_nr_b1 = device->chipset == 0x40 ? 128 : 64;
561  if (device->chipset == 0x40) {
562  b0_offset = 0x2200/4; /* 33a0 */
563  b1_offset = 0x55a0/4; /* 1500 */
564  vs_len = 0x6aa0/4;
565  } else
566  if (device->chipset == 0x41 || device->chipset == 0x42) {
567  b0_offset = 0x2200/4; /* 2200 */
568  b1_offset = 0x4400/4; /* 0b00 */
569  vs_len = 0x4f00/4;
570  } else {
571  b0_offset = 0x1d40/4; /* 2200 */
572  b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
573  vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4;
574  }
575 
576  cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
577  cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041);
578 
579  offset = ctx->ctxvals_pos;
580  ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
581 
582  if (ctx->mode != NOUVEAU_GRCTX_VALS)
583  return;
584 
585  offset += 0x0280/4;
586  for (i = 0; i < 16; i++, offset += 2)
587  nv_wo32(obj, offset * 4, 0x3f800000);
588 
589  for (vs = 0; vs < vs_nr; vs++, offset += vs_len) {
590  for (i = 0; i < vs_nr_b0 * 6; i += 6)
591  nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001);
592  for (i = 0; i < vs_nr_b1 * 4; i += 4)
593  nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000);
594  }
595 }
596 
597 static void
598 nv40_grctx_generate(struct nouveau_grctx *ctx)
599 {
600  /* decide whether we're loading/unloading the context */
601  cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
602  cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
603 
604  cp_name(ctx, cp_check_load);
605  cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
606  cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
607  cp_bra (ctx, ALWAYS, TRUE, cp_exit);
608 
609  /* setup for context load */
610  cp_name(ctx, cp_setup_auto_load);
611  cp_wait(ctx, STATUS, IDLE);
612  cp_out (ctx, CP_NEXT_TO_SWAP);
613  cp_name(ctx, cp_setup_load);
614  cp_wait(ctx, STATUS, IDLE);
615  cp_set (ctx, SWAP_DIRECTION, LOAD);
616  cp_out (ctx, 0x00910880); /* ?? */
617  cp_out (ctx, 0x00901ffe); /* ?? */
618  cp_out (ctx, 0x01940000); /* ?? */
619  cp_lsr (ctx, 0x20);
620  cp_out (ctx, 0x0060000b); /* ?? */
621  cp_wait(ctx, UNK57, CLEAR);
622  cp_out (ctx, 0x0060000c); /* ?? */
623  cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
624 
625  /* setup for context save */
626  cp_name(ctx, cp_setup_save);
627  cp_set (ctx, SWAP_DIRECTION, SAVE);
628 
629  /* general PGRAPH state */
630  cp_name(ctx, cp_swap_state);
631  cp_pos (ctx, 0x00020/4);
632  nv40_graph_construct_general(ctx);
633  cp_wait(ctx, STATUS, IDLE);
634 
635  /* 3D state, block 1 */
636  cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
637  nv40_graph_construct_state3d(ctx);
638  cp_wait(ctx, STATUS, IDLE);
639 
640  /* 3D state, block 2 */
641  nv40_graph_construct_state3d_2(ctx);
642 
643  /* Some other block of "random" state */
644  nv40_graph_construct_state3d_3(ctx);
645 
646  /* Per-vertex shader state */
647  cp_pos (ctx, ctx->ctxvals_pos);
648  nv40_graph_construct_shader(ctx);
649 
650  /* pre-exit state updates */
651  cp_name(ctx, cp_prepare_exit);
652  cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
653  cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
654  cp_out (ctx, CP_NEXT_TO_CURRENT);
655 
656  cp_name(ctx, cp_exit);
657  cp_set (ctx, USER_SAVE, NOT_PENDING);
658  cp_set (ctx, USER_LOAD, NOT_PENDING);
659  cp_out (ctx, CP_END);
660 }
661 
662 void
663 nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
664 {
665  nv40_grctx_generate(&(struct nouveau_grctx) {
666  .device = device,
667  .mode = NOUVEAU_GRCTX_VALS,
668  .data = mem,
669  });
670 }
671 
672 int
673 nv40_grctx_init(struct nouveau_device *device, u32 *size)
674 {
675  u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
676  struct nouveau_grctx ctx = {
677  .device = device,
678  .mode = NOUVEAU_GRCTX_PROG,
679  .data = ctxprog,
680  .ctxprog_max = 256,
681  };
682 
683  if (!ctxprog)
684  return -ENOMEM;
685 
686  nv40_grctx_generate(&ctx);
687 
688  nv_wr32(device, 0x400324, 0);
689  for (i = 0; i < ctx.ctxprog_len; i++)
690  nv_wr32(device, 0x400328, ctxprog[i]);
691  *size = ctx.ctxvals_pos * 4;
692 
693  kfree(ctxprog);
694  return 0;
695 }
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