#include <mach/hardware.h>

Macros
#define	DC21285_PCI_IACK 0x79000000

#define	DC21285_ARMCSR_BASE 0x42000000

#define	DC21285_PCI_TYPE_0_CONFIG 0x7b000000

#define	DC21285_PCI_TYPE_1_CONFIG 0x7a000000

#define	DC21285_OUTBOUND_WRITE_FLUSH 0x78000000

#define	DC21285_FLASH 0x41000000

#define	DC21285_PCI_IO 0x7c000000

#define	DC21285_PCI_MEM 0x80000000

#define	DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x)))

#define	CSR_PCICMD DC21285_IO(0x0004)

#define	CSR_CLASSREV DC21285_IO(0x0008)

#define	CSR_PCICACHELINESIZE DC21285_IO(0x000c)

#define	CSR_PCICSRBASE DC21285_IO(0x0010)

#define	CSR_PCICSRIOBASE DC21285_IO(0x0014)

#define	CSR_PCISDRAMBASE DC21285_IO(0x0018)

#define	CSR_PCIROMBASE DC21285_IO(0x0030)

#define	CSR_MBOX0 DC21285_IO(0x0050)

#define	CSR_MBOX1 DC21285_IO(0x0054)

#define	CSR_MBOX2 DC21285_IO(0x0058)

#define	CSR_MBOX3 DC21285_IO(0x005c)

#define	CSR_DOORBELL DC21285_IO(0x0060)

#define	CSR_DOORBELL_SETUP DC21285_IO(0x0064)

#define	CSR_ROMWRITEREG DC21285_IO(0x0068)

#define	CSR_CSRBASEMASK DC21285_IO(0x00f8)

#define	CSR_CSRBASEOFFSET DC21285_IO(0x00fc)

#define	CSR_SDRAMBASEMASK DC21285_IO(0x0100)

#define	CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)

#define	CSR_ROMBASEMASK DC21285_IO(0x0108)

#define	CSR_SDRAMTIMING DC21285_IO(0x010c)

#define	CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)

#define	CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)

#define	CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)

#define	CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)

#define	CSR_I2O_INFREEHEAD DC21285_IO(0x0120)

#define	CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)

#define	CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)

#define	CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)

#define	CSR_I2O_INFREECOUNT DC21285_IO(0x0130)

#define	CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)

#define	CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)

#define	CSR_SA110_CNTL DC21285_IO(0x013c)

#define	SA110_CNTL_INITCMPLETE (1 << 0)

#define	SA110_CNTL_ASSERTSERR (1 << 1)

#define	SA110_CNTL_RXSERR (1 << 3)

#define	SA110_CNTL_SA110DRAMPARITY (1 << 4)

#define	SA110_CNTL_PCISDRAMPARITY (1 << 5)

#define	SA110_CNTL_DMASDRAMPARITY (1 << 6)

#define	SA110_CNTL_DISCARDTIMER (1 << 8)

#define	SA110_CNTL_PCINRESET (1 << 9)

#define	SA110_CNTL_I2O_256 (0 << 10)

#define	SA110_CNTL_I20_512 (1 << 10)

#define	SA110_CNTL_I2O_1024 (2 << 10)

#define	SA110_CNTL_I2O_2048 (3 << 10)

#define	SA110_CNTL_I2O_4096 (4 << 10)

#define	SA110_CNTL_I2O_8192 (5 << 10)

#define	SA110_CNTL_I2O_16384 (6 << 10)

#define	SA110_CNTL_I2O_32768 (7 << 10)

#define	SA110_CNTL_WATCHDOG (1 << 13)

#define	SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)

#define	SA110_CNTL_ROMWIDTH_16 (1 << 14)

#define	SA110_CNTL_ROMWIDTH_32 (2 << 14)

#define	SA110_CNTL_ROMWIDTH_8 (3 << 14)

#define	SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)

#define	SA110_CNTL_ROMBURSTTIME(x) ((x)<<20)

#define	SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24)

#define	SA110_CNTL_XCSDIR(x) ((x)<<28)

#define	SA110_CNTL_PCICFN (1 << 31)

#define	__footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)

#define	footbridge_cfn_mode() (0)

#define	CSR_PCIADDR_EXTN DC21285_IO(0x0140)

#define	CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)

#define	CSR_XBUS_CYCLE DC21285_IO(0x0148)

#define	CSR_XBUS_IOSTROBE DC21285_IO(0x014c)

#define	CSR_DOORBELL_PCI DC21285_IO(0x0150)

#define	CSR_DOORBELL_SA110 DC21285_IO(0x0154)

#define	CSR_UARTDR DC21285_IO(0x0160)

#define	CSR_RXSTAT DC21285_IO(0x0164)

#define	CSR_H_UBRLCR DC21285_IO(0x0168)

#define	CSR_M_UBRLCR DC21285_IO(0x016c)

#define	CSR_L_UBRLCR DC21285_IO(0x0170)

#define	CSR_UARTCON DC21285_IO(0x0174)

#define	CSR_UARTFLG DC21285_IO(0x0178)

#define	CSR_IRQ_STATUS DC21285_IO(0x0180)

#define	CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)

#define	CSR_IRQ_ENABLE DC21285_IO(0x0188)

#define	CSR_IRQ_DISABLE DC21285_IO(0x018c)

#define	CSR_IRQ_SOFT DC21285_IO(0x0190)

#define	CSR_FIQ_STATUS DC21285_IO(0x0280)

#define	CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)

#define	CSR_FIQ_ENABLE DC21285_IO(0x0288)

#define	CSR_FIQ_DISABLE DC21285_IO(0x028c)

#define	CSR_FIQ_SOFT DC21285_IO(0x0290)

#define	CSR_TIMER1_LOAD DC21285_IO(0x0300)

#define	CSR_TIMER1_VALUE DC21285_IO(0x0304)

#define	CSR_TIMER1_CNTL DC21285_IO(0x0308)

#define	CSR_TIMER1_CLR DC21285_IO(0x030c)

#define	CSR_TIMER2_LOAD DC21285_IO(0x0320)

#define	CSR_TIMER2_VALUE DC21285_IO(0x0324)

#define	CSR_TIMER2_CNTL DC21285_IO(0x0328)

#define	CSR_TIMER2_CLR DC21285_IO(0x032c)

#define	CSR_TIMER3_LOAD DC21285_IO(0x0340)

#define	CSR_TIMER3_VALUE DC21285_IO(0x0344)

#define	CSR_TIMER3_CNTL DC21285_IO(0x0348)

#define	CSR_TIMER3_CLR DC21285_IO(0x034c)

#define	CSR_TIMER4_LOAD DC21285_IO(0x0360)

#define	CSR_TIMER4_VALUE DC21285_IO(0x0364)

#define	CSR_TIMER4_CNTL DC21285_IO(0x0368)

#define	CSR_TIMER4_CLR DC21285_IO(0x036c)

#define	TIMER_CNTL_ENABLE (1 << 7)

#define	TIMER_CNTL_AUTORELOAD (1 << 6)

#define	TIMER_CNTL_DIV1 (0)

#define	TIMER_CNTL_DIV16 (1 << 2)

#define	TIMER_CNTL_DIV256 (2 << 2)

#define	TIMER_CNTL_CNTEXT (3 << 2)

Macro Definition Documentation

#define __footbridge_cfn_mode ( ) (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)

Definition at line 91 of file dec21285.h.

#define CSR_CLASSREV DC21285_IO(0x0008)

Definition at line 29 of file dec21285.h.

#define CSR_CSRBASEMASK DC21285_IO(0x00f8)

Definition at line 42 of file dec21285.h.

#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)

Definition at line 43 of file dec21285.h.

#define CSR_DOORBELL DC21285_IO(0x0060)

Definition at line 39 of file dec21285.h.

#define CSR_DOORBELL_PCI DC21285_IO(0x0150)

Definition at line 104 of file dec21285.h.

#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)

Definition at line 105 of file dec21285.h.

#define CSR_DOORBELL_SETUP DC21285_IO(0x0064)

Definition at line 40 of file dec21285.h.

#define CSR_FIQ_DISABLE DC21285_IO(0x028c)

Definition at line 121 of file dec21285.h.

#define CSR_FIQ_ENABLE DC21285_IO(0x0288)

Definition at line 120 of file dec21285.h.

#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)

Definition at line 119 of file dec21285.h.

#define CSR_FIQ_SOFT DC21285_IO(0x0290)

Definition at line 122 of file dec21285.h.

#define CSR_FIQ_STATUS DC21285_IO(0x0280)

Definition at line 118 of file dec21285.h.

#define CSR_H_UBRLCR DC21285_IO(0x0168)

Definition at line 108 of file dec21285.h.

#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)

Definition at line 56 of file dec21285.h.

#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)

Definition at line 52 of file dec21285.h.

#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)

Definition at line 58 of file dec21285.h.

#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)

Definition at line 53 of file dec21285.h.

#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)

Definition at line 55 of file dec21285.h.

#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)

Definition at line 57 of file dec21285.h.

#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)

Definition at line 54 of file dec21285.h.

#define CSR_IRQ_DISABLE DC21285_IO(0x018c)

Definition at line 116 of file dec21285.h.

#define CSR_IRQ_ENABLE DC21285_IO(0x0188)

Definition at line 115 of file dec21285.h.

#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)

Definition at line 114 of file dec21285.h.

#define CSR_IRQ_SOFT DC21285_IO(0x0190)

Definition at line 117 of file dec21285.h.

#define CSR_IRQ_STATUS DC21285_IO(0x0180)

Definition at line 113 of file dec21285.h.

#define CSR_L_UBRLCR DC21285_IO(0x0170)

Definition at line 110 of file dec21285.h.

#define CSR_M_UBRLCR DC21285_IO(0x016c)

Definition at line 109 of file dec21285.h.

#define CSR_MBOX0 DC21285_IO(0x0050)

Definition at line 35 of file dec21285.h.

#define CSR_MBOX1 DC21285_IO(0x0054)

Definition at line 36 of file dec21285.h.

#define CSR_MBOX2 DC21285_IO(0x0058)

Definition at line 37 of file dec21285.h.

#define CSR_MBOX3 DC21285_IO(0x005c)

Definition at line 38 of file dec21285.h.

#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)

Definition at line 100 of file dec21285.h.

#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)

Definition at line 30 of file dec21285.h.

#define CSR_PCICMD DC21285_IO(0x0004)

Definition at line 28 of file dec21285.h.

#define CSR_PCICSRBASE DC21285_IO(0x0010)

Definition at line 31 of file dec21285.h.

#define CSR_PCICSRIOBASE DC21285_IO(0x0014)

Definition at line 32 of file dec21285.h.

#define CSR_PCIROMBASE DC21285_IO(0x0030)

Definition at line 34 of file dec21285.h.

#define CSR_PCISDRAMBASE DC21285_IO(0x0018)

Definition at line 33 of file dec21285.h.

#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)

Definition at line 101 of file dec21285.h.

#define CSR_ROMBASEMASK DC21285_IO(0x0108)

Definition at line 46 of file dec21285.h.

#define CSR_ROMWRITEREG DC21285_IO(0x0068)

Definition at line 41 of file dec21285.h.

#define CSR_RXSTAT DC21285_IO(0x0164)

Definition at line 107 of file dec21285.h.

#define CSR_SA110_CNTL DC21285_IO(0x013c)

Definition at line 59 of file dec21285.h.

#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)

Definition at line 48 of file dec21285.h.

#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)

Definition at line 49 of file dec21285.h.

#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)

Definition at line 50 of file dec21285.h.

#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)

Definition at line 51 of file dec21285.h.

#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)

Definition at line 44 of file dec21285.h.

#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)

Definition at line 45 of file dec21285.h.

#define CSR_SDRAMTIMING DC21285_IO(0x010c)

Definition at line 47 of file dec21285.h.

#define CSR_TIMER1_CLR DC21285_IO(0x030c)

Definition at line 126 of file dec21285.h.

#define CSR_TIMER1_CNTL DC21285_IO(0x0308)

Definition at line 125 of file dec21285.h.

#define CSR_TIMER1_LOAD DC21285_IO(0x0300)

Definition at line 123 of file dec21285.h.

#define CSR_TIMER1_VALUE DC21285_IO(0x0304)

Definition at line 124 of file dec21285.h.

#define CSR_TIMER2_CLR DC21285_IO(0x032c)

Definition at line 130 of file dec21285.h.

#define CSR_TIMER2_CNTL DC21285_IO(0x0328)

Definition at line 129 of file dec21285.h.

#define CSR_TIMER2_LOAD DC21285_IO(0x0320)

Definition at line 127 of file dec21285.h.

#define CSR_TIMER2_VALUE DC21285_IO(0x0324)

Definition at line 128 of file dec21285.h.

#define CSR_TIMER3_CLR DC21285_IO(0x034c)

Definition at line 134 of file dec21285.h.

#define CSR_TIMER3_CNTL DC21285_IO(0x0348)

Definition at line 133 of file dec21285.h.

#define CSR_TIMER3_LOAD DC21285_IO(0x0340)

Definition at line 131 of file dec21285.h.

#define CSR_TIMER3_VALUE DC21285_IO(0x0344)

Definition at line 132 of file dec21285.h.

#define CSR_TIMER4_CLR DC21285_IO(0x036c)

Definition at line 138 of file dec21285.h.

#define CSR_TIMER4_CNTL DC21285_IO(0x0368)

Definition at line 137 of file dec21285.h.

#define CSR_TIMER4_LOAD DC21285_IO(0x0360)

Definition at line 135 of file dec21285.h.

#define CSR_TIMER4_VALUE DC21285_IO(0x0364)

Definition at line 136 of file dec21285.h.

#define CSR_UARTCON DC21285_IO(0x0174)

Definition at line 111 of file dec21285.h.

#define CSR_UARTDR DC21285_IO(0x0160)

Definition at line 106 of file dec21285.h.

#define CSR_UARTFLG DC21285_IO(0x0178)

Definition at line 112 of file dec21285.h.

#define CSR_XBUS_CYCLE DC21285_IO(0x0148)

Definition at line 102 of file dec21285.h.

#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)

Definition at line 103 of file dec21285.h.

#define DC21285_ARMCSR_BASE 0x42000000

Definition at line 13 of file dec21285.h.

#define DC21285_FLASH 0x41000000

Definition at line 17 of file dec21285.h.

#define DC21285_IO ( x ) ((volatile unsigned long *)(ARMCSR_BASE+(x)))

Definition at line 23 of file dec21285.h.

#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000

Definition at line 16 of file dec21285.h.

#define DC21285_PCI_IACK 0x79000000

Definition at line 12 of file dec21285.h.

#define DC21285_PCI_IO 0x7c000000

Definition at line 18 of file dec21285.h.

#define DC21285_PCI_MEM 0x80000000

Definition at line 19 of file dec21285.h.

#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000

Definition at line 14 of file dec21285.h.

#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000

Definition at line 15 of file dec21285.h.

#define footbridge_cfn_mode ( ) (0)

Definition at line 97 of file dec21285.h.

#define SA110_CNTL_ASSERTSERR (1 << 1)

Definition at line 61 of file dec21285.h.

#define SA110_CNTL_DISCARDTIMER (1 << 8)

Definition at line 66 of file dec21285.h.

#define SA110_CNTL_DMASDRAMPARITY (1 << 6)

Definition at line 65 of file dec21285.h.

#define SA110_CNTL_I20_512 (1 << 10)

Definition at line 69 of file dec21285.h.

#define SA110_CNTL_I2O_1024 (2 << 10)

Definition at line 70 of file dec21285.h.

#define SA110_CNTL_I2O_16384 (6 << 10)

Definition at line 74 of file dec21285.h.

#define SA110_CNTL_I2O_2048 (3 << 10)

Definition at line 71 of file dec21285.h.

#define SA110_CNTL_I2O_256 (0 << 10)

Definition at line 68 of file dec21285.h.

#define SA110_CNTL_I2O_32768 (7 << 10)

Definition at line 75 of file dec21285.h.

#define SA110_CNTL_I2O_4096 (4 << 10)

Definition at line 72 of file dec21285.h.

#define SA110_CNTL_I2O_8192 (5 << 10)

Definition at line 73 of file dec21285.h.

#define SA110_CNTL_INITCMPLETE (1 << 0)

Definition at line 60 of file dec21285.h.

#define SA110_CNTL_PCICFN (1 << 31)

Definition at line 85 of file dec21285.h.

#define SA110_CNTL_PCINRESET (1 << 9)

Definition at line 67 of file dec21285.h.

#define SA110_CNTL_PCISDRAMPARITY (1 << 5)

Definition at line 64 of file dec21285.h.

#define SA110_CNTL_ROMACCESSTIME ( x ) ((x)<<16)

Definition at line 81 of file dec21285.h.

#define SA110_CNTL_ROMBURSTTIME ( x ) ((x)<<20)

Definition at line 82 of file dec21285.h.

#define SA110_CNTL_ROMTRISTATETIME ( x ) ((x)<<24)

Definition at line 83 of file dec21285.h.

#define SA110_CNTL_ROMWIDTH_16 (1 << 14)

Definition at line 78 of file dec21285.h.

#define SA110_CNTL_ROMWIDTH_32 (2 << 14)

Definition at line 79 of file dec21285.h.

#define SA110_CNTL_ROMWIDTH_8 (3 << 14)

Definition at line 80 of file dec21285.h.

#define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)

Definition at line 77 of file dec21285.h.

#define SA110_CNTL_RXSERR (1 << 3)

Definition at line 62 of file dec21285.h.

#define SA110_CNTL_SA110DRAMPARITY (1 << 4)

Definition at line 63 of file dec21285.h.

#define SA110_CNTL_WATCHDOG (1 << 13)

Definition at line 76 of file dec21285.h.

#define SA110_CNTL_XCSDIR ( x ) ((x)<<28)

Definition at line 84 of file dec21285.h.

#define TIMER_CNTL_AUTORELOAD (1 << 6)

Definition at line 141 of file dec21285.h.

#define TIMER_CNTL_CNTEXT (3 << 2)

Definition at line 145 of file dec21285.h.

#define TIMER_CNTL_DIV1 (0)

Definition at line 142 of file dec21285.h.

#define TIMER_CNTL_DIV16 (1 << 2)

Definition at line 143 of file dec21285.h.

#define TIMER_CNTL_DIV256 (2 << 2)

Definition at line 144 of file dec21285.h.

#define TIMER_CNTL_ENABLE (1 << 7)

Definition at line 140 of file dec21285.h.

Macros

Macro Definition Documentation