Linux Kernel  3.7.1
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dis.c
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1 /*
2  * Disassemble s390 instructions.
3  *
4  * Copyright IBM Corp. 2007
5  * Author(s): Martin Schwidefsky ([email protected]),
6  */
7 
8 #include <linux/sched.h>
9 #include <linux/kernel.h>
10 #include <linux/string.h>
11 #include <linux/errno.h>
12 #include <linux/ptrace.h>
13 #include <linux/timer.h>
14 #include <linux/mm.h>
15 #include <linux/smp.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
21 #include <linux/reboot.h>
22 #include <linux/kprobes.h>
23 #include <linux/kdebug.h>
24 
25 #include <asm/uaccess.h>
26 #include <asm/io.h>
27 #include <linux/atomic.h>
28 #include <asm/mathemu.h>
29 #include <asm/cpcmd.h>
30 #include <asm/lowcore.h>
31 #include <asm/debug.h>
32 #include <asm/irq.h>
33 
34 #ifndef CONFIG_64BIT
35 #define ONELONG "%08lx: "
36 #else /* CONFIG_64BIT */
37 #define ONELONG "%016lx: "
38 #endif /* CONFIG_64BIT */
39 
40 #define OPERAND_GPR 0x1 /* Operand printed as %rx */
41 #define OPERAND_FPR 0x2 /* Operand printed as %fx */
42 #define OPERAND_AR 0x4 /* Operand printed as %ax */
43 #define OPERAND_CR 0x8 /* Operand printed as %cx */
44 #define OPERAND_DISP 0x10 /* Operand printed as displacement */
45 #define OPERAND_BASE 0x20 /* Operand printed as base register */
46 #define OPERAND_INDEX 0x40 /* Operand printed as index register */
47 #define OPERAND_PCREL 0x80 /* Operand printed as pc-relative symbol */
48 #define OPERAND_SIGNED 0x100 /* Operand printed as signed value */
49 #define OPERAND_LENGTH 0x200 /* Operand printed as length (+1) */
50 
51 enum {
52  UNUSED, /* Indicates the end of the operand list */
53  R_8, /* GPR starting at position 8 */
54  R_12, /* GPR starting at position 12 */
55  R_16, /* GPR starting at position 16 */
56  R_20, /* GPR starting at position 20 */
57  R_24, /* GPR starting at position 24 */
58  R_28, /* GPR starting at position 28 */
59  R_32, /* GPR starting at position 32 */
60  F_8, /* FPR starting at position 8 */
61  F_12, /* FPR starting at position 12 */
62  F_16, /* FPR starting at position 16 */
63  F_20, /* FPR starting at position 16 */
64  F_24, /* FPR starting at position 24 */
65  F_28, /* FPR starting at position 28 */
66  F_32, /* FPR starting at position 32 */
67  A_8, /* Access reg. starting at position 8 */
68  A_12, /* Access reg. starting at position 12 */
69  A_24, /* Access reg. starting at position 24 */
70  A_28, /* Access reg. starting at position 28 */
71  C_8, /* Control reg. starting at position 8 */
72  C_12, /* Control reg. starting at position 12 */
73  B_16, /* Base register starting at position 16 */
74  B_32, /* Base register starting at position 32 */
75  X_12, /* Index register starting at position 12 */
76  D_20, /* Displacement starting at position 20 */
77  D_36, /* Displacement starting at position 36 */
78  D20_20, /* 20 bit displacement starting at 20 */
79  L4_8, /* 4 bit length starting at position 8 */
80  L4_12, /* 4 bit length starting at position 12 */
81  L8_8, /* 8 bit length starting at position 8 */
82  U4_8, /* 4 bit unsigned value starting at 8 */
83  U4_12, /* 4 bit unsigned value starting at 12 */
84  U4_16, /* 4 bit unsigned value starting at 16 */
85  U4_20, /* 4 bit unsigned value starting at 20 */
86  U4_32, /* 4 bit unsigned value starting at 32 */
87  U8_8, /* 8 bit unsigned value starting at 8 */
88  U8_16, /* 8 bit unsigned value starting at 16 */
89  U8_24, /* 8 bit unsigned value starting at 24 */
90  U8_32, /* 8 bit unsigned value starting at 32 */
91  I8_8, /* 8 bit signed value starting at 8 */
92  I8_32, /* 8 bit signed value starting at 32 */
93  I16_16, /* 16 bit signed value starting at 16 */
94  I16_32, /* 32 bit signed value starting at 16 */
95  U16_16, /* 16 bit unsigned value starting at 16 */
96  U16_32, /* 32 bit unsigned value starting at 16 */
97  J16_16, /* PC relative jump offset at 16 */
98  J32_16, /* PC relative long offset at 16 */
99  I32_16, /* 32 bit signed value starting at 16 */
100  U32_16, /* 32 bit unsigned value starting at 16 */
101  M_16, /* 4 bit optional mask starting at 16 */
102  RO_28, /* optional GPR starting at position 28 */
103 };
104 
105 /*
106  * Enumeration of the different instruction formats.
107  * For details consult the principles of operation.
108  */
109 enum {
110  INSTR_INVALID,
111  INSTR_E,
112  INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU,
113  INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0,
114  INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP,
115  INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU,
116  INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP,
117  INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0,
118  INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF,
119  INSTR_RRE_RR, INSTR_RRE_RR_OPT,
120  INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
121  INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_M0RR, INSTR_RRF_R0RR,
122  INSTR_RRF_R0RR2, INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF,
123  INSTR_RRF_U0RR, INSTR_RRF_UUFF, INSTR_RRR_F0FF, INSTR_RRS_RRRDU,
124  INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR,
125  INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD,
126  INSTR_RSI_RRP,
127  INSTR_RSL_R0RD,
128  INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD,
129  INSTR_RSY_RDRM,
130  INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD,
131  INSTR_RS_RURD,
132  INSTR_RXE_FRRD, INSTR_RXE_RRRD,
133  INSTR_RXF_FRRDF,
134  INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD,
135  INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD,
136  INSTR_SIL_RDI, INSTR_SIL_RDU,
137  INSTR_SIY_IRD, INSTR_SIY_URD,
138  INSTR_SI_URD,
139  INSTR_SSE_RDRD,
140  INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2,
141  INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD,
142  INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3,
143  INSTR_S_00, INSTR_S_RD,
144 };
145 
146 struct operand {
147  int bits; /* The number of bits in the operand. */
148  int shift; /* The number of bits to shift. */
149  int flags; /* One bit syntax flags. */
150 };
151 
152 struct insn {
153  const char name[5];
154  unsigned char opfrag;
155  unsigned char format;
156 };
157 
158 static const struct operand operands[] =
159 {
160  [UNUSED] = { 0, 0, 0 },
161  [R_8] = { 4, 8, OPERAND_GPR },
162  [R_12] = { 4, 12, OPERAND_GPR },
163  [R_16] = { 4, 16, OPERAND_GPR },
164  [R_20] = { 4, 20, OPERAND_GPR },
165  [R_24] = { 4, 24, OPERAND_GPR },
166  [R_28] = { 4, 28, OPERAND_GPR },
167  [R_32] = { 4, 32, OPERAND_GPR },
168  [F_8] = { 4, 8, OPERAND_FPR },
169  [F_12] = { 4, 12, OPERAND_FPR },
170  [F_16] = { 4, 16, OPERAND_FPR },
171  [F_20] = { 4, 16, OPERAND_FPR },
172  [F_24] = { 4, 24, OPERAND_FPR },
173  [F_28] = { 4, 28, OPERAND_FPR },
174  [F_32] = { 4, 32, OPERAND_FPR },
175  [A_8] = { 4, 8, OPERAND_AR },
176  [A_12] = { 4, 12, OPERAND_AR },
177  [A_24] = { 4, 24, OPERAND_AR },
178  [A_28] = { 4, 28, OPERAND_AR },
179  [C_8] = { 4, 8, OPERAND_CR },
180  [C_12] = { 4, 12, OPERAND_CR },
181  [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR },
182  [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR },
183  [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR },
184  [D_20] = { 12, 20, OPERAND_DISP },
185  [D_36] = { 12, 36, OPERAND_DISP },
186  [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED },
187  [L4_8] = { 4, 8, OPERAND_LENGTH },
188  [L4_12] = { 4, 12, OPERAND_LENGTH },
189  [L8_8] = { 8, 8, OPERAND_LENGTH },
190  [U4_8] = { 4, 8, 0 },
191  [U4_12] = { 4, 12, 0 },
192  [U4_16] = { 4, 16, 0 },
193  [U4_20] = { 4, 20, 0 },
194  [U4_32] = { 4, 32, 0 },
195  [U8_8] = { 8, 8, 0 },
196  [U8_16] = { 8, 16, 0 },
197  [U8_24] = { 8, 24, 0 },
198  [U8_32] = { 8, 32, 0 },
199  [I16_16] = { 16, 16, OPERAND_SIGNED },
200  [U16_16] = { 16, 16, 0 },
201  [U16_32] = { 16, 32, 0 },
202  [J16_16] = { 16, 16, OPERAND_PCREL },
203  [I16_32] = { 16, 32, OPERAND_SIGNED },
204  [J32_16] = { 32, 16, OPERAND_PCREL },
205  [I32_16] = { 32, 16, OPERAND_SIGNED },
206  [U32_16] = { 32, 16, 0 },
207  [M_16] = { 4, 16, 0 },
208  [RO_28] = { 4, 28, OPERAND_GPR }
209 };
210 
211 static const unsigned char formats[][7] = {
212  [INSTR_E] = { 0xff, 0,0,0,0,0,0 },
213  [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 },
214  [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 },
215  [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 },
216  [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 },
217  [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 },
218  [INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 },
219  [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 },
220  [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 },
221  [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 },
222  [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 },
223  [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 },
224  [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 },
225  [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 },
226  [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 },
227  [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 },
228  [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 },
229  [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 },
230  [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 },
231  [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 },
232  [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 },
233  [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 },
234  [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 },
235  [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 },
236  [INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 },
237  [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 },
238  [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 },
239  [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 },
240  [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 },
241  [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 },
242  [INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 },
243  [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 },
244  [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 },
245  [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 },
246  [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 },
247  [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 },
248  [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 },
249  [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 },
250  [INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 },
251  [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 },
252  [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 },
253  [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 },
254  [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 },
255  [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 },
256  [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 },
257  [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 },
258  [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 },
259  [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 },
260  [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 },
261  [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 },
262  [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 },
263  [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 },
264  [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 },
265  [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 },
266  [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 },
267  [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 },
268  [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 },
269  [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 },
270  [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 },
271  [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 },
272  [INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 },
273  [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 },
274  [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 },
275  [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 },
276  [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 },
277  [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 },
278  [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 },
279  [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 },
280  [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 },
281  [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 },
282  [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 },
283  [INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 },
284  [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 },
285  [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 },
286  [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 },
287  [INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 },
288  [INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 },
289  [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 },
290  [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 },
291  [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 },
292  [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 },
293  [INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 },
294  [INSTR_SSF_RRDRD2]= { 0x00, R_8,D_20,B_16,D_36,B_32,0 },
295  [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 },
296  [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 },
297  [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 },
298  [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 },
299  [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 },
300  [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 },
301  [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 },
302  [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 },
303 };
304 
305 enum {
306  LONG_INSN_ALGHSIK,
307  LONG_INSN_ALHSIK,
308  LONG_INSN_CLFHSI,
309  LONG_INSN_CLGFRL,
310  LONG_INSN_CLGHRL,
311  LONG_INSN_CLGHSI,
312  LONG_INSN_CLHHSI,
313  LONG_INSN_LLGFRL,
314  LONG_INSN_LLGHRL,
315  LONG_INSN_POPCNT,
316  LONG_INSN_RISBHG,
317  LONG_INSN_RISBLG,
318  LONG_INSN_RINEXT,
319  LONG_INSN_RIEMIT,
320  LONG_INSN_TABORT,
321  LONG_INSN_TBEGIN,
322  LONG_INSN_TBEGINC,
323 };
324 
325 static char *long_insn_name[] = {
326  [LONG_INSN_ALGHSIK] = "alghsik",
327  [LONG_INSN_ALHSIK] = "alhsik",
328  [LONG_INSN_CLFHSI] = "clfhsi",
329  [LONG_INSN_CLGFRL] = "clgfrl",
330  [LONG_INSN_CLGHRL] = "clghrl",
331  [LONG_INSN_CLGHSI] = "clghsi",
332  [LONG_INSN_CLHHSI] = "clhhsi",
333  [LONG_INSN_LLGFRL] = "llgfrl",
334  [LONG_INSN_LLGHRL] = "llghrl",
335  [LONG_INSN_POPCNT] = "popcnt",
336  [LONG_INSN_RISBHG] = "risbhg",
337  [LONG_INSN_RISBLG] = "risblg",
338  [LONG_INSN_RINEXT] = "rinext",
339  [LONG_INSN_RIEMIT] = "riemit",
340  [LONG_INSN_TABORT] = "tabort",
341  [LONG_INSN_TBEGIN] = "tbegin",
342  [LONG_INSN_TBEGINC] = "tbeginc",
343 };
344 
345 static struct insn opcode[] = {
346 #ifdef CONFIG_64BIT
347  { "lmd", 0xef, INSTR_SS_RRRDRD3 },
348 #endif
349  { "spm", 0x04, INSTR_RR_R0 },
350  { "balr", 0x05, INSTR_RR_RR },
351  { "bctr", 0x06, INSTR_RR_RR },
352  { "bcr", 0x07, INSTR_RR_UR },
353  { "svc", 0x0a, INSTR_RR_U0 },
354  { "bsm", 0x0b, INSTR_RR_RR },
355  { "bassm", 0x0c, INSTR_RR_RR },
356  { "basr", 0x0d, INSTR_RR_RR },
357  { "mvcl", 0x0e, INSTR_RR_RR },
358  { "clcl", 0x0f, INSTR_RR_RR },
359  { "lpr", 0x10, INSTR_RR_RR },
360  { "lnr", 0x11, INSTR_RR_RR },
361  { "ltr", 0x12, INSTR_RR_RR },
362  { "lcr", 0x13, INSTR_RR_RR },
363  { "nr", 0x14, INSTR_RR_RR },
364  { "clr", 0x15, INSTR_RR_RR },
365  { "or", 0x16, INSTR_RR_RR },
366  { "xr", 0x17, INSTR_RR_RR },
367  { "lr", 0x18, INSTR_RR_RR },
368  { "cr", 0x19, INSTR_RR_RR },
369  { "ar", 0x1a, INSTR_RR_RR },
370  { "sr", 0x1b, INSTR_RR_RR },
371  { "mr", 0x1c, INSTR_RR_RR },
372  { "dr", 0x1d, INSTR_RR_RR },
373  { "alr", 0x1e, INSTR_RR_RR },
374  { "slr", 0x1f, INSTR_RR_RR },
375  { "lpdr", 0x20, INSTR_RR_FF },
376  { "lndr", 0x21, INSTR_RR_FF },
377  { "ltdr", 0x22, INSTR_RR_FF },
378  { "lcdr", 0x23, INSTR_RR_FF },
379  { "hdr", 0x24, INSTR_RR_FF },
380  { "ldxr", 0x25, INSTR_RR_FF },
381  { "lrdr", 0x25, INSTR_RR_FF },
382  { "mxr", 0x26, INSTR_RR_FF },
383  { "mxdr", 0x27, INSTR_RR_FF },
384  { "ldr", 0x28, INSTR_RR_FF },
385  { "cdr", 0x29, INSTR_RR_FF },
386  { "adr", 0x2a, INSTR_RR_FF },
387  { "sdr", 0x2b, INSTR_RR_FF },
388  { "mdr", 0x2c, INSTR_RR_FF },
389  { "ddr", 0x2d, INSTR_RR_FF },
390  { "awr", 0x2e, INSTR_RR_FF },
391  { "swr", 0x2f, INSTR_RR_FF },
392  { "lper", 0x30, INSTR_RR_FF },
393  { "lner", 0x31, INSTR_RR_FF },
394  { "lter", 0x32, INSTR_RR_FF },
395  { "lcer", 0x33, INSTR_RR_FF },
396  { "her", 0x34, INSTR_RR_FF },
397  { "ledr", 0x35, INSTR_RR_FF },
398  { "lrer", 0x35, INSTR_RR_FF },
399  { "axr", 0x36, INSTR_RR_FF },
400  { "sxr", 0x37, INSTR_RR_FF },
401  { "ler", 0x38, INSTR_RR_FF },
402  { "cer", 0x39, INSTR_RR_FF },
403  { "aer", 0x3a, INSTR_RR_FF },
404  { "ser", 0x3b, INSTR_RR_FF },
405  { "mder", 0x3c, INSTR_RR_FF },
406  { "mer", 0x3c, INSTR_RR_FF },
407  { "der", 0x3d, INSTR_RR_FF },
408  { "aur", 0x3e, INSTR_RR_FF },
409  { "sur", 0x3f, INSTR_RR_FF },
410  { "sth", 0x40, INSTR_RX_RRRD },
411  { "la", 0x41, INSTR_RX_RRRD },
412  { "stc", 0x42, INSTR_RX_RRRD },
413  { "ic", 0x43, INSTR_RX_RRRD },
414  { "ex", 0x44, INSTR_RX_RRRD },
415  { "bal", 0x45, INSTR_RX_RRRD },
416  { "bct", 0x46, INSTR_RX_RRRD },
417  { "bc", 0x47, INSTR_RX_URRD },
418  { "lh", 0x48, INSTR_RX_RRRD },
419  { "ch", 0x49, INSTR_RX_RRRD },
420  { "ah", 0x4a, INSTR_RX_RRRD },
421  { "sh", 0x4b, INSTR_RX_RRRD },
422  { "mh", 0x4c, INSTR_RX_RRRD },
423  { "bas", 0x4d, INSTR_RX_RRRD },
424  { "cvd", 0x4e, INSTR_RX_RRRD },
425  { "cvb", 0x4f, INSTR_RX_RRRD },
426  { "st", 0x50, INSTR_RX_RRRD },
427  { "lae", 0x51, INSTR_RX_RRRD },
428  { "n", 0x54, INSTR_RX_RRRD },
429  { "cl", 0x55, INSTR_RX_RRRD },
430  { "o", 0x56, INSTR_RX_RRRD },
431  { "x", 0x57, INSTR_RX_RRRD },
432  { "l", 0x58, INSTR_RX_RRRD },
433  { "c", 0x59, INSTR_RX_RRRD },
434  { "a", 0x5a, INSTR_RX_RRRD },
435  { "s", 0x5b, INSTR_RX_RRRD },
436  { "m", 0x5c, INSTR_RX_RRRD },
437  { "d", 0x5d, INSTR_RX_RRRD },
438  { "al", 0x5e, INSTR_RX_RRRD },
439  { "sl", 0x5f, INSTR_RX_RRRD },
440  { "std", 0x60, INSTR_RX_FRRD },
441  { "mxd", 0x67, INSTR_RX_FRRD },
442  { "ld", 0x68, INSTR_RX_FRRD },
443  { "cd", 0x69, INSTR_RX_FRRD },
444  { "ad", 0x6a, INSTR_RX_FRRD },
445  { "sd", 0x6b, INSTR_RX_FRRD },
446  { "md", 0x6c, INSTR_RX_FRRD },
447  { "dd", 0x6d, INSTR_RX_FRRD },
448  { "aw", 0x6e, INSTR_RX_FRRD },
449  { "sw", 0x6f, INSTR_RX_FRRD },
450  { "ste", 0x70, INSTR_RX_FRRD },
451  { "ms", 0x71, INSTR_RX_RRRD },
452  { "le", 0x78, INSTR_RX_FRRD },
453  { "ce", 0x79, INSTR_RX_FRRD },
454  { "ae", 0x7a, INSTR_RX_FRRD },
455  { "se", 0x7b, INSTR_RX_FRRD },
456  { "mde", 0x7c, INSTR_RX_FRRD },
457  { "me", 0x7c, INSTR_RX_FRRD },
458  { "de", 0x7d, INSTR_RX_FRRD },
459  { "au", 0x7e, INSTR_RX_FRRD },
460  { "su", 0x7f, INSTR_RX_FRRD },
461  { "ssm", 0x80, INSTR_S_RD },
462  { "lpsw", 0x82, INSTR_S_RD },
463  { "diag", 0x83, INSTR_RS_RRRD },
464  { "brxh", 0x84, INSTR_RSI_RRP },
465  { "brxle", 0x85, INSTR_RSI_RRP },
466  { "bxh", 0x86, INSTR_RS_RRRD },
467  { "bxle", 0x87, INSTR_RS_RRRD },
468  { "srl", 0x88, INSTR_RS_R0RD },
469  { "sll", 0x89, INSTR_RS_R0RD },
470  { "sra", 0x8a, INSTR_RS_R0RD },
471  { "sla", 0x8b, INSTR_RS_R0RD },
472  { "srdl", 0x8c, INSTR_RS_R0RD },
473  { "sldl", 0x8d, INSTR_RS_R0RD },
474  { "srda", 0x8e, INSTR_RS_R0RD },
475  { "slda", 0x8f, INSTR_RS_R0RD },
476  { "stm", 0x90, INSTR_RS_RRRD },
477  { "tm", 0x91, INSTR_SI_URD },
478  { "mvi", 0x92, INSTR_SI_URD },
479  { "ts", 0x93, INSTR_S_RD },
480  { "ni", 0x94, INSTR_SI_URD },
481  { "cli", 0x95, INSTR_SI_URD },
482  { "oi", 0x96, INSTR_SI_URD },
483  { "xi", 0x97, INSTR_SI_URD },
484  { "lm", 0x98, INSTR_RS_RRRD },
485  { "trace", 0x99, INSTR_RS_RRRD },
486  { "lam", 0x9a, INSTR_RS_AARD },
487  { "stam", 0x9b, INSTR_RS_AARD },
488  { "mvcle", 0xa8, INSTR_RS_RRRD },
489  { "clcle", 0xa9, INSTR_RS_RRRD },
490  { "stnsm", 0xac, INSTR_SI_URD },
491  { "stosm", 0xad, INSTR_SI_URD },
492  { "sigp", 0xae, INSTR_RS_RRRD },
493  { "mc", 0xaf, INSTR_SI_URD },
494  { "lra", 0xb1, INSTR_RX_RRRD },
495  { "stctl", 0xb6, INSTR_RS_CCRD },
496  { "lctl", 0xb7, INSTR_RS_CCRD },
497  { "cs", 0xba, INSTR_RS_RRRD },
498  { "cds", 0xbb, INSTR_RS_RRRD },
499  { "clm", 0xbd, INSTR_RS_RURD },
500  { "stcm", 0xbe, INSTR_RS_RURD },
501  { "icm", 0xbf, INSTR_RS_RURD },
502  { "mvn", 0xd1, INSTR_SS_L0RDRD },
503  { "mvc", 0xd2, INSTR_SS_L0RDRD },
504  { "mvz", 0xd3, INSTR_SS_L0RDRD },
505  { "nc", 0xd4, INSTR_SS_L0RDRD },
506  { "clc", 0xd5, INSTR_SS_L0RDRD },
507  { "oc", 0xd6, INSTR_SS_L0RDRD },
508  { "xc", 0xd7, INSTR_SS_L0RDRD },
509  { "mvck", 0xd9, INSTR_SS_RRRDRD },
510  { "mvcp", 0xda, INSTR_SS_RRRDRD },
511  { "mvcs", 0xdb, INSTR_SS_RRRDRD },
512  { "tr", 0xdc, INSTR_SS_L0RDRD },
513  { "trt", 0xdd, INSTR_SS_L0RDRD },
514  { "ed", 0xde, INSTR_SS_L0RDRD },
515  { "edmk", 0xdf, INSTR_SS_L0RDRD },
516  { "pku", 0xe1, INSTR_SS_L0RDRD },
517  { "unpku", 0xe2, INSTR_SS_L0RDRD },
518  { "mvcin", 0xe8, INSTR_SS_L0RDRD },
519  { "pka", 0xe9, INSTR_SS_L0RDRD },
520  { "unpka", 0xea, INSTR_SS_L0RDRD },
521  { "plo", 0xee, INSTR_SS_RRRDRD2 },
522  { "srp", 0xf0, INSTR_SS_LIRDRD },
523  { "mvo", 0xf1, INSTR_SS_LLRDRD },
524  { "pack", 0xf2, INSTR_SS_LLRDRD },
525  { "unpk", 0xf3, INSTR_SS_LLRDRD },
526  { "zap", 0xf8, INSTR_SS_LLRDRD },
527  { "cp", 0xf9, INSTR_SS_LLRDRD },
528  { "ap", 0xfa, INSTR_SS_LLRDRD },
529  { "sp", 0xfb, INSTR_SS_LLRDRD },
530  { "mp", 0xfc, INSTR_SS_LLRDRD },
531  { "dp", 0xfd, INSTR_SS_LLRDRD },
532  { "", 0, INSTR_INVALID }
533 };
534 
535 static struct insn opcode_01[] = {
536 #ifdef CONFIG_64BIT
537  { "sam64", 0x0e, INSTR_E },
538  { "pfpo", 0x0a, INSTR_E },
539  { "ptff", 0x04, INSTR_E },
540 #endif
541  { "pr", 0x01, INSTR_E },
542  { "upt", 0x02, INSTR_E },
543  { "sckpf", 0x07, INSTR_E },
544  { "tam", 0x0b, INSTR_E },
545  { "sam24", 0x0c, INSTR_E },
546  { "sam31", 0x0d, INSTR_E },
547  { "trap2", 0xff, INSTR_E },
548  { "", 0, INSTR_INVALID }
549 };
550 
551 static struct insn opcode_a5[] = {
552 #ifdef CONFIG_64BIT
553  { "iihh", 0x00, INSTR_RI_RU },
554  { "iihl", 0x01, INSTR_RI_RU },
555  { "iilh", 0x02, INSTR_RI_RU },
556  { "iill", 0x03, INSTR_RI_RU },
557  { "nihh", 0x04, INSTR_RI_RU },
558  { "nihl", 0x05, INSTR_RI_RU },
559  { "nilh", 0x06, INSTR_RI_RU },
560  { "nill", 0x07, INSTR_RI_RU },
561  { "oihh", 0x08, INSTR_RI_RU },
562  { "oihl", 0x09, INSTR_RI_RU },
563  { "oilh", 0x0a, INSTR_RI_RU },
564  { "oill", 0x0b, INSTR_RI_RU },
565  { "llihh", 0x0c, INSTR_RI_RU },
566  { "llihl", 0x0d, INSTR_RI_RU },
567  { "llilh", 0x0e, INSTR_RI_RU },
568  { "llill", 0x0f, INSTR_RI_RU },
569 #endif
570  { "", 0, INSTR_INVALID }
571 };
572 
573 static struct insn opcode_a7[] = {
574 #ifdef CONFIG_64BIT
575  { "tmhh", 0x02, INSTR_RI_RU },
576  { "tmhl", 0x03, INSTR_RI_RU },
577  { "brctg", 0x07, INSTR_RI_RP },
578  { "lghi", 0x09, INSTR_RI_RI },
579  { "aghi", 0x0b, INSTR_RI_RI },
580  { "mghi", 0x0d, INSTR_RI_RI },
581  { "cghi", 0x0f, INSTR_RI_RI },
582 #endif
583  { "tmlh", 0x00, INSTR_RI_RU },
584  { "tmll", 0x01, INSTR_RI_RU },
585  { "brc", 0x04, INSTR_RI_UP },
586  { "bras", 0x05, INSTR_RI_RP },
587  { "brct", 0x06, INSTR_RI_RP },
588  { "lhi", 0x08, INSTR_RI_RI },
589  { "ahi", 0x0a, INSTR_RI_RI },
590  { "mhi", 0x0c, INSTR_RI_RI },
591  { "chi", 0x0e, INSTR_RI_RI },
592  { "", 0, INSTR_INVALID }
593 };
594 
595 static struct insn opcode_aa[] = {
596 #ifdef CONFIG_64BIT
597  { { 0, LONG_INSN_RINEXT }, 0x00, INSTR_RI_RI },
598  { "rion", 0x01, INSTR_RI_RI },
599  { "tric", 0x02, INSTR_RI_RI },
600  { "rioff", 0x03, INSTR_RI_RI },
601  { { 0, LONG_INSN_RIEMIT }, 0x04, INSTR_RI_RI },
602 #endif
603  { "", 0, INSTR_INVALID }
604 };
605 
606 static struct insn opcode_b2[] = {
607 #ifdef CONFIG_64BIT
608  { "sske", 0x2b, INSTR_RRF_M0RR },
609  { "stckf", 0x7c, INSTR_S_RD },
610  { "cu21", 0xa6, INSTR_RRF_M0RR },
611  { "cuutf", 0xa6, INSTR_RRF_M0RR },
612  { "cu12", 0xa7, INSTR_RRF_M0RR },
613  { "cutfu", 0xa7, INSTR_RRF_M0RR },
614  { "stfle", 0xb0, INSTR_S_RD },
615  { "lpswe", 0xb2, INSTR_S_RD },
616  { "srnmt", 0xb9, INSTR_S_RD },
617  { "lfas", 0xbd, INSTR_S_RD },
618  { "etndg", 0xec, INSTR_RRE_R0 },
619  { { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD },
620  { "tend", 0xf8, INSTR_S_RD },
621 #endif
622  { "stidp", 0x02, INSTR_S_RD },
623  { "sck", 0x04, INSTR_S_RD },
624  { "stck", 0x05, INSTR_S_RD },
625  { "sckc", 0x06, INSTR_S_RD },
626  { "stckc", 0x07, INSTR_S_RD },
627  { "spt", 0x08, INSTR_S_RD },
628  { "stpt", 0x09, INSTR_S_RD },
629  { "spka", 0x0a, INSTR_S_RD },
630  { "ipk", 0x0b, INSTR_S_00 },
631  { "ptlb", 0x0d, INSTR_S_00 },
632  { "spx", 0x10, INSTR_S_RD },
633  { "stpx", 0x11, INSTR_S_RD },
634  { "stap", 0x12, INSTR_S_RD },
635  { "sie", 0x14, INSTR_S_RD },
636  { "pc", 0x18, INSTR_S_RD },
637  { "sac", 0x19, INSTR_S_RD },
638  { "servc", 0x20, INSTR_RRE_RR },
639  { "cfc", 0x1a, INSTR_S_RD },
640  { "ipte", 0x21, INSTR_RRE_RR },
641  { "ipm", 0x22, INSTR_RRE_R0 },
642  { "ivsk", 0x23, INSTR_RRE_RR },
643  { "iac", 0x24, INSTR_RRE_R0 },
644  { "ssar", 0x25, INSTR_RRE_R0 },
645  { "epar", 0x26, INSTR_RRE_R0 },
646  { "esar", 0x27, INSTR_RRE_R0 },
647  { "pt", 0x28, INSTR_RRE_RR },
648  { "iske", 0x29, INSTR_RRE_RR },
649  { "rrbe", 0x2a, INSTR_RRE_RR },
650  { "sske", 0x2b, INSTR_RRE_RR },
651  { "tb", 0x2c, INSTR_RRE_0R },
652  { "dxr", 0x2d, INSTR_RRE_F0 },
653  { "pgin", 0x2e, INSTR_RRE_RR },
654  { "pgout", 0x2f, INSTR_RRE_RR },
655  { "csch", 0x30, INSTR_S_00 },
656  { "hsch", 0x31, INSTR_S_00 },
657  { "msch", 0x32, INSTR_S_RD },
658  { "ssch", 0x33, INSTR_S_RD },
659  { "stsch", 0x34, INSTR_S_RD },
660  { "tsch", 0x35, INSTR_S_RD },
661  { "tpi", 0x36, INSTR_S_RD },
662  { "sal", 0x37, INSTR_S_00 },
663  { "rsch", 0x38, INSTR_S_00 },
664  { "stcrw", 0x39, INSTR_S_RD },
665  { "stcps", 0x3a, INSTR_S_RD },
666  { "rchp", 0x3b, INSTR_S_00 },
667  { "schm", 0x3c, INSTR_S_00 },
668  { "bakr", 0x40, INSTR_RRE_RR },
669  { "cksm", 0x41, INSTR_RRE_RR },
670  { "sqdr", 0x44, INSTR_RRE_F0 },
671  { "sqer", 0x45, INSTR_RRE_F0 },
672  { "stura", 0x46, INSTR_RRE_RR },
673  { "msta", 0x47, INSTR_RRE_R0 },
674  { "palb", 0x48, INSTR_RRE_00 },
675  { "ereg", 0x49, INSTR_RRE_RR },
676  { "esta", 0x4a, INSTR_RRE_RR },
677  { "lura", 0x4b, INSTR_RRE_RR },
678  { "tar", 0x4c, INSTR_RRE_AR },
679  { "cpya", 0x4d, INSTR_RRE_AA },
680  { "sar", 0x4e, INSTR_RRE_AR },
681  { "ear", 0x4f, INSTR_RRE_RA },
682  { "csp", 0x50, INSTR_RRE_RR },
683  { "msr", 0x52, INSTR_RRE_RR },
684  { "mvpg", 0x54, INSTR_RRE_RR },
685  { "mvst", 0x55, INSTR_RRE_RR },
686  { "cuse", 0x57, INSTR_RRE_RR },
687  { "bsg", 0x58, INSTR_RRE_RR },
688  { "bsa", 0x5a, INSTR_RRE_RR },
689  { "clst", 0x5d, INSTR_RRE_RR },
690  { "srst", 0x5e, INSTR_RRE_RR },
691  { "cmpsc", 0x63, INSTR_RRE_RR },
692  { "siga", 0x74, INSTR_S_RD },
693  { "xsch", 0x76, INSTR_S_00 },
694  { "rp", 0x77, INSTR_S_RD },
695  { "stcke", 0x78, INSTR_S_RD },
696  { "sacf", 0x79, INSTR_S_RD },
697  { "spp", 0x80, INSTR_S_RD },
698  { "stsi", 0x7d, INSTR_S_RD },
699  { "srnm", 0x99, INSTR_S_RD },
700  { "stfpc", 0x9c, INSTR_S_RD },
701  { "lfpc", 0x9d, INSTR_S_RD },
702  { "tre", 0xa5, INSTR_RRE_RR },
703  { "cuutf", 0xa6, INSTR_RRE_RR },
704  { "cutfu", 0xa7, INSTR_RRE_RR },
705  { "stfl", 0xb1, INSTR_S_RD },
706  { "trap4", 0xff, INSTR_S_RD },
707  { "", 0, INSTR_INVALID }
708 };
709 
710 static struct insn opcode_b3[] = {
711 #ifdef CONFIG_64BIT
712  { "maylr", 0x38, INSTR_RRF_F0FF },
713  { "mylr", 0x39, INSTR_RRF_F0FF },
714  { "mayr", 0x3a, INSTR_RRF_F0FF },
715  { "myr", 0x3b, INSTR_RRF_F0FF },
716  { "mayhr", 0x3c, INSTR_RRF_F0FF },
717  { "myhr", 0x3d, INSTR_RRF_F0FF },
718  { "cegbr", 0xa4, INSTR_RRE_RR },
719  { "cdgbr", 0xa5, INSTR_RRE_RR },
720  { "cxgbr", 0xa6, INSTR_RRE_RR },
721  { "cgebr", 0xa8, INSTR_RRF_U0RF },
722  { "cgdbr", 0xa9, INSTR_RRF_U0RF },
723  { "cgxbr", 0xaa, INSTR_RRF_U0RF },
724  { "cfer", 0xb8, INSTR_RRF_U0RF },
725  { "cfdr", 0xb9, INSTR_RRF_U0RF },
726  { "cfxr", 0xba, INSTR_RRF_U0RF },
727  { "cegr", 0xc4, INSTR_RRE_RR },
728  { "cdgr", 0xc5, INSTR_RRE_RR },
729  { "cxgr", 0xc6, INSTR_RRE_RR },
730  { "cger", 0xc8, INSTR_RRF_U0RF },
731  { "cgdr", 0xc9, INSTR_RRF_U0RF },
732  { "cgxr", 0xca, INSTR_RRF_U0RF },
733  { "lpdfr", 0x70, INSTR_RRE_FF },
734  { "lndfr", 0x71, INSTR_RRE_FF },
735  { "cpsdr", 0x72, INSTR_RRF_F0FF2 },
736  { "lcdfr", 0x73, INSTR_RRE_FF },
737  { "ldgr", 0xc1, INSTR_RRE_FR },
738  { "lgdr", 0xcd, INSTR_RRE_RF },
739  { "adtr", 0xd2, INSTR_RRR_F0FF },
740  { "axtr", 0xda, INSTR_RRR_F0FF },
741  { "cdtr", 0xe4, INSTR_RRE_FF },
742  { "cxtr", 0xec, INSTR_RRE_FF },
743  { "kdtr", 0xe0, INSTR_RRE_FF },
744  { "kxtr", 0xe8, INSTR_RRE_FF },
745  { "cedtr", 0xf4, INSTR_RRE_FF },
746  { "cextr", 0xfc, INSTR_RRE_FF },
747  { "cdgtr", 0xf1, INSTR_RRE_FR },
748  { "cxgtr", 0xf9, INSTR_RRE_FR },
749  { "cdstr", 0xf3, INSTR_RRE_FR },
750  { "cxstr", 0xfb, INSTR_RRE_FR },
751  { "cdutr", 0xf2, INSTR_RRE_FR },
752  { "cxutr", 0xfa, INSTR_RRE_FR },
753  { "cgdtr", 0xe1, INSTR_RRF_U0RF },
754  { "cgxtr", 0xe9, INSTR_RRF_U0RF },
755  { "csdtr", 0xe3, INSTR_RRE_RF },
756  { "csxtr", 0xeb, INSTR_RRE_RF },
757  { "cudtr", 0xe2, INSTR_RRE_RF },
758  { "cuxtr", 0xea, INSTR_RRE_RF },
759  { "ddtr", 0xd1, INSTR_RRR_F0FF },
760  { "dxtr", 0xd9, INSTR_RRR_F0FF },
761  { "eedtr", 0xe5, INSTR_RRE_RF },
762  { "eextr", 0xed, INSTR_RRE_RF },
763  { "esdtr", 0xe7, INSTR_RRE_RF },
764  { "esxtr", 0xef, INSTR_RRE_RF },
765  { "iedtr", 0xf6, INSTR_RRF_F0FR },
766  { "iextr", 0xfe, INSTR_RRF_F0FR },
767  { "ltdtr", 0xd6, INSTR_RRE_FF },
768  { "ltxtr", 0xde, INSTR_RRE_FF },
769  { "fidtr", 0xd7, INSTR_RRF_UUFF },
770  { "fixtr", 0xdf, INSTR_RRF_UUFF },
771  { "ldetr", 0xd4, INSTR_RRF_0UFF },
772  { "lxdtr", 0xdc, INSTR_RRF_0UFF },
773  { "ledtr", 0xd5, INSTR_RRF_UUFF },
774  { "ldxtr", 0xdd, INSTR_RRF_UUFF },
775  { "mdtr", 0xd0, INSTR_RRR_F0FF },
776  { "mxtr", 0xd8, INSTR_RRR_F0FF },
777  { "qadtr", 0xf5, INSTR_RRF_FUFF },
778  { "qaxtr", 0xfd, INSTR_RRF_FUFF },
779  { "rrdtr", 0xf7, INSTR_RRF_FFRU },
780  { "rrxtr", 0xff, INSTR_RRF_FFRU },
781  { "sfasr", 0x85, INSTR_RRE_R0 },
782  { "sdtr", 0xd3, INSTR_RRR_F0FF },
783  { "sxtr", 0xdb, INSTR_RRR_F0FF },
784 #endif
785  { "lpebr", 0x00, INSTR_RRE_FF },
786  { "lnebr", 0x01, INSTR_RRE_FF },
787  { "ltebr", 0x02, INSTR_RRE_FF },
788  { "lcebr", 0x03, INSTR_RRE_FF },
789  { "ldebr", 0x04, INSTR_RRE_FF },
790  { "lxdbr", 0x05, INSTR_RRE_FF },
791  { "lxebr", 0x06, INSTR_RRE_FF },
792  { "mxdbr", 0x07, INSTR_RRE_FF },
793  { "kebr", 0x08, INSTR_RRE_FF },
794  { "cebr", 0x09, INSTR_RRE_FF },
795  { "aebr", 0x0a, INSTR_RRE_FF },
796  { "sebr", 0x0b, INSTR_RRE_FF },
797  { "mdebr", 0x0c, INSTR_RRE_FF },
798  { "debr", 0x0d, INSTR_RRE_FF },
799  { "maebr", 0x0e, INSTR_RRF_F0FF },
800  { "msebr", 0x0f, INSTR_RRF_F0FF },
801  { "lpdbr", 0x10, INSTR_RRE_FF },
802  { "lndbr", 0x11, INSTR_RRE_FF },
803  { "ltdbr", 0x12, INSTR_RRE_FF },
804  { "lcdbr", 0x13, INSTR_RRE_FF },
805  { "sqebr", 0x14, INSTR_RRE_FF },
806  { "sqdbr", 0x15, INSTR_RRE_FF },
807  { "sqxbr", 0x16, INSTR_RRE_FF },
808  { "meebr", 0x17, INSTR_RRE_FF },
809  { "kdbr", 0x18, INSTR_RRE_FF },
810  { "cdbr", 0x19, INSTR_RRE_FF },
811  { "adbr", 0x1a, INSTR_RRE_FF },
812  { "sdbr", 0x1b, INSTR_RRE_FF },
813  { "mdbr", 0x1c, INSTR_RRE_FF },
814  { "ddbr", 0x1d, INSTR_RRE_FF },
815  { "madbr", 0x1e, INSTR_RRF_F0FF },
816  { "msdbr", 0x1f, INSTR_RRF_F0FF },
817  { "lder", 0x24, INSTR_RRE_FF },
818  { "lxdr", 0x25, INSTR_RRE_FF },
819  { "lxer", 0x26, INSTR_RRE_FF },
820  { "maer", 0x2e, INSTR_RRF_F0FF },
821  { "mser", 0x2f, INSTR_RRF_F0FF },
822  { "sqxr", 0x36, INSTR_RRE_FF },
823  { "meer", 0x37, INSTR_RRE_FF },
824  { "madr", 0x3e, INSTR_RRF_F0FF },
825  { "msdr", 0x3f, INSTR_RRF_F0FF },
826  { "lpxbr", 0x40, INSTR_RRE_FF },
827  { "lnxbr", 0x41, INSTR_RRE_FF },
828  { "ltxbr", 0x42, INSTR_RRE_FF },
829  { "lcxbr", 0x43, INSTR_RRE_FF },
830  { "ledbr", 0x44, INSTR_RRE_FF },
831  { "ldxbr", 0x45, INSTR_RRE_FF },
832  { "lexbr", 0x46, INSTR_RRE_FF },
833  { "fixbr", 0x47, INSTR_RRF_U0FF },
834  { "kxbr", 0x48, INSTR_RRE_FF },
835  { "cxbr", 0x49, INSTR_RRE_FF },
836  { "axbr", 0x4a, INSTR_RRE_FF },
837  { "sxbr", 0x4b, INSTR_RRE_FF },
838  { "mxbr", 0x4c, INSTR_RRE_FF },
839  { "dxbr", 0x4d, INSTR_RRE_FF },
840  { "tbedr", 0x50, INSTR_RRF_U0FF },
841  { "tbdr", 0x51, INSTR_RRF_U0FF },
842  { "diebr", 0x53, INSTR_RRF_FUFF },
843  { "fiebr", 0x57, INSTR_RRF_U0FF },
844  { "thder", 0x58, INSTR_RRE_RR },
845  { "thdr", 0x59, INSTR_RRE_RR },
846  { "didbr", 0x5b, INSTR_RRF_FUFF },
847  { "fidbr", 0x5f, INSTR_RRF_U0FF },
848  { "lpxr", 0x60, INSTR_RRE_FF },
849  { "lnxr", 0x61, INSTR_RRE_FF },
850  { "ltxr", 0x62, INSTR_RRE_FF },
851  { "lcxr", 0x63, INSTR_RRE_FF },
852  { "lxr", 0x65, INSTR_RRE_RR },
853  { "lexr", 0x66, INSTR_RRE_FF },
854  { "fixr", 0x67, INSTR_RRF_U0FF },
855  { "cxr", 0x69, INSTR_RRE_FF },
856  { "lzer", 0x74, INSTR_RRE_R0 },
857  { "lzdr", 0x75, INSTR_RRE_R0 },
858  { "lzxr", 0x76, INSTR_RRE_R0 },
859  { "fier", 0x77, INSTR_RRF_U0FF },
860  { "fidr", 0x7f, INSTR_RRF_U0FF },
861  { "sfpc", 0x84, INSTR_RRE_RR_OPT },
862  { "efpc", 0x8c, INSTR_RRE_RR_OPT },
863  { "cefbr", 0x94, INSTR_RRE_RF },
864  { "cdfbr", 0x95, INSTR_RRE_RF },
865  { "cxfbr", 0x96, INSTR_RRE_RF },
866  { "cfebr", 0x98, INSTR_RRF_U0RF },
867  { "cfdbr", 0x99, INSTR_RRF_U0RF },
868  { "cfxbr", 0x9a, INSTR_RRF_U0RF },
869  { "cefr", 0xb4, INSTR_RRE_RF },
870  { "cdfr", 0xb5, INSTR_RRE_RF },
871  { "cxfr", 0xb6, INSTR_RRE_RF },
872  { "", 0, INSTR_INVALID }
873 };
874 
875 static struct insn opcode_b9[] = {
876 #ifdef CONFIG_64BIT
877  { "lpgr", 0x00, INSTR_RRE_RR },
878  { "lngr", 0x01, INSTR_RRE_RR },
879  { "ltgr", 0x02, INSTR_RRE_RR },
880  { "lcgr", 0x03, INSTR_RRE_RR },
881  { "lgr", 0x04, INSTR_RRE_RR },
882  { "lurag", 0x05, INSTR_RRE_RR },
883  { "lgbr", 0x06, INSTR_RRE_RR },
884  { "lghr", 0x07, INSTR_RRE_RR },
885  { "agr", 0x08, INSTR_RRE_RR },
886  { "sgr", 0x09, INSTR_RRE_RR },
887  { "algr", 0x0a, INSTR_RRE_RR },
888  { "slgr", 0x0b, INSTR_RRE_RR },
889  { "msgr", 0x0c, INSTR_RRE_RR },
890  { "dsgr", 0x0d, INSTR_RRE_RR },
891  { "eregg", 0x0e, INSTR_RRE_RR },
892  { "lrvgr", 0x0f, INSTR_RRE_RR },
893  { "lpgfr", 0x10, INSTR_RRE_RR },
894  { "lngfr", 0x11, INSTR_RRE_RR },
895  { "ltgfr", 0x12, INSTR_RRE_RR },
896  { "lcgfr", 0x13, INSTR_RRE_RR },
897  { "lgfr", 0x14, INSTR_RRE_RR },
898  { "llgfr", 0x16, INSTR_RRE_RR },
899  { "llgtr", 0x17, INSTR_RRE_RR },
900  { "agfr", 0x18, INSTR_RRE_RR },
901  { "sgfr", 0x19, INSTR_RRE_RR },
902  { "algfr", 0x1a, INSTR_RRE_RR },
903  { "slgfr", 0x1b, INSTR_RRE_RR },
904  { "msgfr", 0x1c, INSTR_RRE_RR },
905  { "dsgfr", 0x1d, INSTR_RRE_RR },
906  { "cgr", 0x20, INSTR_RRE_RR },
907  { "clgr", 0x21, INSTR_RRE_RR },
908  { "sturg", 0x25, INSTR_RRE_RR },
909  { "lbr", 0x26, INSTR_RRE_RR },
910  { "lhr", 0x27, INSTR_RRE_RR },
911  { "cgfr", 0x30, INSTR_RRE_RR },
912  { "clgfr", 0x31, INSTR_RRE_RR },
913  { "bctgr", 0x46, INSTR_RRE_RR },
914  { "ngr", 0x80, INSTR_RRE_RR },
915  { "ogr", 0x81, INSTR_RRE_RR },
916  { "xgr", 0x82, INSTR_RRE_RR },
917  { "flogr", 0x83, INSTR_RRE_RR },
918  { "llgcr", 0x84, INSTR_RRE_RR },
919  { "llghr", 0x85, INSTR_RRE_RR },
920  { "mlgr", 0x86, INSTR_RRE_RR },
921  { "dlgr", 0x87, INSTR_RRE_RR },
922  { "alcgr", 0x88, INSTR_RRE_RR },
923  { "slbgr", 0x89, INSTR_RRE_RR },
924  { "cspg", 0x8a, INSTR_RRE_RR },
925  { "idte", 0x8e, INSTR_RRF_R0RR },
926  { "llcr", 0x94, INSTR_RRE_RR },
927  { "llhr", 0x95, INSTR_RRE_RR },
928  { "esea", 0x9d, INSTR_RRE_R0 },
929  { "lptea", 0xaa, INSTR_RRF_RURR },
930  { "cu14", 0xb0, INSTR_RRF_M0RR },
931  { "cu24", 0xb1, INSTR_RRF_M0RR },
932  { "cu41", 0xb2, INSTR_RRF_M0RR },
933  { "cu42", 0xb3, INSTR_RRF_M0RR },
934  { "crt", 0x72, INSTR_RRF_U0RR },
935  { "cgrt", 0x60, INSTR_RRF_U0RR },
936  { "clrt", 0x73, INSTR_RRF_U0RR },
937  { "clgrt", 0x61, INSTR_RRF_U0RR },
938  { "ptf", 0xa2, INSTR_RRE_R0 },
939  { "pfmf", 0xaf, INSTR_RRE_RR },
940  { "trte", 0xbf, INSTR_RRF_M0RR },
941  { "trtre", 0xbd, INSTR_RRF_M0RR },
942  { "ahhhr", 0xc8, INSTR_RRF_R0RR2 },
943  { "shhhr", 0xc9, INSTR_RRF_R0RR2 },
944  { "alhhh", 0xca, INSTR_RRF_R0RR2 },
945  { "alhhl", 0xca, INSTR_RRF_R0RR2 },
946  { "slhhh", 0xcb, INSTR_RRF_R0RR2 },
947  { "chhr ", 0xcd, INSTR_RRE_RR },
948  { "clhhr", 0xcf, INSTR_RRE_RR },
949  { "ahhlr", 0xd8, INSTR_RRF_R0RR2 },
950  { "shhlr", 0xd9, INSTR_RRF_R0RR2 },
951  { "slhhl", 0xdb, INSTR_RRF_R0RR2 },
952  { "chlr", 0xdd, INSTR_RRE_RR },
953  { "clhlr", 0xdf, INSTR_RRE_RR },
954  { { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR },
955  { "locgr", 0xe2, INSTR_RRF_M0RR },
956  { "ngrk", 0xe4, INSTR_RRF_R0RR2 },
957  { "ogrk", 0xe6, INSTR_RRF_R0RR2 },
958  { "xgrk", 0xe7, INSTR_RRF_R0RR2 },
959  { "agrk", 0xe8, INSTR_RRF_R0RR2 },
960  { "sgrk", 0xe9, INSTR_RRF_R0RR2 },
961  { "algrk", 0xea, INSTR_RRF_R0RR2 },
962  { "slgrk", 0xeb, INSTR_RRF_R0RR2 },
963  { "locr", 0xf2, INSTR_RRF_M0RR },
964  { "nrk", 0xf4, INSTR_RRF_R0RR2 },
965  { "ork", 0xf6, INSTR_RRF_R0RR2 },
966  { "xrk", 0xf7, INSTR_RRF_R0RR2 },
967  { "ark", 0xf8, INSTR_RRF_R0RR2 },
968  { "srk", 0xf9, INSTR_RRF_R0RR2 },
969  { "alrk", 0xfa, INSTR_RRF_R0RR2 },
970  { "slrk", 0xfb, INSTR_RRF_R0RR2 },
971 #endif
972  { "kmac", 0x1e, INSTR_RRE_RR },
973  { "lrvr", 0x1f, INSTR_RRE_RR },
974  { "km", 0x2e, INSTR_RRE_RR },
975  { "kmc", 0x2f, INSTR_RRE_RR },
976  { "kimd", 0x3e, INSTR_RRE_RR },
977  { "klmd", 0x3f, INSTR_RRE_RR },
978  { "epsw", 0x8d, INSTR_RRE_RR },
979  { "trtt", 0x90, INSTR_RRE_RR },
980  { "trtt", 0x90, INSTR_RRF_M0RR },
981  { "trto", 0x91, INSTR_RRE_RR },
982  { "trto", 0x91, INSTR_RRF_M0RR },
983  { "trot", 0x92, INSTR_RRE_RR },
984  { "trot", 0x92, INSTR_RRF_M0RR },
985  { "troo", 0x93, INSTR_RRE_RR },
986  { "troo", 0x93, INSTR_RRF_M0RR },
987  { "mlr", 0x96, INSTR_RRE_RR },
988  { "dlr", 0x97, INSTR_RRE_RR },
989  { "alcr", 0x98, INSTR_RRE_RR },
990  { "slbr", 0x99, INSTR_RRE_RR },
991  { "", 0, INSTR_INVALID }
992 };
993 
994 static struct insn opcode_c0[] = {
995 #ifdef CONFIG_64BIT
996  { "lgfi", 0x01, INSTR_RIL_RI },
997  { "xihf", 0x06, INSTR_RIL_RU },
998  { "xilf", 0x07, INSTR_RIL_RU },
999  { "iihf", 0x08, INSTR_RIL_RU },
1000  { "iilf", 0x09, INSTR_RIL_RU },
1001  { "nihf", 0x0a, INSTR_RIL_RU },
1002  { "nilf", 0x0b, INSTR_RIL_RU },
1003  { "oihf", 0x0c, INSTR_RIL_RU },
1004  { "oilf", 0x0d, INSTR_RIL_RU },
1005  { "llihf", 0x0e, INSTR_RIL_RU },
1006  { "llilf", 0x0f, INSTR_RIL_RU },
1007 #endif
1008  { "larl", 0x00, INSTR_RIL_RP },
1009  { "brcl", 0x04, INSTR_RIL_UP },
1010  { "brasl", 0x05, INSTR_RIL_RP },
1011  { "", 0, INSTR_INVALID }
1012 };
1013 
1014 static struct insn opcode_c2[] = {
1015 #ifdef CONFIG_64BIT
1016  { "slgfi", 0x04, INSTR_RIL_RU },
1017  { "slfi", 0x05, INSTR_RIL_RU },
1018  { "agfi", 0x08, INSTR_RIL_RI },
1019  { "afi", 0x09, INSTR_RIL_RI },
1020  { "algfi", 0x0a, INSTR_RIL_RU },
1021  { "alfi", 0x0b, INSTR_RIL_RU },
1022  { "cgfi", 0x0c, INSTR_RIL_RI },
1023  { "cfi", 0x0d, INSTR_RIL_RI },
1024  { "clgfi", 0x0e, INSTR_RIL_RU },
1025  { "clfi", 0x0f, INSTR_RIL_RU },
1026  { "msfi", 0x01, INSTR_RIL_RI },
1027  { "msgfi", 0x00, INSTR_RIL_RI },
1028 #endif
1029  { "", 0, INSTR_INVALID }
1030 };
1031 
1032 static struct insn opcode_c4[] = {
1033 #ifdef CONFIG_64BIT
1034  { "lrl", 0x0d, INSTR_RIL_RP },
1035  { "lgrl", 0x08, INSTR_RIL_RP },
1036  { "lgfrl", 0x0c, INSTR_RIL_RP },
1037  { "lhrl", 0x05, INSTR_RIL_RP },
1038  { "lghrl", 0x04, INSTR_RIL_RP },
1039  { { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP },
1040  { "llhrl", 0x02, INSTR_RIL_RP },
1041  { { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP },
1042  { "strl", 0x0f, INSTR_RIL_RP },
1043  { "stgrl", 0x0b, INSTR_RIL_RP },
1044  { "sthrl", 0x07, INSTR_RIL_RP },
1045 #endif
1046  { "", 0, INSTR_INVALID }
1047 };
1048 
1049 static struct insn opcode_c6[] = {
1050 #ifdef CONFIG_64BIT
1051  { "crl", 0x0d, INSTR_RIL_RP },
1052  { "cgrl", 0x08, INSTR_RIL_RP },
1053  { "cgfrl", 0x0c, INSTR_RIL_RP },
1054  { "chrl", 0x05, INSTR_RIL_RP },
1055  { "cghrl", 0x04, INSTR_RIL_RP },
1056  { "clrl", 0x0f, INSTR_RIL_RP },
1057  { "clgrl", 0x0a, INSTR_RIL_RP },
1058  { { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP },
1059  { "clhrl", 0x07, INSTR_RIL_RP },
1060  { { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP },
1061  { "pfdrl", 0x02, INSTR_RIL_UP },
1062  { "exrl", 0x00, INSTR_RIL_RP },
1063 #endif
1064  { "", 0, INSTR_INVALID }
1065 };
1066 
1067 static struct insn opcode_c8[] = {
1068 #ifdef CONFIG_64BIT
1069  { "mvcos", 0x00, INSTR_SSF_RRDRD },
1070  { "ectg", 0x01, INSTR_SSF_RRDRD },
1071  { "csst", 0x02, INSTR_SSF_RRDRD },
1072  { "lpd", 0x04, INSTR_SSF_RRDRD2 },
1073  { "lpdg ", 0x05, INSTR_SSF_RRDRD2 },
1074 #endif
1075  { "", 0, INSTR_INVALID }
1076 };
1077 
1078 static struct insn opcode_cc[] = {
1079 #ifdef CONFIG_64BIT
1080  { "brcth", 0x06, INSTR_RIL_RP },
1081  { "aih", 0x08, INSTR_RIL_RI },
1082  { "alsih", 0x0a, INSTR_RIL_RI },
1083  { "alsih", 0x0b, INSTR_RIL_RI },
1084  { "cih", 0x0d, INSTR_RIL_RI },
1085  { "clih ", 0x0f, INSTR_RIL_RI },
1086 #endif
1087  { "", 0, INSTR_INVALID }
1088 };
1089 
1090 static struct insn opcode_e3[] = {
1091 #ifdef CONFIG_64BIT
1092  { "ltg", 0x02, INSTR_RXY_RRRD },
1093  { "lrag", 0x03, INSTR_RXY_RRRD },
1094  { "lg", 0x04, INSTR_RXY_RRRD },
1095  { "cvby", 0x06, INSTR_RXY_RRRD },
1096  { "ag", 0x08, INSTR_RXY_RRRD },
1097  { "sg", 0x09, INSTR_RXY_RRRD },
1098  { "alg", 0x0a, INSTR_RXY_RRRD },
1099  { "slg", 0x0b, INSTR_RXY_RRRD },
1100  { "msg", 0x0c, INSTR_RXY_RRRD },
1101  { "dsg", 0x0d, INSTR_RXY_RRRD },
1102  { "cvbg", 0x0e, INSTR_RXY_RRRD },
1103  { "lrvg", 0x0f, INSTR_RXY_RRRD },
1104  { "lt", 0x12, INSTR_RXY_RRRD },
1105  { "lray", 0x13, INSTR_RXY_RRRD },
1106  { "lgf", 0x14, INSTR_RXY_RRRD },
1107  { "lgh", 0x15, INSTR_RXY_RRRD },
1108  { "llgf", 0x16, INSTR_RXY_RRRD },
1109  { "llgt", 0x17, INSTR_RXY_RRRD },
1110  { "agf", 0x18, INSTR_RXY_RRRD },
1111  { "sgf", 0x19, INSTR_RXY_RRRD },
1112  { "algf", 0x1a, INSTR_RXY_RRRD },
1113  { "slgf", 0x1b, INSTR_RXY_RRRD },
1114  { "msgf", 0x1c, INSTR_RXY_RRRD },
1115  { "dsgf", 0x1d, INSTR_RXY_RRRD },
1116  { "cg", 0x20, INSTR_RXY_RRRD },
1117  { "clg", 0x21, INSTR_RXY_RRRD },
1118  { "stg", 0x24, INSTR_RXY_RRRD },
1119  { "cvdy", 0x26, INSTR_RXY_RRRD },
1120  { "cvdg", 0x2e, INSTR_RXY_RRRD },
1121  { "strvg", 0x2f, INSTR_RXY_RRRD },
1122  { "cgf", 0x30, INSTR_RXY_RRRD },
1123  { "clgf", 0x31, INSTR_RXY_RRRD },
1124  { "strvh", 0x3f, INSTR_RXY_RRRD },
1125  { "bctg", 0x46, INSTR_RXY_RRRD },
1126  { "sty", 0x50, INSTR_RXY_RRRD },
1127  { "msy", 0x51, INSTR_RXY_RRRD },
1128  { "ny", 0x54, INSTR_RXY_RRRD },
1129  { "cly", 0x55, INSTR_RXY_RRRD },
1130  { "oy", 0x56, INSTR_RXY_RRRD },
1131  { "xy", 0x57, INSTR_RXY_RRRD },
1132  { "ly", 0x58, INSTR_RXY_RRRD },
1133  { "cy", 0x59, INSTR_RXY_RRRD },
1134  { "ay", 0x5a, INSTR_RXY_RRRD },
1135  { "sy", 0x5b, INSTR_RXY_RRRD },
1136  { "aly", 0x5e, INSTR_RXY_RRRD },
1137  { "sly", 0x5f, INSTR_RXY_RRRD },
1138  { "sthy", 0x70, INSTR_RXY_RRRD },
1139  { "lay", 0x71, INSTR_RXY_RRRD },
1140  { "stcy", 0x72, INSTR_RXY_RRRD },
1141  { "icy", 0x73, INSTR_RXY_RRRD },
1142  { "lb", 0x76, INSTR_RXY_RRRD },
1143  { "lgb", 0x77, INSTR_RXY_RRRD },
1144  { "lhy", 0x78, INSTR_RXY_RRRD },
1145  { "chy", 0x79, INSTR_RXY_RRRD },
1146  { "ahy", 0x7a, INSTR_RXY_RRRD },
1147  { "shy", 0x7b, INSTR_RXY_RRRD },
1148  { "ng", 0x80, INSTR_RXY_RRRD },
1149  { "og", 0x81, INSTR_RXY_RRRD },
1150  { "xg", 0x82, INSTR_RXY_RRRD },
1151  { "mlg", 0x86, INSTR_RXY_RRRD },
1152  { "dlg", 0x87, INSTR_RXY_RRRD },
1153  { "alcg", 0x88, INSTR_RXY_RRRD },
1154  { "slbg", 0x89, INSTR_RXY_RRRD },
1155  { "stpq", 0x8e, INSTR_RXY_RRRD },
1156  { "lpq", 0x8f, INSTR_RXY_RRRD },
1157  { "llgc", 0x90, INSTR_RXY_RRRD },
1158  { "llgh", 0x91, INSTR_RXY_RRRD },
1159  { "llc", 0x94, INSTR_RXY_RRRD },
1160  { "llh", 0x95, INSTR_RXY_RRRD },
1161  { "cgh", 0x34, INSTR_RXY_RRRD },
1162  { "laey", 0x75, INSTR_RXY_RRRD },
1163  { "ltgf", 0x32, INSTR_RXY_RRRD },
1164  { "mfy", 0x5c, INSTR_RXY_RRRD },
1165  { "mhy", 0x7c, INSTR_RXY_RRRD },
1166  { "pfd", 0x36, INSTR_RXY_URRD },
1167  { "lbh", 0xc0, INSTR_RXY_RRRD },
1168  { "llch", 0xc2, INSTR_RXY_RRRD },
1169  { "stch", 0xc3, INSTR_RXY_RRRD },
1170  { "lhh", 0xc4, INSTR_RXY_RRRD },
1171  { "llhh", 0xc6, INSTR_RXY_RRRD },
1172  { "sthh", 0xc7, INSTR_RXY_RRRD },
1173  { "lfh", 0xca, INSTR_RXY_RRRD },
1174  { "stfh", 0xcb, INSTR_RXY_RRRD },
1175  { "chf", 0xcd, INSTR_RXY_RRRD },
1176  { "clhf", 0xcf, INSTR_RXY_RRRD },
1177  { "ntstg", 0x25, INSTR_RXY_RRRD },
1178 #endif
1179  { "lrv", 0x1e, INSTR_RXY_RRRD },
1180  { "lrvh", 0x1f, INSTR_RXY_RRRD },
1181  { "strv", 0x3e, INSTR_RXY_RRRD },
1182  { "ml", 0x96, INSTR_RXY_RRRD },
1183  { "dl", 0x97, INSTR_RXY_RRRD },
1184  { "alc", 0x98, INSTR_RXY_RRRD },
1185  { "slb", 0x99, INSTR_RXY_RRRD },
1186  { "", 0, INSTR_INVALID }
1187 };
1188 
1189 static struct insn opcode_e5[] = {
1190 #ifdef CONFIG_64BIT
1191  { "strag", 0x02, INSTR_SSE_RDRD },
1192  { "chhsi", 0x54, INSTR_SIL_RDI },
1193  { "chsi", 0x5c, INSTR_SIL_RDI },
1194  { "cghsi", 0x58, INSTR_SIL_RDI },
1195  { { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU },
1196  { { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU },
1197  { { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU },
1198  { "mvhhi", 0x44, INSTR_SIL_RDI },
1199  { "mvhi", 0x4c, INSTR_SIL_RDI },
1200  { "mvghi", 0x48, INSTR_SIL_RDI },
1201  { { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU },
1202  { { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU },
1203 #endif
1204  { "lasp", 0x00, INSTR_SSE_RDRD },
1205  { "tprot", 0x01, INSTR_SSE_RDRD },
1206  { "mvcsk", 0x0e, INSTR_SSE_RDRD },
1207  { "mvcdk", 0x0f, INSTR_SSE_RDRD },
1208  { "", 0, INSTR_INVALID }
1209 };
1210 
1211 static struct insn opcode_eb[] = {
1212 #ifdef CONFIG_64BIT
1213  { "lmg", 0x04, INSTR_RSY_RRRD },
1214  { "srag", 0x0a, INSTR_RSY_RRRD },
1215  { "slag", 0x0b, INSTR_RSY_RRRD },
1216  { "srlg", 0x0c, INSTR_RSY_RRRD },
1217  { "sllg", 0x0d, INSTR_RSY_RRRD },
1218  { "tracg", 0x0f, INSTR_RSY_RRRD },
1219  { "csy", 0x14, INSTR_RSY_RRRD },
1220  { "rllg", 0x1c, INSTR_RSY_RRRD },
1221  { "clmh", 0x20, INSTR_RSY_RURD },
1222  { "clmy", 0x21, INSTR_RSY_RURD },
1223  { "stmg", 0x24, INSTR_RSY_RRRD },
1224  { "stctg", 0x25, INSTR_RSY_CCRD },
1225  { "stmh", 0x26, INSTR_RSY_RRRD },
1226  { "stcmh", 0x2c, INSTR_RSY_RURD },
1227  { "stcmy", 0x2d, INSTR_RSY_RURD },
1228  { "lctlg", 0x2f, INSTR_RSY_CCRD },
1229  { "csg", 0x30, INSTR_RSY_RRRD },
1230  { "cdsy", 0x31, INSTR_RSY_RRRD },
1231  { "cdsg", 0x3e, INSTR_RSY_RRRD },
1232  { "bxhg", 0x44, INSTR_RSY_RRRD },
1233  { "bxleg", 0x45, INSTR_RSY_RRRD },
1234  { "tmy", 0x51, INSTR_SIY_URD },
1235  { "mviy", 0x52, INSTR_SIY_URD },
1236  { "niy", 0x54, INSTR_SIY_URD },
1237  { "cliy", 0x55, INSTR_SIY_URD },
1238  { "oiy", 0x56, INSTR_SIY_URD },
1239  { "xiy", 0x57, INSTR_SIY_URD },
1240  { "lric", 0x60, INSTR_RSY_RDRM },
1241  { "stric", 0x61, INSTR_RSY_RDRM },
1242  { "mric", 0x62, INSTR_RSY_RDRM },
1243  { "icmh", 0x80, INSTR_RSE_RURD },
1244  { "icmh", 0x80, INSTR_RSY_RURD },
1245  { "icmy", 0x81, INSTR_RSY_RURD },
1246  { "clclu", 0x8f, INSTR_RSY_RRRD },
1247  { "stmy", 0x90, INSTR_RSY_RRRD },
1248  { "lmh", 0x96, INSTR_RSY_RRRD },
1249  { "lmy", 0x98, INSTR_RSY_RRRD },
1250  { "lamy", 0x9a, INSTR_RSY_AARD },
1251  { "stamy", 0x9b, INSTR_RSY_AARD },
1252  { "asi", 0x6a, INSTR_SIY_IRD },
1253  { "agsi", 0x7a, INSTR_SIY_IRD },
1254  { "alsi", 0x6e, INSTR_SIY_IRD },
1255  { "algsi", 0x7e, INSTR_SIY_IRD },
1256  { "ecag", 0x4c, INSTR_RSY_RRRD },
1257  { "srak", 0xdc, INSTR_RSY_RRRD },
1258  { "slak", 0xdd, INSTR_RSY_RRRD },
1259  { "srlk", 0xde, INSTR_RSY_RRRD },
1260  { "sllk", 0xdf, INSTR_RSY_RRRD },
1261  { "locg", 0xe2, INSTR_RSY_RDRM },
1262  { "stocg", 0xe3, INSTR_RSY_RDRM },
1263  { "lang", 0xe4, INSTR_RSY_RRRD },
1264  { "laog", 0xe6, INSTR_RSY_RRRD },
1265  { "laxg", 0xe7, INSTR_RSY_RRRD },
1266  { "laag", 0xe8, INSTR_RSY_RRRD },
1267  { "laalg", 0xea, INSTR_RSY_RRRD },
1268  { "loc", 0xf2, INSTR_RSY_RDRM },
1269  { "stoc", 0xf3, INSTR_RSY_RDRM },
1270  { "lan", 0xf4, INSTR_RSY_RRRD },
1271  { "lao", 0xf6, INSTR_RSY_RRRD },
1272  { "lax", 0xf7, INSTR_RSY_RRRD },
1273  { "laa", 0xf8, INSTR_RSY_RRRD },
1274  { "laal", 0xfa, INSTR_RSY_RRRD },
1275 #endif
1276  { "rll", 0x1d, INSTR_RSY_RRRD },
1277  { "mvclu", 0x8e, INSTR_RSY_RRRD },
1278  { "tp", 0xc0, INSTR_RSL_R0RD },
1279  { "", 0, INSTR_INVALID }
1280 };
1281 
1282 static struct insn opcode_ec[] = {
1283 #ifdef CONFIG_64BIT
1284  { "brxhg", 0x44, INSTR_RIE_RRP },
1285  { "brxlg", 0x45, INSTR_RIE_RRP },
1286  { "crb", 0xf6, INSTR_RRS_RRRDU },
1287  { "cgrb", 0xe4, INSTR_RRS_RRRDU },
1288  { "crj", 0x76, INSTR_RIE_RRPU },
1289  { "cgrj", 0x64, INSTR_RIE_RRPU },
1290  { "cib", 0xfe, INSTR_RIS_RURDI },
1291  { "cgib", 0xfc, INSTR_RIS_RURDI },
1292  { "cij", 0x7e, INSTR_RIE_RUPI },
1293  { "cgij", 0x7c, INSTR_RIE_RUPI },
1294  { "cit", 0x72, INSTR_RIE_R0IU },
1295  { "cgit", 0x70, INSTR_RIE_R0IU },
1296  { "clrb", 0xf7, INSTR_RRS_RRRDU },
1297  { "clgrb", 0xe5, INSTR_RRS_RRRDU },
1298  { "clrj", 0x77, INSTR_RIE_RRPU },
1299  { "clgrj", 0x65, INSTR_RIE_RRPU },
1300  { "clib", 0xff, INSTR_RIS_RURDU },
1301  { "clgib", 0xfd, INSTR_RIS_RURDU },
1302  { "clij", 0x7f, INSTR_RIE_RUPU },
1303  { "clgij", 0x7d, INSTR_RIE_RUPU },
1304  { "clfit", 0x73, INSTR_RIE_R0UU },
1305  { "clgit", 0x71, INSTR_RIE_R0UU },
1306  { "rnsbg", 0x54, INSTR_RIE_RRUUU },
1307  { "rxsbg", 0x57, INSTR_RIE_RRUUU },
1308  { "rosbg", 0x56, INSTR_RIE_RRUUU },
1309  { "risbg", 0x55, INSTR_RIE_RRUUU },
1310  { { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU },
1311  { { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU },
1312  { "ahik", 0xd8, INSTR_RIE_RRI0 },
1313  { "aghik", 0xd9, INSTR_RIE_RRI0 },
1314  { { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 },
1315  { { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 },
1316 #endif
1317  { "", 0, INSTR_INVALID }
1318 };
1319 
1320 static struct insn opcode_ed[] = {
1321 #ifdef CONFIG_64BIT
1322  { "mayl", 0x38, INSTR_RXF_FRRDF },
1323  { "myl", 0x39, INSTR_RXF_FRRDF },
1324  { "may", 0x3a, INSTR_RXF_FRRDF },
1325  { "my", 0x3b, INSTR_RXF_FRRDF },
1326  { "mayh", 0x3c, INSTR_RXF_FRRDF },
1327  { "myh", 0x3d, INSTR_RXF_FRRDF },
1328  { "ley", 0x64, INSTR_RXY_FRRD },
1329  { "ldy", 0x65, INSTR_RXY_FRRD },
1330  { "stey", 0x66, INSTR_RXY_FRRD },
1331  { "stdy", 0x67, INSTR_RXY_FRRD },
1332  { "sldt", 0x40, INSTR_RXF_FRRDF },
1333  { "slxt", 0x48, INSTR_RXF_FRRDF },
1334  { "srdt", 0x41, INSTR_RXF_FRRDF },
1335  { "srxt", 0x49, INSTR_RXF_FRRDF },
1336  { "tdcet", 0x50, INSTR_RXE_FRRD },
1337  { "tdcdt", 0x54, INSTR_RXE_FRRD },
1338  { "tdcxt", 0x58, INSTR_RXE_FRRD },
1339  { "tdget", 0x51, INSTR_RXE_FRRD },
1340  { "tdgdt", 0x55, INSTR_RXE_FRRD },
1341  { "tdgxt", 0x59, INSTR_RXE_FRRD },
1342 #endif
1343  { "ldeb", 0x04, INSTR_RXE_FRRD },
1344  { "lxdb", 0x05, INSTR_RXE_FRRD },
1345  { "lxeb", 0x06, INSTR_RXE_FRRD },
1346  { "mxdb", 0x07, INSTR_RXE_FRRD },
1347  { "keb", 0x08, INSTR_RXE_FRRD },
1348  { "ceb", 0x09, INSTR_RXE_FRRD },
1349  { "aeb", 0x0a, INSTR_RXE_FRRD },
1350  { "seb", 0x0b, INSTR_RXE_FRRD },
1351  { "mdeb", 0x0c, INSTR_RXE_FRRD },
1352  { "deb", 0x0d, INSTR_RXE_FRRD },
1353  { "maeb", 0x0e, INSTR_RXF_FRRDF },
1354  { "mseb", 0x0f, INSTR_RXF_FRRDF },
1355  { "tceb", 0x10, INSTR_RXE_FRRD },
1356  { "tcdb", 0x11, INSTR_RXE_FRRD },
1357  { "tcxb", 0x12, INSTR_RXE_FRRD },
1358  { "sqeb", 0x14, INSTR_RXE_FRRD },
1359  { "sqdb", 0x15, INSTR_RXE_FRRD },
1360  { "meeb", 0x17, INSTR_RXE_FRRD },
1361  { "kdb", 0x18, INSTR_RXE_FRRD },
1362  { "cdb", 0x19, INSTR_RXE_FRRD },
1363  { "adb", 0x1a, INSTR_RXE_FRRD },
1364  { "sdb", 0x1b, INSTR_RXE_FRRD },
1365  { "mdb", 0x1c, INSTR_RXE_FRRD },
1366  { "ddb", 0x1d, INSTR_RXE_FRRD },
1367  { "madb", 0x1e, INSTR_RXF_FRRDF },
1368  { "msdb", 0x1f, INSTR_RXF_FRRDF },
1369  { "lde", 0x24, INSTR_RXE_FRRD },
1370  { "lxd", 0x25, INSTR_RXE_FRRD },
1371  { "lxe", 0x26, INSTR_RXE_FRRD },
1372  { "mae", 0x2e, INSTR_RXF_FRRDF },
1373  { "mse", 0x2f, INSTR_RXF_FRRDF },
1374  { "sqe", 0x34, INSTR_RXE_FRRD },
1375  { "sqd", 0x35, INSTR_RXE_FRRD },
1376  { "mee", 0x37, INSTR_RXE_FRRD },
1377  { "mad", 0x3e, INSTR_RXF_FRRDF },
1378  { "msd", 0x3f, INSTR_RXF_FRRDF },
1379  { "", 0, INSTR_INVALID }
1380 };
1381 
1382 /* Extracts an operand value from an instruction. */
1383 static unsigned int extract_operand(unsigned char *code,
1384  const struct operand *operand)
1385 {
1386  unsigned int val;
1387  int bits;
1388 
1389  /* Extract fragments of the operand byte for byte. */
1390  code += operand->shift / 8;
1391  bits = (operand->shift & 7) + operand->bits;
1392  val = 0;
1393  do {
1394  val <<= 8;
1395  val |= (unsigned int) *code++;
1396  bits -= 8;
1397  } while (bits > 0);
1398  val >>= -bits;
1399  val &= ((1U << (operand->bits - 1)) << 1) - 1;
1400 
1401  /* Check for special long displacement case. */
1402  if (operand->bits == 20 && operand->shift == 20)
1403  val = (val & 0xff) << 12 | (val & 0xfff00) >> 8;
1404 
1405  /* Sign extend value if the operand is signed or pc relative. */
1406  if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) &&
1407  (val & (1U << (operand->bits - 1))))
1408  val |= (-1U << (operand->bits - 1)) << 1;
1409 
1410  /* Double value if the operand is pc relative. */
1411  if (operand->flags & OPERAND_PCREL)
1412  val <<= 1;
1413 
1414  /* Length x in an instructions has real length x + 1. */
1415  if (operand->flags & OPERAND_LENGTH)
1416  val++;
1417  return val;
1418 }
1419 
1420 static inline int insn_length(unsigned char code)
1421 {
1422  return ((((int) code + 64) >> 7) + 1) << 1;
1423 }
1424 
1425 static struct insn *find_insn(unsigned char *code)
1426 {
1427  unsigned char opfrag = code[1];
1428  unsigned char opmask;
1429  struct insn *table;
1430 
1431  switch (code[0]) {
1432  case 0x01:
1433  table = opcode_01;
1434  break;
1435  case 0xa5:
1436  table = opcode_a5;
1437  break;
1438  case 0xa7:
1439  table = opcode_a7;
1440  break;
1441  case 0xaa:
1442  table = opcode_aa;
1443  break;
1444  case 0xb2:
1445  table = opcode_b2;
1446  break;
1447  case 0xb3:
1448  table = opcode_b3;
1449  break;
1450  case 0xb9:
1451  table = opcode_b9;
1452  break;
1453  case 0xc0:
1454  table = opcode_c0;
1455  break;
1456  case 0xc2:
1457  table = opcode_c2;
1458  break;
1459  case 0xc4:
1460  table = opcode_c4;
1461  break;
1462  case 0xc6:
1463  table = opcode_c6;
1464  break;
1465  case 0xc8:
1466  table = opcode_c8;
1467  break;
1468  case 0xcc:
1469  table = opcode_cc;
1470  break;
1471  case 0xe3:
1472  table = opcode_e3;
1473  opfrag = code[5];
1474  break;
1475  case 0xe5:
1476  table = opcode_e5;
1477  break;
1478  case 0xeb:
1479  table = opcode_eb;
1480  opfrag = code[5];
1481  break;
1482  case 0xec:
1483  table = opcode_ec;
1484  opfrag = code[5];
1485  break;
1486  case 0xed:
1487  table = opcode_ed;
1488  opfrag = code[5];
1489  break;
1490  default:
1491  table = opcode;
1492  opfrag = code[0];
1493  break;
1494  }
1495  while (table->format != INSTR_INVALID) {
1496  opmask = formats[table->format][0];
1497  if (table->opfrag == (opfrag & opmask))
1498  return table;
1499  table++;
1500  }
1501  return NULL;
1502 }
1503 
1515 int insn_to_mnemonic(unsigned char *instruction, char buf[8])
1516 {
1517  struct insn *insn;
1518 
1519  insn = find_insn(instruction);
1520  if (!insn)
1521  return -ENOENT;
1522  if (insn->name[0] == '\0')
1523  snprintf(buf, sizeof(buf), "%s",
1524  long_insn_name[(int) insn->name[1]]);
1525  else
1526  snprintf(buf, sizeof(buf), "%.5s", insn->name);
1527  return 0;
1528 }
1529 EXPORT_SYMBOL_GPL(insn_to_mnemonic);
1530 
1531 static int print_insn(char *buffer, unsigned char *code, unsigned long addr)
1532 {
1533  struct insn *insn;
1534  const unsigned char *ops;
1535  const struct operand *operand;
1536  unsigned int value;
1537  char separator;
1538  char *ptr;
1539  int i;
1540 
1541  ptr = buffer;
1542  insn = find_insn(code);
1543  if (insn) {
1544  if (insn->name[0] == '\0')
1545  ptr += sprintf(ptr, "%s\t",
1546  long_insn_name[(int) insn->name[1]]);
1547  else
1548  ptr += sprintf(ptr, "%.5s\t", insn->name);
1549  /* Extract the operands. */
1550  separator = 0;
1551  for (ops = formats[insn->format] + 1, i = 0;
1552  *ops != 0 && i < 6; ops++, i++) {
1553  operand = operands + *ops;
1554  value = extract_operand(code, operand);
1555  if ((operand->flags & OPERAND_INDEX) && value == 0)
1556  continue;
1557  if ((operand->flags & OPERAND_BASE) &&
1558  value == 0 && separator == '(') {
1559  separator = ',';
1560  continue;
1561  }
1562  if (separator)
1563  ptr += sprintf(ptr, "%c", separator);
1564  if (operand->flags & OPERAND_GPR)
1565  ptr += sprintf(ptr, "%%r%i", value);
1566  else if (operand->flags & OPERAND_FPR)
1567  ptr += sprintf(ptr, "%%f%i", value);
1568  else if (operand->flags & OPERAND_AR)
1569  ptr += sprintf(ptr, "%%a%i", value);
1570  else if (operand->flags & OPERAND_CR)
1571  ptr += sprintf(ptr, "%%c%i", value);
1572  else if (operand->flags & OPERAND_PCREL)
1573  ptr += sprintf(ptr, "%lx", (signed int) value
1574  + addr);
1575  else if (operand->flags & OPERAND_SIGNED)
1576  ptr += sprintf(ptr, "%i", value);
1577  else
1578  ptr += sprintf(ptr, "%u", value);
1579  if (operand->flags & OPERAND_DISP)
1580  separator = '(';
1581  else if (operand->flags & OPERAND_BASE) {
1582  ptr += sprintf(ptr, ")");
1583  separator = ',';
1584  } else
1585  separator = ',';
1586  }
1587  } else
1588  ptr += sprintf(ptr, "unknown");
1589  return (int) (ptr - buffer);
1590 }
1591 
1592 void show_code(struct pt_regs *regs)
1593 {
1594  char *mode = user_mode(regs) ? "User" : "Krnl";
1595  unsigned char code[64];
1596  char buffer[64], *ptr;
1597  mm_segment_t old_fs;
1598  unsigned long addr;
1599  int start, end, opsize, hops, i;
1600 
1601  /* Get a snapshot of the 64 bytes surrounding the fault address. */
1602  old_fs = get_fs();
1603  set_fs(user_mode(regs) ? USER_DS : KERNEL_DS);
1604  for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) {
1605  addr = regs->psw.addr - 34 + start;
1606  if (__copy_from_user(code + start - 2,
1607  (char __user *) addr, 2))
1608  break;
1609  }
1610  for (end = 32; end < 64; end += 2) {
1611  addr = regs->psw.addr + end - 32;
1612  if (__copy_from_user(code + end,
1613  (char __user *) addr, 2))
1614  break;
1615  }
1616  set_fs(old_fs);
1617  /* Code snapshot useable ? */
1618  if ((regs->psw.addr & 1) || start >= end) {
1619  printk("%s Code: Bad PSW.\n", mode);
1620  return;
1621  }
1622  /* Find a starting point for the disassembly. */
1623  while (start < 32) {
1624  for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) {
1625  if (!find_insn(code + start + i))
1626  break;
1627  i += insn_length(code[start + i]);
1628  }
1629  if (start + i == 32)
1630  /* Looks good, sequence ends at PSW. */
1631  break;
1632  start += 2;
1633  }
1634  /* Decode the instructions. */
1635  ptr = buffer;
1636  ptr += sprintf(ptr, "%s Code:", mode);
1637  hops = 0;
1638  while (start < end && hops < 8) {
1639  opsize = insn_length(code[start]);
1640  if (start + opsize == 32)
1641  *ptr++ = '#';
1642  else if (start == 32)
1643  *ptr++ = '>';
1644  else
1645  *ptr++ = ' ';
1646  addr = regs->psw.addr + start - 32;
1647  ptr += sprintf(ptr, ONELONG, addr);
1648  if (start + opsize >= end)
1649  break;
1650  for (i = 0; i < opsize; i++)
1651  ptr += sprintf(ptr, "%02x", code[start + i]);
1652  *ptr++ = '\t';
1653  if (i < 6)
1654  *ptr++ = '\t';
1655  ptr += print_insn(ptr, code + start, addr);
1656  start += opsize;
1657  printk(buffer);
1658  ptr = buffer;
1659  ptr += sprintf(ptr, "\n ");
1660  hops++;
1661  }
1662  printk("\n");
1663 }
1664 
1665 void print_fn_code(unsigned char *code, unsigned long len)
1666 {
1667  char buffer[64], *ptr;
1668  int opsize, i;
1669 
1670  while (len) {
1671  ptr = buffer;
1672  opsize = insn_length(*code);
1673  ptr += sprintf(ptr, "%p: ", code);
1674  for (i = 0; i < opsize; i++)
1675  ptr += sprintf(ptr, "%02x", code[i]);
1676  *ptr++ = '\t';
1677  if (i < 4)
1678  *ptr++ = '\t';
1679  ptr += print_insn(ptr, code, (unsigned long) code);
1680  *ptr++ = '\n';
1681  *ptr++ = 0;
1682  printk(buffer);
1683  code += opsize;
1684  len -= opsize;
1685  }
1686 }
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