dpll3xxx.c File Reference

#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clkdev.h>
#include <plat/clock.h>
#include "soc.h"
#include "clock.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

Go to the source code of this file.

Macros
#define	DPLL_AUTOIDLE_DISABLE   0x0
#define	DPLL_AUTOIDLE_LOW_POWER_STOP   0x1
#define	MAX_DPLL_WAIT_TRIES   1000000

Functions
unsigned long	omap3_dpll_recalc (struct clk *clk)
int	omap3_noncore_dpll_enable (struct clk *clk)
void	omap3_noncore_dpll_disable (struct clk *clk)
int	omap3_noncore_dpll_set_rate (struct clk *clk, unsigned long rate)
u32	omap3_dpll_autoidle_read (struct clk *clk)
void	omap3_dpll_allow_idle (struct clk *clk)
void	omap3_dpll_deny_idle (struct clk *clk)
unsigned long	omap3_clkoutx2_recalc (struct clk *clk)

Variables
struct clkops	clkops_omap3_noncore_dpll_ops
struct clkops	clkops_omap3_core_dpll_ops

Macro Definition Documentation

#define DPLL_AUTOIDLE_DISABLE   0x0

Definition at line 39 of file dpll3xxx.c.

#define DPLL_AUTOIDLE_LOW_POWER_STOP   0x1

Definition at line 40 of file dpll3xxx.c.

#define MAX_DPLL_WAIT_TRIES   1000000

Definition at line 42 of file dpll3xxx.c.

Function Documentation

unsigned long omap3_clkoutx2_recalc

(

struct clk *

clk

)

omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate : DPLL output struct clk

Using parent clock DPLL data, look up DPLL state. If locked, set our rate to the dpll_clk * 2; otherwise, just use dpll_clk.

Definition at line 620 of file dpll3xxx.c.

void omap3_dpll_allow_idle

(

struct clk *

clk

)

omap3_dpll_allow_idle - enable DPLL autoidle bits : struct clk * of the DPLL to operate on

Enable DPLL automatic idle control. This automatic idle mode switching takes effect only when the DPLL is locked, at least on OMAP3430. The DPLL will enter low-power stop when its downstream clocks are gated. No return value.

Definition at line 554 of file dpll3xxx.c.

u32 omap3_dpll_autoidle_read

(

struct clk *

clk

)

omap3_dpll_autoidle_read - read a DPLL's autoidle bits : struct clk * of the DPLL to read

Return the DPLL's autoidle bits, shifted down to bit 0. Returns -EINVAL if passed a null pointer or if the struct clk does not appear to refer to a DPLL.

Definition at line 525 of file dpll3xxx.c.

void omap3_dpll_deny_idle

(

struct clk *

clk

)

omap3_dpll_deny_idle - prevent DPLL from automatically idling : struct clk * of the DPLL to operate on

Disable DPLL automatic idle control. No return value.

Definition at line 588 of file dpll3xxx.c.

unsigned long omap3_dpll_recalc

(

struct clk *

clk

)

omap3_dpll_recalc - recalculate DPLL rate : DPLL struct clk

Recalculate and propagate the DPLL rate.

Definition at line 360 of file dpll3xxx.c.

void omap3_noncore_dpll_disable

(

struct clk *

clk

)

omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop : pointer to a DPLL struct clk

Instructs a non-CORE DPLL to enter low-power stop. This function is intended for use in struct clkops. No return value.

Definition at line 418 of file dpll3xxx.c.

int omap3_noncore_dpll_enable

(

struct clk *

clk

)

omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode : pointer to a DPLL struct clk

Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. The choice of modes depends on the DPLL's programmed rate: if it is the same as the DPLL's parent clock, it will enter bypass; otherwise, it will enter lock. This code will wait for the DPLL to indicate readiness before returning, unless the DPLL takes too long to enter the target state. Intended to be used as the struct clk's enable function. If DPLL3 was passed in, or the DPLL does not support low-power stop, or if the DPLL took too long to enter bypass or lock, return -EINVAL; otherwise, return 0.

Definition at line 381 of file dpll3xxx.c.

int omap3_noncore_dpll_set_rate	(	struct clk *	clk,
		unsigned long	rate
	)

omap3_noncore_dpll_set_rate - set non-core DPLL rate : struct clk * of DPLL to set : rounded target rate

Set the DPLL CLKOUT to the target rate. If the DPLL can enter low-power bypass, and the target rate is the bypass source clock rate, then configure the DPLL for bypass. Otherwise, round the target rate if it hasn't been done already, then program and lock the DPLL. Returns -EINVAL upon error, or 0 upon success.

Definition at line 437 of file dpll3xxx.c.

Variable Documentation

struct clkops clkops_omap3_core_dpll_ops

Initial value:

= {
    .allow_idle = omap3_dpll_allow_idle,
    .deny_idle  = omap3_dpll_deny_idle,
}

Definition at line 662 of file dpll3xxx.c.

struct clkops clkops_omap3_noncore_dpll_ops

Initial value:

= {
    .enable     = omap3_noncore_dpll_enable,
    .disable    = omap3_noncore_dpll_disable,
    .allow_idle = omap3_dpll_allow_idle,
    .deny_idle  = omap3_dpll_deny_idle,
}

Definition at line 655 of file dpll3xxx.c.