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| #define | DW_MMC_240A 0x240a |
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| #define | SDMMC_CTRL 0x000 |
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| #define | SDMMC_PWREN 0x004 |
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| #define | SDMMC_CLKDIV 0x008 |
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| #define | SDMMC_CLKSRC 0x00c |
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| #define | SDMMC_CLKENA 0x010 |
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| #define | SDMMC_TMOUT 0x014 |
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| #define | SDMMC_CTYPE 0x018 |
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| #define | SDMMC_BLKSIZ 0x01c |
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| #define | SDMMC_BYTCNT 0x020 |
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| #define | SDMMC_INTMASK 0x024 |
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| #define | SDMMC_CMDARG 0x028 |
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| #define | SDMMC_CMD 0x02c |
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| #define | SDMMC_RESP0 0x030 |
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| #define | SDMMC_RESP1 0x034 |
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| #define | SDMMC_RESP2 0x038 |
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| #define | SDMMC_RESP3 0x03c |
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| #define | SDMMC_MINTSTS 0x040 |
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| #define | SDMMC_RINTSTS 0x044 |
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| #define | SDMMC_STATUS 0x048 |
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| #define | SDMMC_FIFOTH 0x04c |
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| #define | SDMMC_CDETECT 0x050 |
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| #define | SDMMC_WRTPRT 0x054 |
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| #define | SDMMC_GPIO 0x058 |
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| #define | SDMMC_TCBCNT 0x05c |
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| #define | SDMMC_TBBCNT 0x060 |
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| #define | SDMMC_DEBNCE 0x064 |
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| #define | SDMMC_USRID 0x068 |
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| #define | SDMMC_VERID 0x06c |
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| #define | SDMMC_HCON 0x070 |
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| #define | SDMMC_UHS_REG 0x074 |
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| #define | SDMMC_BMOD 0x080 |
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| #define | SDMMC_PLDMND 0x084 |
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| #define | SDMMC_DBADDR 0x088 |
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| #define | SDMMC_IDSTS 0x08c |
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| #define | SDMMC_IDINTEN 0x090 |
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| #define | SDMMC_DSCADDR 0x094 |
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| #define | SDMMC_BUFADDR 0x098 |
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| #define | SDMMC_DATA(x) (x) |
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| #define | DATA_OFFSET 0x100 |
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| #define | DATA_240A_OFFSET 0x200 |
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| #define | _SBF(f, v) ((v) << (f)) |
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| #define | SDMMC_CTRL_USE_IDMAC BIT(25) |
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| #define | SDMMC_CTRL_CEATA_INT_EN BIT(11) |
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| #define | SDMMC_CTRL_SEND_AS_CCSD BIT(10) |
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| #define | SDMMC_CTRL_SEND_CCSD BIT(9) |
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| #define | SDMMC_CTRL_ABRT_READ_DATA BIT(8) |
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| #define | SDMMC_CTRL_SEND_IRQ_RESP BIT(7) |
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| #define | SDMMC_CTRL_READ_WAIT BIT(6) |
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| #define | SDMMC_CTRL_DMA_ENABLE BIT(5) |
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| #define | SDMMC_CTRL_INT_ENABLE BIT(4) |
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| #define | SDMMC_CTRL_DMA_RESET BIT(2) |
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| #define | SDMMC_CTRL_FIFO_RESET BIT(1) |
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| #define | SDMMC_CTRL_RESET BIT(0) |
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| #define | SDMMC_CLKEN_LOW_PWR BIT(16) |
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| #define | SDMMC_CLKEN_ENABLE BIT(0) |
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| #define | SDMMC_TMOUT_DATA(n) _SBF(8, (n)) |
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| #define | SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 |
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| #define | SDMMC_TMOUT_RESP(n) ((n) & 0xFF) |
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| #define | SDMMC_TMOUT_RESP_MSK 0xFF |
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| #define | SDMMC_CTYPE_8BIT BIT(16) |
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| #define | SDMMC_CTYPE_4BIT BIT(0) |
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| #define | SDMMC_CTYPE_1BIT 0 |
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| #define | SDMMC_INT_SDIO(n) BIT(16 + (n)) |
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| #define | SDMMC_INT_EBE BIT(15) |
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| #define | SDMMC_INT_ACD BIT(14) |
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| #define | SDMMC_INT_SBE BIT(13) |
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| #define | SDMMC_INT_HLE BIT(12) |
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| #define | SDMMC_INT_FRUN BIT(11) |
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| #define | SDMMC_INT_HTO BIT(10) |
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| #define | SDMMC_INT_DTO BIT(9) |
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| #define | SDMMC_INT_RTO BIT(8) |
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| #define | SDMMC_INT_DCRC BIT(7) |
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| #define | SDMMC_INT_RCRC BIT(6) |
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| #define | SDMMC_INT_RXDR BIT(5) |
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| #define | SDMMC_INT_TXDR BIT(4) |
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| #define | SDMMC_INT_DATA_OVER BIT(3) |
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| #define | SDMMC_INT_CMD_DONE BIT(2) |
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| #define | SDMMC_INT_RESP_ERR BIT(1) |
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| #define | SDMMC_INT_CD BIT(0) |
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| #define | SDMMC_INT_ERROR 0xbfc2 |
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| #define | SDMMC_CMD_START BIT(31) |
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| #define | SDMMC_CMD_CCS_EXP BIT(23) |
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| #define | SDMMC_CMD_CEATA_RD BIT(22) |
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| #define | SDMMC_CMD_UPD_CLK BIT(21) |
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| #define | SDMMC_CMD_INIT BIT(15) |
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| #define | SDMMC_CMD_STOP BIT(14) |
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| #define | SDMMC_CMD_PRV_DAT_WAIT BIT(13) |
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| #define | SDMMC_CMD_SEND_STOP BIT(12) |
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| #define | SDMMC_CMD_STRM_MODE BIT(11) |
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| #define | SDMMC_CMD_DAT_WR BIT(10) |
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| #define | SDMMC_CMD_DAT_EXP BIT(9) |
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| #define | SDMMC_CMD_RESP_CRC BIT(8) |
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| #define | SDMMC_CMD_RESP_LONG BIT(7) |
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| #define | SDMMC_CMD_RESP_EXP BIT(6) |
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| #define | SDMMC_CMD_INDX(n) ((n) & 0x1F) |
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| #define | SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) |
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| #define | SDMMC_IDMAC_INT_AI BIT(9) |
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| #define | SDMMC_IDMAC_INT_NI BIT(8) |
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| #define | SDMMC_IDMAC_INT_CES BIT(5) |
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| #define | SDMMC_IDMAC_INT_DU BIT(4) |
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| #define | SDMMC_IDMAC_INT_FBE BIT(2) |
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| #define | SDMMC_IDMAC_INT_RI BIT(1) |
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| #define | SDMMC_IDMAC_INT_TI BIT(0) |
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| #define | SDMMC_IDMAC_ENABLE BIT(7) |
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| #define | SDMMC_IDMAC_FB BIT(1) |
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| #define | SDMMC_IDMAC_SWRESET BIT(0) |
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| #define | SDMMC_GET_VERID(x) ((x) & 0xFFFF) |
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| #define | mci_readl(dev, reg) __raw_readl((dev)->regs + SDMMC_##reg) |
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| #define | mci_writel(dev, reg, value) __raw_writel((value), (dev)->regs + SDMMC_##reg) |
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| #define | mci_readw(dev, reg) __raw_readw((dev)->regs + SDMMC_##reg) |
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| #define | mci_writew(dev, reg, value) __raw_writew((value), (dev)->regs + SDMMC_##reg) |
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| #define | mci_readq(dev, reg) (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) |
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| #define | mci_writeq(dev, reg, value) (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) |
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1.8.2