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common.h
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1 /*****************************************************************************
2  * *
3  * File: common.h *
4  * $Revision: 1.21 $ *
5  * $Date: 2005/06/22 00:43:25 $ *
6  * Description: *
7  * part of the Chelsio 10Gb Ethernet Driver. *
8  * *
9  * This program is free software; you can redistribute it and/or modify *
10  * it under the terms of the GNU General Public License, version 2, as *
11  * published by the Free Software Foundation. *
12  * *
13  * You should have received a copy of the GNU General Public License along *
14  * with this program; if not, write to the Free Software Foundation, Inc., *
15  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16  * *
17  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20  * *
21  * http://www.chelsio.com *
22  * *
23  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24  * All rights reserved. *
25  * *
26  * Maintainers: [email protected] *
27  * *
28  * Authors: Dimitrios Michailidis <[email protected]> *
29  * Tina Yang <[email protected]> *
30  * Felix Marti <[email protected]> *
31  * Scott Bardone <[email protected]> *
32  * Kurt Ottaway <[email protected]> *
33  * Frank DiMambro <[email protected]> *
34  * *
35  * History: *
36  * *
37  ****************************************************************************/
38 
39 #define pr_fmt(fmt) "cxgb: " fmt
40 
41 #ifndef _CXGB_COMMON_H_
42 #define _CXGB_COMMON_H_
43 
44 #include <linux/module.h>
45 #include <linux/netdevice.h>
46 #include <linux/types.h>
47 #include <linux/delay.h>
48 #include <linux/pci.h>
49 #include <linux/ethtool.h>
50 #include <linux/if_vlan.h>
51 #include <linux/mdio.h>
52 #include <linux/crc32.h>
53 #include <linux/init.h>
54 #include <linux/slab.h>
55 #include <asm/io.h>
56 #include <linux/pci_ids.h>
57 
58 #define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
59 #define DRV_NAME "cxgb"
60 #define DRV_VERSION "2.2"
61 
62 #define CH_DEVICE(devid, ssid, idx) \
63  { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
64 
65 #define SUPPORTED_PAUSE (1 << 13)
66 #define SUPPORTED_LOOPBACK (1 << 15)
67 
68 #define ADVERTISED_PAUSE (1 << 13)
69 #define ADVERTISED_ASYM_PAUSE (1 << 14)
70 
71 typedef struct adapter adapter_t;
72 
73 struct t1_rx_mode {
74  struct net_device *dev;
75 };
76 
77 #define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
78 #define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
79 #define t1_rx_mode_mc_cnt(rm) (netdev_mc_count(rm->dev))
80 #define t1_get_netdev(rm) (rm->dev)
81 
82 #define MAX_NPORTS 4
83 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
84 #define NMTUS 8
85 #define TCB_SIZE 128
86 
87 #define SPEED_INVALID 0xffff
88 #define DUPLEX_INVALID 0xff
89 
90 enum {
91  CHBT_BOARD_N110,
92  CHBT_BOARD_N210,
93  CHBT_BOARD_7500,
94  CHBT_BOARD_8000,
95  CHBT_BOARD_CHT101,
96  CHBT_BOARD_CHT110,
97  CHBT_BOARD_CHT210,
98  CHBT_BOARD_CHT204,
99  CHBT_BOARD_CHT204V,
100  CHBT_BOARD_CHT204E,
101  CHBT_BOARD_CHN204,
102  CHBT_BOARD_COUGAR,
103  CHBT_BOARD_6800,
104  CHBT_BOARD_SIMUL,
105 };
106 
107 enum {
108  CHBT_TERM_FPGA,
109  CHBT_TERM_T1,
110  CHBT_TERM_T2,
111  CHBT_TERM_T3
112 };
113 
114 enum {
115  CHBT_MAC_CHELSIO_A,
116  CHBT_MAC_IXF1010,
117  CHBT_MAC_PM3393,
118  CHBT_MAC_VSC7321,
119  CHBT_MAC_DUMMY
120 };
121 
122 enum {
123  CHBT_PHY_88E1041,
124  CHBT_PHY_88E1111,
125  CHBT_PHY_88X2010,
126  CHBT_PHY_XPAK,
127  CHBT_PHY_MY3126,
128  CHBT_PHY_8244,
129  CHBT_PHY_DUMMY
130 };
131 
132 enum {
133  PAUSE_RX = 1 << 0,
134  PAUSE_TX = 1 << 1,
135  PAUSE_AUTONEG = 1 << 2
136 };
137 
138 /* Revisions of T1 chip */
139 enum {
140  TERM_T1A = 0,
141  TERM_T1B = 1,
142  TERM_T2 = 3
143 };
144 
145 struct sge_params {
146  unsigned int cmdQ_size[2];
147  unsigned int freelQ_size[2];
148  unsigned int large_buf_capacity;
149  unsigned int rx_coalesce_usecs;
150  unsigned int last_rx_coalesce_raw;
151  unsigned int default_rx_coalesce_usecs;
152  unsigned int sample_interval_usecs;
153  unsigned int coalesce_enable;
154  unsigned int polling;
155 };
156 
157 struct chelsio_pci_params {
158  unsigned short speed;
159  unsigned char width;
160  unsigned char is_pcix;
161 };
162 
163 struct tp_params {
164  unsigned int pm_size;
165  unsigned int cm_size;
166  unsigned int pm_rx_base;
167  unsigned int pm_tx_base;
168  unsigned int pm_rx_pg_size;
169  unsigned int pm_tx_pg_size;
170  unsigned int pm_rx_num_pgs;
171  unsigned int pm_tx_num_pgs;
172  unsigned int rx_coalescing_size;
173  unsigned int use_5tuple_mode;
174 };
175 
176 struct mc5_params {
177  unsigned int mode; /* selects MC5 width */
178  unsigned int nservers; /* size of server region */
179  unsigned int nroutes; /* size of routing region */
180 };
181 
182 /* Default MC5 region sizes */
183 #define DEFAULT_SERVER_REGION_LEN 256
184 #define DEFAULT_RT_REGION_LEN 1024
185 
186 struct adapter_params {
187  struct sge_params sge;
188  struct mc5_params mc5;
189  struct tp_params tp;
190  struct chelsio_pci_params pci;
191 
192  const struct board_info *brd_info;
193 
194  unsigned short mtus[NMTUS];
195  unsigned int nports; /* # of ethernet ports */
196  unsigned int stats_update_period;
197  unsigned short chip_revision;
198  unsigned char chip_version;
199  unsigned char is_asic;
200  unsigned char has_msi;
201 };
202 
203 struct link_config {
204  unsigned int supported; /* link capabilities */
205  unsigned int advertising; /* advertised capabilities */
206  unsigned short requested_speed; /* speed user has requested */
207  unsigned short speed; /* actual link speed */
208  unsigned char requested_duplex; /* duplex user has requested */
209  unsigned char duplex; /* actual link duplex */
210  unsigned char requested_fc; /* flow control user has requested */
211  unsigned char fc; /* actual link flow control */
212  unsigned char autoneg; /* autonegotiating? */
213 };
214 
215 struct cmac;
216 struct cphy;
217 
218 struct port_info {
219  struct net_device *dev;
220  struct cmac *mac;
221  struct cphy *phy;
222  struct link_config link_config;
223  struct net_device_stats netstats;
224 };
225 
226 struct sge;
227 struct peespi;
228 
229 struct adapter {
230  u8 __iomem *regs;
231  struct pci_dev *pdev;
232  unsigned long registered_device_map;
233  unsigned long open_device_map;
234  unsigned long flags;
235 
236  const char *name;
237  int msg_enable;
238  u32 mmio_len;
239 
240  struct work_struct ext_intr_handler_task;
241  struct adapter_params params;
242 
243  /* Terminator modules. */
244  struct sge *sge;
245  struct peespi *espi;
246  struct petp *tp;
247 
248  struct napi_struct napi;
249  struct port_info port[MAX_NPORTS];
250  struct delayed_work stats_update_task;
251  struct timer_list stats_update_timer;
252 
253  spinlock_t tpi_lock;
254  spinlock_t work_lock;
255  spinlock_t mac_lock;
256 
257  /* guards async operations */
258  spinlock_t async_lock ____cacheline_aligned;
259  u32 slow_intr_mask;
260  int t1powersave;
261 };
262 
263 enum { /* adapter flags */
264  FULL_INIT_DONE = 1 << 0,
265 };
266 
267 struct mdio_ops;
268 struct gmac;
269 struct gphy;
270 
271 struct board_info {
272  unsigned char board;
273  unsigned char port_number;
274  unsigned long caps;
275  unsigned char chip_term;
276  unsigned char chip_mac;
277  unsigned char chip_phy;
278  unsigned int clock_core;
279  unsigned int clock_mc3;
280  unsigned int clock_mc4;
281  unsigned int espi_nports;
282  unsigned int clock_elmer0;
283  unsigned char mdio_mdien;
284  unsigned char mdio_mdiinv;
285  unsigned char mdio_mdc;
286  unsigned char mdio_phybaseaddr;
287  const struct gmac *gmac;
288  const struct gphy *gphy;
289  const struct mdio_ops *mdio_ops;
290  const char *desc;
291 };
292 
293 static inline int t1_is_asic(const adapter_t *adapter)
294 {
295  return adapter->params.is_asic;
296 }
297 
298 extern const struct pci_device_id t1_pci_tbl[];
299 
300 static inline int adapter_matches_type(const adapter_t *adapter,
301  int version, int revision)
302 {
303  return adapter->params.chip_version == version &&
304  adapter->params.chip_revision == revision;
305 }
306 
307 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
308 #define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
309 
310 /* Returns true if an adapter supports VLAN acceleration and TSO */
311 static inline int vlan_tso_capable(const adapter_t *adapter)
312 {
313  return !t1_is_T1B(adapter);
314 }
315 
316 #define for_each_port(adapter, iter) \
317  for (iter = 0; iter < (adapter)->params.nports; ++iter)
318 
319 #define board_info(adapter) ((adapter)->params.brd_info)
320 #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
321 
322 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
323 {
324  return board_info(adap)->clock_core / 1000000;
325 }
326 
327 extern int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
328 extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
329 extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
330 extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
331 
332 extern void t1_interrupts_enable(adapter_t *adapter);
333 extern void t1_interrupts_disable(adapter_t *adapter);
334 extern void t1_interrupts_clear(adapter_t *adapter);
335 extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
336 extern void t1_elmer0_ext_intr(adapter_t *adapter);
337 extern int t1_slow_intr_handler(adapter_t *adapter);
338 
339 extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
340 extern const struct board_info *t1_get_board_info(unsigned int board_id);
341 extern const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
342  unsigned short ssid);
343 extern int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
344 extern int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
345  struct adapter_params *p);
346 extern int t1_init_hw_modules(adapter_t *adapter);
347 extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
348 extern void t1_free_sw_modules(adapter_t *adapter);
349 extern void t1_fatal_err(adapter_t *adapter);
350 extern void t1_link_changed(adapter_t *adapter, int port_id);
351 extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
352  int speed, int duplex, int pause);
353 #endif /* _CXGB_COMMON_H_ */
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