Macros
#define	E1000_CTRL 0x00000 /* Device Control - RW */

#define	E1000_STATUS 0x00008 /* Device Status - RO */

#define	E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */

#define	E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */

#define	E1000_EITR(_n) (0x01680 + (0x4 * (_n)))

#define	E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */

#define	E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */

#define	E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */

#define	E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */

#define	E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */

#define	E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */

#define	E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */

#define	E1000_RDBAL(_n)

#define	E1000_RDBAH(_n)

#define	E1000_RDLEN(_n)

#define	E1000_SRRCTL(_n)

#define	E1000_RDH(_n)

#define	E1000_RDT(_n)

#define	E1000_RXDCTL(_n)

#define	E1000_TDBAL(_n)

#define	E1000_TDBAH(_n)

#define	E1000_TDLEN(_n)

#define	E1000_TDH(_n)

#define	E1000_TDT(_n)

#define	E1000_TXDCTL(_n)

#define	E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))

#define	E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))

#define	E1000_RAL(_i)

#define	E1000_RAH(_i)

#define	E1000_VFGPRC 0x00F10

#define	E1000_VFGORC 0x00F18

#define	E1000_VFMPRC 0x00F3C

#define	E1000_VFGPTC 0x00F14

#define	E1000_VFGOTC 0x00F34

#define	E1000_VFGOTLBC 0x00F50

#define	E1000_VFGPTLBC 0x00F44

#define	E1000_VFGORLBC 0x00F48

#define	E1000_VFGPRLBC 0x00F40

#define	E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))

#define	E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))

#define	er32(reg) readl(hw->hw_addr + E1000_##reg)

#define	ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg)

#define	array_er32(reg, offset) readl(hw->hw_addr + E1000_##reg + (offset << 2))

#define	array_ew32(reg, offset, val) writel((val), hw->hw_addr + E1000_##reg + (offset << 2))

#define	e1e_flush() er32(STATUS)

Macro Definition Documentation

#define array_er32	(	reg,
		offset
	)	readl(hw->hw_addr + E1000_##reg + (offset << 2))

Definition at line 102 of file regs.h.

#define array_ew32	(	reg,
		offset,
		val
	)	writel((val), hw->hw_addr + E1000_##reg + (offset << 2))

Definition at line 104 of file regs.h.

#define E1000_CTRL 0x00000 /* Device Control - RW */

Definition at line 31 of file regs.h.

#define E1000_DCA_RXCTRL ( _n ) (0x02814 + (_n << 8))

Definition at line 78 of file regs.h.

#define E1000_DCA_TXCTRL ( _n ) (0x03814 + (_n << 8))

Definition at line 77 of file regs.h.

#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */

Definition at line 39 of file regs.h.

#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */

Definition at line 40 of file regs.h.

#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */

Definition at line 34 of file regs.h.

#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */

Definition at line 36 of file regs.h.

#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */

Definition at line 38 of file regs.h.

#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */

Definition at line 37 of file regs.h.

#define E1000_EITR ( _n ) (0x01680 + (0x4 * (_n)))

Definition at line 35 of file regs.h.

#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */

Definition at line 33 of file regs.h.

#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */

Definition at line 41 of file regs.h.

#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */

Definition at line 42 of file regs.h.

#define E1000_RAH ( _i )

Value:

(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \

(0x054E4 + ((_i - 16) * 8)))

Definition at line 81 of file regs.h.

#define E1000_RAL ( _i )

Value:

(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \

(0x054E0 + ((_i - 16) * 8)))

Definition at line 79 of file regs.h.

#define E1000_RDBAH ( _n )

Value:

((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \

(0x0C004 + ((_n) * 0x40)))

Definition at line 53 of file regs.h.

#define E1000_RDBAL ( _n )

Value:

((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \

(0x0C000 + ((_n) * 0x40)))

Definition at line 51 of file regs.h.

#define E1000_RDH ( _n )

Value:

((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \

(0x0C010 + ((_n) * 0x40)))

Definition at line 59 of file regs.h.

#define E1000_RDLEN ( _n )

Value:

((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \

(0x0C008 + ((_n) * 0x40)))

Definition at line 55 of file regs.h.

#define E1000_RDT ( _n )

Value:

((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \

(0x0C018 + ((_n) * 0x40)))

Definition at line 61 of file regs.h.

#define E1000_RXDCTL ( _n )

Value:

((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \

(0x0C028 + ((_n) * 0x40)))

Definition at line 63 of file regs.h.

#define E1000_SRRCTL ( _n )

Value:

((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \

(0x0C00C + ((_n) * 0x40)))

Definition at line 57 of file regs.h.

#define E1000_STATUS 0x00008 /* Device Status - RO */

Definition at line 32 of file regs.h.

#define E1000_TDBAH ( _n )

Value:

((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \

(0x0E004 + ((_n) * 0x40)))

Definition at line 67 of file regs.h.

#define E1000_TDBAL ( _n )

Value:

((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \

(0x0E000 + ((_n) * 0x40)))

Definition at line 65 of file regs.h.

#define E1000_TDH ( _n )

Value:

((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \

(0x0E010 + ((_n) * 0x40)))

Definition at line 71 of file regs.h.

#define E1000_TDLEN ( _n )

Value:

((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \

(0x0E008 + ((_n) * 0x40)))

Definition at line 69 of file regs.h.

#define E1000_TDT ( _n )

Value:

((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \

(0x0E018 + ((_n) * 0x40)))

Definition at line 73 of file regs.h.

#define E1000_TXDCTL ( _n )

Value:

((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \

(0x0E028 + ((_n) * 0x40)))

Definition at line 75 of file regs.h.

#define E1000_V2PMAILBOX ( _n ) (0x00C40 + (4 * (_n)))

Definition at line 96 of file regs.h.

#define E1000_VFGORC 0x00F18

Definition at line 86 of file regs.h.

#define E1000_VFGORLBC 0x00F48

Definition at line 92 of file regs.h.

#define E1000_VFGOTC 0x00F34

Definition at line 89 of file regs.h.

#define E1000_VFGOTLBC 0x00F50

Definition at line 90 of file regs.h.

#define E1000_VFGPRC 0x00F10

Definition at line 85 of file regs.h.

#define E1000_VFGPRLBC 0x00F40

Definition at line 93 of file regs.h.

#define E1000_VFGPTC 0x00F14

Definition at line 88 of file regs.h.

#define E1000_VFGPTLBC 0x00F44

Definition at line 91 of file regs.h.

#define E1000_VFMPRC 0x00F3C

Definition at line 87 of file regs.h.

#define E1000_VMBMEM ( _n ) (0x00800 + (64 * (_n)))

Definition at line 97 of file regs.h.

#define e1e_flush ( ) er32(STATUS)

Definition at line 106 of file regs.h.

#define er32 ( reg ) readl(hw->hw_addr + E1000_##reg)

Definition at line 100 of file regs.h.

#define ew32	(	reg,
		val
	)	writel((val), hw->hw_addr + E1000_##reg)

Definition at line 101 of file regs.h.

Macros

Macro Definition Documentation