|
| #define | DRV_NAME "epic100" |
| |
| #define | DRV_VERSION "2.1" |
| |
| #define | DRV_RELDATE "Sept 11, 2006" |
| |
| #define | MAX_UNITS 8 /* More are supported, limit only on options */ |
| |
| #define | TX_RING_SIZE 256 |
| |
| #define | TX_QUEUE_LEN 240 /* Limit ring entries actually used. */ |
| |
| #define | RX_RING_SIZE 256 |
| |
| #define | TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc) |
| |
| #define | RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc) |
| |
| #define | TX_TIMEOUT (2*HZ) |
| |
| #define | PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ |
| |
| #define | TX_FIFO_THRESH 256 |
| |
| #define | RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */ |
| |
| #define | EPIC_TOTAL_SIZE 0x100 |
| |
| #define | USE_IO_OPS 1 |
| |
| #define | EPIC_BAR 0 |
| |
| #define | ew16(reg, val) iowrite16(val, ioaddr + (reg)) |
| |
| #define | ew32(reg, val) iowrite32(val, ioaddr + (reg)) |
| |
| #define | er8(reg) ioread8(ioaddr + (reg)) |
| |
| #define | er16(reg) ioread16(ioaddr + (reg)) |
| |
| #define | er32(reg) ioread32(ioaddr + (reg)) |
| |
| #define | EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */ |
| |
| #define | EpicNapiEvent |
| |
| #define | EpicNormalEvent (0x0000ffff & ~EpicNapiEvent) |
| |
| #define | PRIV_ALIGN 15 /* Required alignment mask */ |
| |
| #define | EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ |
| |
| #define | EE_CS 0x02 /* EEPROM chip select. */ |
| |
| #define | EE_DATA_WRITE 0x08 /* EEPROM chip data in. */ |
| |
| #define | EE_WRITE_0 0x01 |
| |
| #define | EE_WRITE_1 0x09 |
| |
| #define | EE_DATA_READ 0x10 /* EEPROM chip data out. */ |
| |
| #define | EE_ENB (0x0001 | EE_CS) |
| |
| #define | eeprom_delay() er32(EECTL) |
| |
| #define | EE_WRITE_CMD (5 << 6) |
| |
| #define | EE_READ64_CMD (6 << 6) |
| |
| #define | EE_READ256_CMD (6 << 8) |
| |
| #define | EE_ERASE_CMD (7 << 6) |
| |
| #define | MII_READOP 1 |
| |
| #define | MII_WRITEOP 2 |
| |
|
| enum | chip_capability_flags {
CanHaveMII =1,
CanHaveMII =1,
HasBrokenTx =2,
AlwaysFDX =4,
FDXOnNoMII =8,
HAS_MII_XCVR,
HAS_CHIP_XCVR,
MII_PWRDWN =1,
TYPE2_INTR =2,
NO_MII =4
} |
| |
| enum | chip_t {
CH_8139 = 0,
CH_8139_K,
CH_8139A,
CH_8139A_G,
CH_8139B,
CH_8130,
CH_8139C,
CH_8100,
CH_8100B_8139D,
CH_8101,
SMSC_83C170_0,
SMSC_83C170,
SMSC_83C175
} |
| |
| enum | epic_registers {
COMMAND =0,
INTSTAT =4,
INTMASK =8,
GENCTL =0x0C,
NVCTL =0x10,
EECTL =0x14,
PCIBurstCnt =0x18,
TEST1 =0x1C,
CRCCNT =0x20,
ALICNT =0x24,
MPCNT =0x28,
MIICtrl =0x30,
MIIData =0x34,
MIICfg =0x38,
LAN0 =64,
MC0 =80,
RxCtrl =96,
TxCtrl =112,
TxSTAT =0x74,
PRxCDAR =0x84,
RxSTAT =0xA4,
EarlyRx =0xB0,
PTxCDAR =0xC4,
TxThresh =0xDC
} |
| |
| enum | IntrStatus {
TxIdle =0x40000,
RxIdle =0x20000,
IntrSummary =0x010000,
PCIBusErr170 =0x7000,
PCIBusErr175 =0x1000,
PhyEvent175 =0x8000,
RxStarted =0x0800,
RxEarlyWarn =0x0400,
CntFull =0x0200,
TxUnderrun =0x0100,
TxEmpty =0x0080,
TxDone =0x0020,
RxError =0x0010,
RxOverflow =0x0008,
RxFull =0x0004,
RxHeader =0x0002,
RxDone =0x0001
} |
| |
| enum | CommandBits {
StopRx =1,
StartRx =2,
TxQueued =4,
RxQueued =8,
StopTxDMA =0x20,
StopRxDMA =0x40,
RestartTx =0x80
} |
| |
| enum | desc_status_bits {
DescOwned = 0x80000000,
DescWholePkt = 0x60000000,
DescEndPkt = 0x40000000,
DescStartPkt = 0x20000000,
DescEndRing = 0x02000000,
DescUseLink = 0x01000000,
RxDescErrorSummary = 0x8000,
RxDescCRCError = 0x0002,
RxDescCollisionSeen = 0x0040,
RxDescFrameTooLong = 0x0080,
RxDescRunt = 0x0800,
RxDescDescErr = 0x4000,
RxWholePkt = 0x00000300,
RxLengthOver2047 = 0x38000010,
DescOwn =0x8000,
DescEndPacket =0x4000,
DescEndRing =0x2000,
LastFrag =0x80000000,
DescIntrOnTx =0x8000,
DescIntrOnDMADone =0x80000000,
DisableAlign = 0x00000001,
DescOwn =0x80000000,
DescMore =0x40000000,
DescIntr =0x20000000,
DescNoCRC =0x10000000,
DescPktOK =0x08000000,
DescSizeMask =0xfff,
DescTxAbort =0x04000000,
DescTxFIFO =0x02000000,
DescTxCarrier =0x01000000,
DescTxDefer =0x00800000,
DescTxExcDefer =0x00400000,
DescTxOOWCol =0x00200000,
DescTxExcColl =0x00100000,
DescTxCollCount =0x000f0000,
DescRxAbort =0x04000000,
DescRxOver =0x02000000,
DescRxDest =0x01800000,
DescRxLong =0x00400000,
DescRxRunt =0x00200000,
DescRxInvalid =0x00100000,
DescRxCRC =0x00080000,
DescRxAlign =0x00040000,
DescRxLoop =0x00020000,
DesRxColl =0x00010000,
DescOwn =0x80000000,
DescEndPacket =0x40000000,
DescEndRing =0x20000000,
DescIntr =0x10000000,
RX_EOP =0x0040,
DescOwn =0x8000,
DescOwn =0x80000000
} |
| |
|
| | MODULE_AUTHOR ("Donald Becker <[email protected]>") |
| |
| | MODULE_DESCRIPTION ("SMC 83c170 EPIC series Ethernet driver") |
| |
| | MODULE_LICENSE ("GPL") |
| |
| | module_param (debug, int, 0) |
| |
| | module_param (rx_copybreak, int, 0) |
| |
| | module_param_array (options, int, NULL, 0) |
| |
| | module_param_array (full_duplex, int, NULL, 0) |
| |
| | MODULE_PARM_DESC (debug,"EPIC/100 debug level (0-5)") |
| |
| | MODULE_PARM_DESC (options,"EPIC/100: Bits 0-3: media type, bit 4: full duplex") |
| |
| | MODULE_PARM_DESC (rx_copybreak,"EPIC/100 copy breakpoint for copy-only-tiny-frames") |
| |
| | MODULE_PARM_DESC (full_duplex,"EPIC/100 full duplex setting(s) (1)") |
| |
| | MODULE_DEVICE_TABLE (pci, epic_pci_tbl) |
| |
| | module_init (epic_init) |
| |
| | module_exit (epic_cleanup) |
| |
1.8.2