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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | ath5k_hw_rx_ctl |
| struct | ath5k_hw_rx_status |
| struct | ath5k_hw_2w_tx_ctl |
| struct | ath5k_hw_4w_tx_ctl |
| struct | ath5k_hw_tx_status |
| struct | ath5k_hw_5210_tx_desc |
| struct | ath5k_hw_5212_tx_desc |
| struct | ath5k_hw_all_rx_desc |
| struct | ath5k_desc |
Enumerations | |
| enum | ath5k_phy_error_code { AR5K_RX_PHY_ERROR_UNDERRUN = 0, AR5K_RX_PHY_ERROR_TIMING = 1, AR5K_RX_PHY_ERROR_PARITY = 2, AR5K_RX_PHY_ERROR_RATE = 3, AR5K_RX_PHY_ERROR_LENGTH = 4, AR5K_RX_PHY_ERROR_RADAR = 5, AR5K_RX_PHY_ERROR_SERVICE = 6, AR5K_RX_PHY_ERROR_TOR = 7, AR5K_RX_PHY_ERROR_OFDM_TIMING = 17, AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY = 18, AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19, AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL = 20, AR5K_RX_PHY_ERROR_OFDM_POWER_DROP = 21, AR5K_RX_PHY_ERROR_OFDM_SERVICE = 22, AR5K_RX_PHY_ERROR_OFDM_RESTART = 23, AR5K_RX_PHY_ERROR_CCK_TIMING = 25, AR5K_RX_PHY_ERROR_CCK_HEADER_CRC = 26, AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL = 27, AR5K_RX_PHY_ERROR_CCK_SERVICE = 30, AR5K_RX_PHY_ERROR_CCK_RESTART = 31 } |
Functions | |
| struct ath5k_hw_rx_ctl | __aligned (4) |
| #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT |
| #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 /* [5210] antenna selection */ |
| #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 /* [5211] antenna selection */ |
| #define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 /* clear destination mask */ |
| #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 /* key is valid */ |
| #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff /* frame length */ |
| #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210 0x1c000000 /* [5210] frame type */ |
| #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210 0x0003f000 /* [5210] header length */ |
| #define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 /* TX interrupt request */ |
| #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET_5210 0x00800000 /* [5210] long packet */ |
| #define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 /* RTS/CTS enable */ |
| #define AR5K_2W_TX_DESC_CTL0_VEOL_5211 0x00800000 /* [5211] virtual end-of-list */ |
| #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 /* tx rate */ |
| #define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff /* data buffer length */ |
| #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX |
| #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 0x0007e000 /* [5210] key table index */ |
| #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211 0x000fe000 /* [5211] key table index */ |
| #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211 0x00700000 /* [5211] frame type */ |
| #define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 /* more desc for this frame */ |
| #define AR5K_2W_TX_DESC_CTL1_NOACK_5211 0x00800000 /* [5211] no ACK */ |
| #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210 0xfff80000 /* [5210] lower 13 bit of duration */ |
| #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 /* TX antenna selection */ |
| #define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 /* clear destination mask */ |
| #define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 /* precede frame with CTS */ |
| #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 /* destination index valid */ |
| #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff /* frame length */ |
| #define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 /* TX interrupt request */ |
| #define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 /* RTS/CTS enable */ |
| #define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 /* virtual end-of-list */ |
| #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 /* transmit power */ |
| #define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff /* data buffer length */ |
| #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 /* length of frame ICV */ |
| #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 /* length of frame IV */ |
| #define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 /* compression processing */ |
| #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX 0x000fe000 /* destination table index */ |
| #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 /* frame type */ |
| #define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 /* more desc for this frame */ |
| #define AR5K_4W_TX_DESC_CTL2_DURATION_UPD_EN 0x00008000 /* frame duration update */ |
| #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff /* RTS/CTS duration */ |
| #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 /* series 0 max attempts */ |
| #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 /* series 1 max attempts */ |
| #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 /* series 2 max attempts */ |
| #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 /* series 3 max attempts */ |
| #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 /* RTS or CTS rate */ |
| #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f /* series 0 tx rate */ |
| #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 /* series 1 tx rate */ |
| #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 /* series 2 tx rate */ |
| #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 /* series 3 tx rate */ |
| #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff /* RX data length */ |
| #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 /* more desc for this frame */ |
| #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210 0x00004000 /* [5210] receive on ant 1 */ |
| #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211 0x38000000 /* [5211] receive antenna */ |
| #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 /* reception rate */ |
| #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 /* rssi */ |
| #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 /* CRC error */ |
| #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 /* decryption CRC failure */ |
| #define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 /* descriptor complete */ |
| #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210 0x00000008 /* [5210] FIFO overrun */ |
| #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 /* reception success */ |
| #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 /* key cache miss */ |
| #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 /* decryption key index */ |
| #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 /* key index valid */ |
| #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 /* PHY error */ |
| #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 /* 13 bit of TSF */ |
| #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff /* RX data length */ |
| #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 /* decompression CRC error */ |
| #define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 /* more desc for this frame */ |
| #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 /* receive antenna */ |
| #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 /* reception rate */ |
| #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 /* rssi */ |
| #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004 /* CRC error */ |
| #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 /* decryption CRC failure */ |
| #define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 /* descriptor complete */ |
| #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 /* frame reception success */ |
| #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 /* key cache miss */ |
| #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 /* decryption key index */ |
| #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 /* key index valid */ |
| #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020 /* MIC decrypt error */ |
| #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010 /* PHY error */ |
| #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE 0x0000ff00 /* phy error code overlays key index and valid fields */ |
| #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 /* first 15bit of the TSF */ |
| #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */ |
| #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */ |
| #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 /* excessive retries */ |
| #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 /* FIFO underrun */ |
| #define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 /* TX filter indication */ |
| #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 /* TX success */ |
| #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 /* long retry count */ |
| #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 /* TX timestamp */ |
| #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 /* short retry count */ |
| #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5211 0x0000f000 /* [5211+] virtual collision count */ |
| #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 /* signal strength of ACK */ |
| #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 0x00800000 /* [5212] compression status */ |
| #define AR5K_DESC_TX_STATUS1_DONE 0x00000001 /* descriptor complete */ |
| #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212 0x00600000 /* [5212] final TX attempt series ix */ |
| #define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe /* TX sequence number */ |
| #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 0x01000000 /* [5212] transmit antenna */ |
| enum ath5k_phy_error_code |
enum ath5k_phy_error_code - PHY Error codes : Transmit underrun, [5210] No error : Timing error : Illegal parity : Illegal rate : Illegal length : Radar detect, [5210] 64 QAM rate : Illegal service : Transmit override receive : OFDM Timing error [5212+] : OFDM Signal parity error [5212+] : OFDM Illegal rate [5212+] : OFDM Illegal length [5212+] : OFDM Power drop [5212+] : OFDM Service (?) [5212+] : OFDM Restart (?) [5212+] : CCK Timing error [5212+] : Header CRC error [5212+] : Illegal rate [5212+] : CCK Service (?) [5212+] : CCK Restart (?) [5212+]
| struct ath5k_hw_rx_ctl __aligned | ( | 4 | ) |
| enum ath5k_phy_error_code __aligned |
| struct ath5k_hw_all_rx_desc ds_rx |
| struct ath5k_hw_5210_tx_desc ds_tx5210 |
| struct ath5k_hw_5212_tx_desc ds_tx5212 |
| struct ath5k_hw_rx_ctl rx_ctl |
| struct ath5k_hw_rx_status rx_stat |
| struct ath5k_hw_4w_tx_ctl tx_ctl |
| struct ath5k_hw_tx_status tx_stat |
| union { ... } ud |
1.8.2