#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/average.h>
#include <linux/leds.h>
#include <net/mac80211.h>
#include "desc.h"
#include "eeprom.h"
#include "debug.h"
#include "../ath.h"
#include "ani.h"

Data Structures
struct	ath5k_tx_status

struct	ath5k_txq

struct	ath5k_txq_info

struct	ath5k_rx_status

struct	ath5k_gain

struct	ath5k_athchan_2ghz

struct	ath5k_capabilities

struct	ath5k_nfcal_hist

struct	ath5k_led

struct	ath5k_rfkill

struct	ath5k_statistics

struct	ath5k_hw

struct	ath_bus_ops

Macros
#define	CHAN_DEBUG 0

#define	PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */

#define	PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */

#define	PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */

#define	PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */

#define	PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */

#define	PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */

#define	PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */

#define	PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */

#define	PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */

#define	PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */

#define	PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */

#define	PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */

#define	PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */

#define	PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */

#define	PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */

#define	PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */

#define	PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */

#define	PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */

#define	PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */

#define	PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */

#define	ATH5K_PRINTF(fmt,...) pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)

#define	ATH5K_PRINTK(_sc, _level, _fmt,...) _ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)

#define	ATH5K_PRINTK_LIMIT(_sc, _level, _fmt,...)

#define	ATH5K_INFO(_sc, _fmt,...) ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)

#define	ATH5K_WARN(_sc, _fmt,...) ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)

#define	ATH5K_ERR(_sc, _fmt,...) ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)

#define	AR5K_REG_SM(_val, _flags) (((_val) << _flags##_S) & (_flags))

#define	AR5K_REG_MS(_val, _flags) (((_val) & (_flags)) >> _flags##_S)

#define	AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)

#define	AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)

#define	AR5K_REG_ENABLE_BITS(ah, _reg, _flags) ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) \| (_flags), _reg)

#define	AR5K_REG_DISABLE_BITS(ah, _reg, _flags) ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)

#define	AR5K_REG_READ_Q(ah, _reg, _queue) (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \

#define	AR5K_REG_WRITE_Q(ah, _reg, _queue) ath5k_hw_reg_write(ah, (1 << _queue), _reg)

#define	AR5K_Q_ENABLE_BITS(_reg, _queue)

#define	AR5K_Q_DISABLE_BITS(_reg, _queue)

#define	AR5K_REG_WAIT(_i)

#define	AR5K_TUNE_DMA_BEACON_RESP 2

#define	AR5K_TUNE_SW_BEACON_RESP 10

#define	AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0

#define	AR5K_TUNE_MIN_TX_FIFO_THRES 1

#define	AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)

#define	AR5K_TUNE_REGISTER_TIMEOUT 20000

#define	AR5K_TUNE_RSSI_THRES 129

#define	AR5K_TUNE_BMISS_THRES 7

#define	AR5K_TUNE_REGISTER_DWELL_TIME 20000

#define	AR5K_TUNE_BEACON_INTERVAL 100

#define	AR5K_TUNE_AIFS 2

#define	AR5K_TUNE_AIFS_11B 2

#define	AR5K_TUNE_AIFS_XR 0

#define	AR5K_TUNE_CWMIN 15

#define	AR5K_TUNE_CWMIN_11B 31

#define	AR5K_TUNE_CWMIN_XR 3

#define	AR5K_TUNE_CWMAX 1023

#define	AR5K_TUNE_CWMAX_11B 1023

#define	AR5K_TUNE_CWMAX_XR 7

#define	AR5K_TUNE_NOISE_FLOOR -72

#define	AR5K_TUNE_CCA_MAX_GOOD_VALUE -95

#define	AR5K_TUNE_MAX_TXPOWER 63

#define	AR5K_TUNE_DEFAULT_TXPOWER 25

#define	AR5K_TUNE_TPC_TXPOWER false

#define	ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 60000 /* 60 sec */

#define	ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT 10000 /* 10 sec */

#define	ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */

#define	ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */

#define	AR5K_INIT_CARR_SENSE_EN 1

#define	AR5K_INIT_CFG 0x00000000

#define	AR5K_INIT_CYCRSSI_THR1 2

#define	AR5K_INIT_RETRY_SHORT 7

#define	AR5K_INIT_RETRY_LONG 4

#define	AR5K_INIT_SLOT_TIME_TURBO 6

#define	AR5K_INIT_SLOT_TIME_DEFAULT 9

#define	AR5K_INIT_SLOT_TIME_HALF_RATE 13

#define	AR5K_INIT_SLOT_TIME_QUARTER_RATE 21

#define	AR5K_INIT_SLOT_TIME_B 20

#define	AR5K_SLOT_TIME_MAX 0xffff

#define	AR5K_INIT_SIFS_TURBO 6

#define	AR5K_INIT_SIFS_DEFAULT_BG 10

#define	AR5K_INIT_SIFS_DEFAULT_A 16

#define	AR5K_INIT_SIFS_HALF_RATE 32

#define	AR5K_INIT_SIFS_QUARTER_RATE 64

#define	AR5K_INIT_OFDM_PREAMPLE_TIME 20

#define	AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14

#define	AR5K_INIT_OFDM_SYMBOL_TIME 4

#define	AR5K_INIT_OFDM_PLCP_BITS 22

#define	AR5K_INIT_RX_LAT_MAX 63

#define	AR5K_INIT_TX_LAT_A 54

#define	AR5K_INIT_TX_LAT_BG 384

#define	AR5K_INIT_TX_LAT_MIN 32

#define	AR5K_INIT_TX_LATENCY_5210 54

#define	AR5K_INIT_RX_LATENCY_5210 29

#define	AR5K_INIT_TXF2TXD_START_DEFAULT 14

#define	AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12

#define	AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13

#define	AR5K_SWITCH_SETTLING 5760

#define	AR5K_SWITCH_SETTLING_TURBO 7168

#define	AR5K_AGC_SETTLING 28

#define	AR5K_AGC_SETTLING_TURBO 37

#define	AR5K_SREV_UNKNOWN 0xffff

#define	AR5K_SREV_AR5210 0x00 /* Crete */

#define	AR5K_SREV_AR5311 0x10 /* Maui 1 */

#define	AR5K_SREV_AR5311A 0x20 /* Maui 2 */

#define	AR5K_SREV_AR5311B 0x30 /* Spirit */

#define	AR5K_SREV_AR5211 0x40 /* Oahu */

#define	AR5K_SREV_AR5212 0x50 /* Venice */

#define	AR5K_SREV_AR5312_R2 0x52 /* AP31 */

#define	AR5K_SREV_AR5212_V4 0x54 /* ??? */

#define	AR5K_SREV_AR5213 0x55 /* ??? */

#define	AR5K_SREV_AR5312_R7 0x57 /* AP30 */

#define	AR5K_SREV_AR2313_R8 0x58 /* AP43 */

#define	AR5K_SREV_AR5213A 0x59 /* Hainan */

#define	AR5K_SREV_AR2413 0x78 /* Griffin lite */

#define	AR5K_SREV_AR2414 0x70 /* Griffin */

#define	AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */

#define	AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */

#define	AR5K_SREV_AR5424 0x90 /* Condor */

#define	AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */

#define	AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */

#define	AR5K_SREV_AR5413 0xa4 /* Eagle lite */

#define	AR5K_SREV_AR5414 0xa0 /* Eagle */

#define	AR5K_SREV_AR2415 0xb0 /* Talon */

#define	AR5K_SREV_AR5416 0xc0 /* PCI-E */

#define	AR5K_SREV_AR5418 0xca /* PCI-E */

#define	AR5K_SREV_AR2425 0xe0 /* Swan */

#define	AR5K_SREV_AR2417 0xf0 /* Nala */

#define	AR5K_SREV_RAD_5110 0x00

#define	AR5K_SREV_RAD_5111 0x10

#define	AR5K_SREV_RAD_5111A 0x15

#define	AR5K_SREV_RAD_2111 0x20

#define	AR5K_SREV_RAD_5112 0x30

#define	AR5K_SREV_RAD_5112A 0x35

#define	AR5K_SREV_RAD_5112B 0x36

#define	AR5K_SREV_RAD_2112 0x40

#define	AR5K_SREV_RAD_2112A 0x45

#define	AR5K_SREV_RAD_2112B 0x46

#define	AR5K_SREV_RAD_2413 0x50

#define	AR5K_SREV_RAD_5413 0x60

#define	AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */

#define	AR5K_SREV_RAD_2317 0x80

#define	AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */

#define	AR5K_SREV_RAD_2425 0xa2

#define	AR5K_SREV_RAD_5133 0xc0

#define	AR5K_SREV_PHY_5211 0x30

#define	AR5K_SREV_PHY_5212 0x41

#define	AR5K_SREV_PHY_5212A 0x42

#define	AR5K_SREV_PHY_5212B 0x43

#define	AR5K_SREV_PHY_2413 0x45

#define	AR5K_SREV_PHY_5413 0x61

#define	AR5K_SREV_PHY_2425 0x70

#define	AR5K_TXSTAT_ALTRATE 0x80

#define	AR5K_TXERR_XRETRY 0x01

#define	AR5K_TXERR_FILT 0x02

#define	AR5K_TXERR_FIFO 0x04

#define	AR5K_NUM_TX_QUEUES 10

#define	AR5K_NUM_TX_QUEUES_NOQCU 2

#define	AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */

#define	AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */

#define	AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */

#define	AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */

#define	AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */

#define	AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */

#define	AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */

#define	AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */

#define	AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */

#define	AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */

#define	AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/

#define	AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */

#define	AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */

#define	AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/

#define	AR5K_TXPOWER_OFDM(_r, _v)

#define	AR5K_TXPOWER_CCK(_r, _v)

#define	AR5K_RXERR_CRC 0x01

#define	AR5K_RXERR_PHY 0x02

#define	AR5K_RXERR_FIFO 0x04

#define	AR5K_RXERR_DECRYPT 0x08

#define	AR5K_RXERR_MIC 0x10

#define	AR5K_RXKEYIX_INVALID ((u8) -1)

#define	AR5K_TXKEYIX_INVALID ((u32) -1)

#define	AR5K_BEACON_PERIOD 0x0000ffff

#define	AR5K_BEACON_ENA 0x00800000 /enable beacon xmit/

#define	AR5K_BEACON_RESET_TSF 0x01000000 /force a TSF reset/

#define	TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)

#define	AR5K_SLOT_TIME_9 396

#define	AR5K_SLOT_TIME_20 880

#define	AR5K_SLOT_TIME_MAX 0xffff

#define	AR5K_MAX_RATES 32

#define	ATH5K_RATE_CODE_1M 0x1B

#define	ATH5K_RATE_CODE_2M 0x1A

#define	ATH5K_RATE_CODE_5_5M 0x19

#define	ATH5K_RATE_CODE_11M 0x18

#define	ATH5K_RATE_CODE_6M 0x0B

#define	ATH5K_RATE_CODE_9M 0x0F

#define	ATH5K_RATE_CODE_12M 0x0A

#define	ATH5K_RATE_CODE_18M 0x0E

#define	ATH5K_RATE_CODE_24M 0x09

#define	ATH5K_RATE_CODE_36M 0x0D

#define	ATH5K_RATE_CODE_48M 0x08

#define	ATH5K_RATE_CODE_54M 0x0C

#define	AR5K_SET_SHORT_PREAMBLE 0x04

#define	AR5K_KEYCACHE_SIZE 8

#define	AR5K_RSSI_EP_MULTIPLIER (1 << 7)

#define	AR5K_ASSERT_ENTRY(_e, _s)

#define	AR5K_LED_INIT 0 /IEEE80211_S_INIT/

#define	AR5K_LED_SCAN 1 /IEEE80211_S_SCAN/

#define	AR5K_LED_AUTH 2 /IEEE80211_S_AUTH/

#define	AR5K_LED_ASSOC 3 /IEEE80211_S_ASSOC/

#define	AR5K_LED_RUN 4 /IEEE80211_S_RUN/

#define	AR5K_SOFTLED_PIN 0

#define	AR5K_SOFTLED_ON 0

#define	AR5K_SOFTLED_OFF 1

#define	ATH5K_NF_CAL_HIST_MAX 8

#define	ATH5K_LED_MAX_NAME_LEN 31

#define	AR5K_MAX_GPIO 10

#define	AR5K_MAX_RF_BANKS 8

#define	ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)

#define	ATH_RXBUF 40 /* number of RX buffers */

#define	ATH_TXBUF 200 /* number of TX buffers */

#define	ATH_BCBUF 4 /* number of beacon buffers */

#define	ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */

#define	ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */

#define	ATH_STAT_INVALID 0 /* disable hardware accesses */

#define	ATH_STAT_PROMISC 1

#define	ATH_STAT_LEDSOFT 2 /* enable LED gpio status */

#define	ATH_STAT_STARTED 3 /* opened & irqs enabled */

#define	ah_modes ah_capabilities.cap_mode

#define	ah_ee_version ah_capabilities.cap_eeprom.ee_version

Enumerations
enum	ath5k_version { AR5K_AR5210 = 0, AR5K_AR5211 = 1, AR5K_AR5212 = 2 }

enum	ath5k_radio { AR5K_RF5110 = 0, AR5K_RF5111 = 1, AR5K_RF5112 = 2, AR5K_RF2413 = 3, AR5K_RF5413 = 4, AR5K_RF2316 = 5, AR5K_RF2317 = 6, AR5K_RF2425 = 7 }

enum	ath5k_driver_mode { AR5K_MODE_11A = 0, AR5K_MODE_11B = 1, AR5K_MODE_11G = 2, AR5K_MODE_MAX = 3 }

enum	ath5k_ant_mode { AR5K_ANTMODE_DEFAULT = 0, AR5K_ANTMODE_FIXED_A = 1, AR5K_ANTMODE_FIXED_B = 2, AR5K_ANTMODE_SINGLE_AP = 3, AR5K_ANTMODE_SECTOR_AP = 4, AR5K_ANTMODE_SECTOR_STA = 5, AR5K_ANTMODE_DEBUG = 6, AR5K_ANTMODE_MAX }

enum	ath5k_bw_mode { AR5K_BWMODE_DEFAULT = 0, AR5K_BWMODE_5MHZ = 1, AR5K_BWMODE_10MHZ = 2, AR5K_BWMODE_40MHZ = 3 }

enum	ath5k_tx_queue { AR5K_TX_QUEUE_INACTIVE = 0, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_BEACON, AR5K_TX_QUEUE_CAB, AR5K_TX_QUEUE_UAPSD }

enum	ath5k_tx_queue_subtype { AR5K_WME_AC_BK = 0, AR5K_WME_AC_BE, AR5K_WME_AC_VI, AR5K_WME_AC_VO }

enum	ath5k_tx_queue_id { AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, AR5K_TX_QUEUE_ID_DATA_MIN = 0, AR5K_TX_QUEUE_ID_DATA_MAX = 3, AR5K_TX_QUEUE_ID_UAPSD = 7, AR5K_TX_QUEUE_ID_CAB = 8, AR5K_TX_QUEUE_ID_BEACON = 9 }

enum	ath5k_pkt_type { AR5K_PKT_TYPE_NORMAL = 0, AR5K_PKT_TYPE_ATIM = 1, AR5K_PKT_TYPE_PSPOLL = 2, AR5K_PKT_TYPE_BEACON = 3, AR5K_PKT_TYPE_PROBE_RESP = 4, AR5K_PKT_TYPE_PIFS = 5 }

enum	ath5k_rfgain { AR5K_RFGAIN_INACTIVE = 0, AR5K_RFGAIN_ACTIVE, AR5K_RFGAIN_READ_REQUESTED, AR5K_RFGAIN_NEED_CHANGE }

enum	ath5k_dmasize { AR5K_DMASIZE_4B = 0, AR5K_DMASIZE_8B, AR5K_DMASIZE_16B, AR5K_DMASIZE_32B, AR5K_DMASIZE_64B, AR5K_DMASIZE_128B, AR5K_DMASIZE_256B, AR5K_DMASIZE_512B }

enum	ath5k_int { AR5K_INT_RXOK = 0x00000001, AR5K_INT_RXDESC = 0x00000002, AR5K_INT_RXERR = 0x00000004, AR5K_INT_RXNOFRM = 0x00000008, AR5K_INT_RXEOL = 0x00000010, AR5K_INT_RXORN = 0x00000020, AR5K_INT_TXOK = 0x00000040, AR5K_INT_TXDESC = 0x00000080, AR5K_INT_TXERR = 0x00000100, AR5K_INT_TXNOFRM = 0x00000200, AR5K_INT_TXEOL = 0x00000400, AR5K_INT_TXURN = 0x00000800, AR5K_INT_MIB = 0x00001000, AR5K_INT_SWI = 0x00002000, AR5K_INT_RXPHY = 0x00004000, AR5K_INT_RXKCM = 0x00008000, AR5K_INT_SWBA = 0x00010000, AR5K_INT_BRSSI = 0x00020000, AR5K_INT_BMISS = 0x00040000, AR5K_INT_FATAL = 0x00080000, AR5K_INT_BNR = 0x00100000, AR5K_INT_TIM = 0x00200000, AR5K_INT_DTIM = 0x00400000, AR5K_INT_DTIM_SYNC = 0x00800000, AR5K_INT_GPIO = 0x01000000, AR5K_INT_BCN_TIMEOUT = 0x02000000, AR5K_INT_CAB_TIMEOUT = 0x04000000, AR5K_INT_QCBRORN = 0x08000000, AR5K_INT_QCBRURN = 0x10000000, AR5K_INT_QTRIG = 0x20000000, AR5K_INT_GLOBAL = 0x80000000, AR5K_INT_TX_ALL, AR5K_INT_RX_ALL, AR5K_INT_COMMON, AR5K_INT_NOCARD = 0xffffffff }

enum	ath5k_calibration_mask { AR5K_CALIBRATION_FULL = 0x01, AR5K_CALIBRATION_SHORT = 0x02, AR5K_CALIBRATION_NF = 0x04, AR5K_CALIBRATION_ANI = 0x08 }

enum	ath5k_power_mode { AR5K_PM_UNDEFINED = 0, AR5K_PM_AUTO, AR5K_PM_AWAKE, AR5K_PM_FULL_SLEEP, AR5K_PM_NETWORK_SLEEP }

Functions
void	__printf (3, 4) _ath5k_printk(const struct ath5k_hw *ah

int	ath5k_hw_init (struct ath5k_hw *ah)

void	ath5k_hw_deinit (struct ath5k_hw *ah)

int	ath5k_sysfs_register (struct ath5k_hw *ah)

void	ath5k_sysfs_unregister (struct ath5k_hw *ah)

int	ath5k_hw_read_srev (struct ath5k_hw *ah)

int	ath5k_init_leds (struct ath5k_hw *ah)

void	ath5k_led_enable (struct ath5k_hw *ah)

void	ath5k_led_off (struct ath5k_hw *ah)

void	ath5k_unregister_leds (struct ath5k_hw *ah)

int	ath5k_hw_nic_wakeup (struct ath5k_hw ah, struct ieee80211_channel channel)

int	ath5k_hw_on_hold (struct ath5k_hw *ah)

int	ath5k_hw_reset (struct ath5k_hw ah, enum nl80211_iftype op_mode, struct ieee80211_channel channel, bool fast, bool skip_pcu)

int	ath5k_hw_register_timeout (struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, bool is_set)

unsigned int	ath5k_hw_htoclock (struct ath5k_hw *ah, unsigned int usec)

unsigned int	ath5k_hw_clocktoh (struct ath5k_hw *ah, unsigned int clock)

void	ath5k_hw_set_clockrate (struct ath5k_hw *ah)

void	ath5k_hw_start_rx_dma (struct ath5k_hw *ah)

u32	ath5k_hw_get_rxdp (struct ath5k_hw *ah)

int	ath5k_hw_set_rxdp (struct ath5k_hw *ah, u32 phys_addr)

int	ath5k_hw_start_tx_dma (struct ath5k_hw *ah, unsigned int queue)

int	ath5k_hw_stop_beacon_queue (struct ath5k_hw *ah, unsigned int queue)

u32	ath5k_hw_get_txdp (struct ath5k_hw *ah, unsigned int queue)

int	ath5k_hw_set_txdp (struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)

int	ath5k_hw_update_tx_triglevel (struct ath5k_hw *ah, bool increase)

bool	ath5k_hw_is_intr_pending (struct ath5k_hw *ah)

int	ath5k_hw_get_isr (struct ath5k_hw ah, enum ath5k_int interrupt_mask)

enum ath5k_int	ath5k_hw_set_imr (struct ath5k_hw *ah, enum ath5k_int new_mask)

void	ath5k_hw_update_mib_counters (struct ath5k_hw *ah)

void	ath5k_hw_dma_init (struct ath5k_hw *ah)

int	ath5k_hw_dma_stop (struct ath5k_hw *ah)

int	ath5k_eeprom_init (struct ath5k_hw *ah)

void	ath5k_eeprom_detach (struct ath5k_hw *ah)

int	ath5k_hw_get_frame_duration (struct ath5k_hw ah, enum ieee80211_band band, int len, struct ieee80211_rate rate, bool shortpre)

unsigned int	ath5k_hw_get_default_slottime (struct ath5k_hw *ah)

unsigned int	ath5k_hw_get_default_sifs (struct ath5k_hw *ah)

int	ath5k_hw_set_opmode (struct ath5k_hw *ah, enum nl80211_iftype opmode)

void	ath5k_hw_set_coverage_class (struct ath5k_hw *ah, u8 coverage_class)

int	ath5k_hw_set_lladdr (struct ath5k_hw ah, const u8 mac)

void	ath5k_hw_set_bssid (struct ath5k_hw *ah)

void	ath5k_hw_set_bssid_mask (struct ath5k_hw ah, const u8 mask)

void	ath5k_hw_set_mcast_filter (struct ath5k_hw *ah, u32 filter0, u32 filter1)

u32	ath5k_hw_get_rx_filter (struct ath5k_hw *ah)

void	ath5k_hw_set_rx_filter (struct ath5k_hw *ah, u32 filter)

void	ath5k_hw_start_rx_pcu (struct ath5k_hw *ah)

void	ath5k_hw_stop_rx_pcu (struct ath5k_hw *ah)

u64	ath5k_hw_get_tsf64 (struct ath5k_hw *ah)

void	ath5k_hw_set_tsf64 (struct ath5k_hw *ah, u64 tsf64)

void	ath5k_hw_reset_tsf (struct ath5k_hw *ah)

void	ath5k_hw_init_beacon_timers (struct ath5k_hw *ah, u32 next_beacon, u32 interval)

bool	ath5k_hw_check_beacon_timers (struct ath5k_hw *ah, int intval)

void	ath5k_hw_pcu_init (struct ath5k_hw *ah, enum nl80211_iftype op_mode)

int	ath5k_hw_get_tx_queueprops (struct ath5k_hw ah, int queue, struct ath5k_txq_info queue_info)

int	ath5k_hw_set_tx_queueprops (struct ath5k_hw ah, int queue, const struct ath5k_txq_info queue_info)

int	ath5k_hw_setup_tx_queue (struct ath5k_hw ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info queue_info)

void	ath5k_hw_set_tx_retry_limits (struct ath5k_hw *ah, unsigned int queue)

u32	ath5k_hw_num_tx_pending (struct ath5k_hw *ah, unsigned int queue)

void	ath5k_hw_release_tx_queue (struct ath5k_hw *ah, unsigned int queue)

int	ath5k_hw_reset_tx_queue (struct ath5k_hw *ah, unsigned int queue)

int	ath5k_hw_set_ifs_intervals (struct ath5k_hw *ah, unsigned int slot_time)

int	ath5k_hw_init_queues (struct ath5k_hw *ah)

int	ath5k_hw_init_desc_functions (struct ath5k_hw *ah)

int	ath5k_hw_setup_rx_desc (struct ath5k_hw ah, struct ath5k_desc desc, u32 size, unsigned int flags)

int	ath5k_hw_setup_mrr_tx_desc (struct ath5k_hw ah, struct ath5k_desc desc, unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)

void	ath5k_hw_set_ledstate (struct ath5k_hw *ah, unsigned int state)

int	ath5k_hw_set_gpio_input (struct ath5k_hw *ah, u32 gpio)

int	ath5k_hw_set_gpio_output (struct ath5k_hw *ah, u32 gpio)

u32	ath5k_hw_get_gpio (struct ath5k_hw *ah, u32 gpio)

int	ath5k_hw_set_gpio (struct ath5k_hw *ah, u32 gpio, u32 val)

void	ath5k_hw_set_gpio_intr (struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level)

void	ath5k_rfkill_hw_start (struct ath5k_hw *ah)

void	ath5k_rfkill_hw_stop (struct ath5k_hw *ah)

int	ath5k_hw_set_capabilities (struct ath5k_hw *ah)

int	ath5k_hw_enable_pspoll (struct ath5k_hw ah, u8 bssid, u16 assoc_id)

int	ath5k_hw_disable_pspoll (struct ath5k_hw *ah)

int	ath5k_hw_write_initvals (struct ath5k_hw *ah, u8 mode, bool change_channel)

u16	ath5k_hw_radio_revision (struct ath5k_hw *ah, enum ieee80211_band band)

int	ath5k_hw_phy_disable (struct ath5k_hw *ah)

enum ath5k_rfgain	ath5k_hw_gainf_calibrate (struct ath5k_hw *ah)

int	ath5k_hw_rfgain_opt_init (struct ath5k_hw *ah)

bool	ath5k_channel_ok (struct ath5k_hw ah, struct ieee80211_channel channel)

void	ath5k_hw_init_nfcal_hist (struct ath5k_hw *ah)

int	ath5k_hw_phy_calibrate (struct ath5k_hw ah, struct ieee80211_channel channel)

void	ath5k_hw_update_noise_floor (struct ath5k_hw *ah)

bool	ath5k_hw_chan_has_spur_noise (struct ath5k_hw ah, struct ieee80211_channel channel)

void	ath5k_hw_set_antenna_mode (struct ath5k_hw *ah, u8 ant_mode)

void	ath5k_hw_set_antenna_switch (struct ath5k_hw *ah, u8 ee_mode)

int	ath5k_hw_set_txpower_limit (struct ath5k_hw *ah, u8 txpower)

int	ath5k_hw_phy_init (struct ath5k_hw ah, struct ieee80211_channel channel, u8 mode, bool fast)

Variables
void const char *	level

void const char const char *	fmt

bool	ath5k_modparam_nohwcrypt

struct ieee80211_ops	ath5k_hw_ops

Macro Definition Documentation

#define ah_ee_version ah_capabilities.cap_eeprom.ee_version

Definition at line 1361 of file ath5k.h.

#define ah_modes ah_capabilities.cap_mode

Definition at line 1360 of file ath5k.h.

#define AR5K_AGC_SETTLING 28

Definition at line 262 of file ath5k.h.

#define AR5K_AGC_SETTLING_TURBO 37

Definition at line 264 of file ath5k.h.

#define AR5K_ASSERT_ENTRY	(	_e,
		_s
	)

Value:

do {        \
    if (_e >= _s)               \
        return false;           \
} while (0)

Definition at line 931 of file ath5k.h.

#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/

Definition at line 739 of file ath5k.h.

#define AR5K_BEACON_PERIOD 0x0000ffff

Definition at line 738 of file ath5k.h.

#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/

Definition at line 740 of file ath5k.h.

#define AR5K_INIT_CARR_SENSE_EN 1

Definition at line 198 of file ath5k.h.

#define AR5K_INIT_CFG 0x00000000

Definition at line 206 of file ath5k.h.

#define AR5K_INIT_CYCRSSI_THR1 2

Definition at line 210 of file ath5k.h.

#define AR5K_INIT_OFDM_PLCP_BITS 22

Definition at line 238 of file ath5k.h.

#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14

Definition at line 236 of file ath5k.h.

#define AR5K_INIT_OFDM_PREAMPLE_TIME 20

Definition at line 234 of file ath5k.h.

#define AR5K_INIT_OFDM_SYMBOL_TIME 4

Definition at line 237 of file ath5k.h.

#define AR5K_INIT_RETRY_LONG 4

Definition at line 214 of file ath5k.h.

#define AR5K_INIT_RETRY_SHORT 7

Definition at line 213 of file ath5k.h.

#define AR5K_INIT_RX_LAT_MAX 63

Definition at line 241 of file ath5k.h.

#define AR5K_INIT_RX_LATENCY_5210 29

Definition at line 250 of file ath5k.h.

#define AR5K_INIT_SIFS_DEFAULT_A 16

Definition at line 227 of file ath5k.h.

#define AR5K_INIT_SIFS_DEFAULT_BG 10

Definition at line 226 of file ath5k.h.

#define AR5K_INIT_SIFS_HALF_RATE 32

Definition at line 228 of file ath5k.h.

#define AR5K_INIT_SIFS_QUARTER_RATE 64

Definition at line 229 of file ath5k.h.

#define AR5K_INIT_SIFS_TURBO 6

Definition at line 225 of file ath5k.h.

#define AR5K_INIT_SLOT_TIME_B 20

Definition at line 221 of file ath5k.h.

#define AR5K_INIT_SLOT_TIME_DEFAULT 9

Definition at line 218 of file ath5k.h.

#define AR5K_INIT_SLOT_TIME_HALF_RATE 13

Definition at line 219 of file ath5k.h.

#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21

Definition at line 220 of file ath5k.h.

#define AR5K_INIT_SLOT_TIME_TURBO 6

Definition at line 217 of file ath5k.h.

#define AR5K_INIT_TX_LAT_A 54

Definition at line 244 of file ath5k.h.

#define AR5K_INIT_TX_LAT_BG 384

Definition at line 245 of file ath5k.h.

#define AR5K_INIT_TX_LAT_MIN 32

Definition at line 247 of file ath5k.h.

#define AR5K_INIT_TX_LATENCY_5210 54

Definition at line 249 of file ath5k.h.

#define AR5K_INIT_TXF2TXD_START_DEFAULT 14

Definition at line 253 of file ath5k.h.

#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12

Definition at line 254 of file ath5k.h.

#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13

Definition at line 255 of file ath5k.h.

#define AR5K_KEYCACHE_SIZE 8

Definition at line 919 of file ath5k.h.

#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/

Definition at line 1123 of file ath5k.h.

#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/

Definition at line 1122 of file ath5k.h.

#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/

Definition at line 1120 of file ath5k.h.

#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/

Definition at line 1124 of file ath5k.h.

#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/

Definition at line 1121 of file ath5k.h.

#define AR5K_MAX_GPIO 10

Definition at line 1239 of file ath5k.h.

#define AR5K_MAX_RATES 32

DOC: Rate codes

Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.

The rate code is used to get the RX rate or set the TX rate on the hardware descriptors. It is also used for internal modulation control and settings.

This is the hardware rate map we are aware of (html unfriendly):

Rate code Rate (Kbps)

0x01 3000 (XR) 0x02 1000 (XR) 0x03 250 (XR) 0x04 - 05 -Reserved- 0x06 2000 (XR) 0x07 500 (XR) 0x08 48000 (OFDM) 0x09 24000 (OFDM) 0x0A 12000 (OFDM) 0x0B 6000 (OFDM) 0x0C 54000 (OFDM) 0x0D 36000 (OFDM) 0x0E 18000 (OFDM) 0x0F 9000 (OFDM) 0x10 - 17 -Reserved- 0x18 11000L (CCK) 0x19 5500L (CCK) 0x1A 2000L (CCK) 0x1B 1000L (CCK) 0x1C 11000S (CCK) 0x1D 5500S (CCK) 0x1E 2000S (CCK) 0x1F -Reserved-

"S" indicates CCK rates with short preamble and "L" with long preamble.

AR5211 has different rate codes for CCK (802.11B) rates. It only uses the lowest 4 bits, so they are the same as above with a 0xF mask. (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). We handle this in ath5k_setup_bands().

Definition at line 894 of file ath5k.h.

#define AR5K_MAX_RF_BANKS 8

Definition at line 1240 of file ath5k.h.

#define AR5K_NUM_TX_QUEUES 10

Definition at line 546 of file ath5k.h.

#define AR5K_NUM_TX_QUEUES_NOQCU 2

Definition at line 547 of file ath5k.h.

#define AR5K_Q_DISABLE_BITS	(	_reg,
		_queue
	)

Value:

do {                \
    _reg &= ~(1 << _queue);                     \
} while (0)

Definition at line 148 of file ath5k.h.

#define AR5K_Q_ENABLE_BITS	(	_reg,
		_queue
	)

Value:

do {                \
    _reg |= 1 << _queue;                        \
} while (0)

Definition at line 144 of file ath5k.h.

#define AR5K_REG_DISABLE_BITS	(	ah,
		_reg,
		_flags
	)	ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)

Definition at line 134 of file ath5k.h.

#define AR5K_REG_ENABLE_BITS	(	ah,
		_reg,
		_flags
	)	ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) \| (_flags), _reg)

Definition at line 131 of file ath5k.h.

#define AR5K_REG_MASKED_BITS	(	ah,
		_reg,
		_flags,
		_mask
	)

Value:

ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \

(_mask)) | (_flags), _reg)

Definition at line 127 of file ath5k.h.

#define AR5K_REG_MS	(	_val,
		_flags
	)	(((_val) & (_flags)) >> _flags##_S)

Definition at line 115 of file ath5k.h.

#define AR5K_REG_READ_Q	(	ah,
		_reg,
		_queue
	)	(ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \

Definition at line 138 of file ath5k.h.

#define AR5K_REG_SM	(	_val,
		_flags
	)	(((_val) << _flags##_S) & (_flags))

Definition at line 111 of file ath5k.h.

#define AR5K_REG_WAIT ( _i )

Value:

do {                        \
    if (_i % 64)                            \
        udelay(1);                      \
} while (0)

Definition at line 153 of file ath5k.h.

#define AR5K_REG_WRITE_BITS	(	ah,
		_reg,
		_flags,
		_val
	)

Value:

ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \

(((_val) << _flags##_S) & (_flags)), _reg)

Definition at line 123 of file ath5k.h.

#define AR5K_REG_WRITE_Q	(	ah,
		_reg,
		_queue
	)	ath5k_hw_reg_write(ah, (1 << _queue), _reg)

Definition at line 141 of file ath5k.h.

#define AR5K_RSSI_EP_MULTIPLIER (1 << 7)

Definition at line 929 of file ath5k.h.

#define AR5K_RXERR_CRC 0x01

Definition at line 725 of file ath5k.h.

#define AR5K_RXERR_DECRYPT 0x08

Definition at line 728 of file ath5k.h.

#define AR5K_RXERR_FIFO 0x04

Definition at line 727 of file ath5k.h.

#define AR5K_RXERR_MIC 0x10

Definition at line 729 of file ath5k.h.

#define AR5K_RXERR_PHY 0x02

Definition at line 726 of file ath5k.h.

#define AR5K_RXKEYIX_INVALID ((u8) -1)

Definition at line 730 of file ath5k.h.

#define AR5K_SET_SHORT_PREAMBLE 0x04

Definition at line 913 of file ath5k.h.

#define AR5K_SLOT_TIME_20 880

Definition at line 799 of file ath5k.h.

#define AR5K_SLOT_TIME_9 396

Definition at line 798 of file ath5k.h.

#define AR5K_SLOT_TIME_MAX 0xffff

Definition at line 800 of file ath5k.h.

#define AR5K_SLOT_TIME_MAX 0xffff

Definition at line 800 of file ath5k.h.

#define AR5K_SOFTLED_OFF 1

Definition at line 1129 of file ath5k.h.

#define AR5K_SOFTLED_ON 0

Definition at line 1128 of file ath5k.h.

#define AR5K_SOFTLED_PIN 0

Definition at line 1127 of file ath5k.h.

#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */

Definition at line 322 of file ath5k.h.

#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */

Definition at line 326 of file ath5k.h.

#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */

Definition at line 327 of file ath5k.h.

#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */

Definition at line 329 of file ath5k.h.

#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */

Definition at line 330 of file ath5k.h.

#define AR5K_SREV_AR2413 0x78 /* Griffin lite */

Definition at line 324 of file ath5k.h.

#define AR5K_SREV_AR2414 0x70 /* Griffin */

Definition at line 325 of file ath5k.h.

#define AR5K_SREV_AR2415 0xb0 /* Talon */

Definition at line 333 of file ath5k.h.

#define AR5K_SREV_AR2417 0xf0 /* Nala */

Definition at line 337 of file ath5k.h.

#define AR5K_SREV_AR2425 0xe0 /* Swan */

Definition at line 336 of file ath5k.h.

#define AR5K_SREV_AR5210 0x00 /* Crete */

Definition at line 312 of file ath5k.h.

#define AR5K_SREV_AR5211 0x40 /* Oahu */

Definition at line 316 of file ath5k.h.

#define AR5K_SREV_AR5212 0x50 /* Venice */

Definition at line 317 of file ath5k.h.

#define AR5K_SREV_AR5212_V4 0x54 /* ??? */

Definition at line 319 of file ath5k.h.

#define AR5K_SREV_AR5213 0x55 /* ??? */

Definition at line 320 of file ath5k.h.

#define AR5K_SREV_AR5213A 0x59 /* Hainan */

Definition at line 323 of file ath5k.h.

#define AR5K_SREV_AR5311 0x10 /* Maui 1 */

Definition at line 313 of file ath5k.h.

#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */

Definition at line 314 of file ath5k.h.

#define AR5K_SREV_AR5311B 0x30 /* Spirit */

Definition at line 315 of file ath5k.h.

#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */

Definition at line 318 of file ath5k.h.

#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */

Definition at line 321 of file ath5k.h.

#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */

Definition at line 331 of file ath5k.h.

#define AR5K_SREV_AR5414 0xa0 /* Eagle */

Definition at line 332 of file ath5k.h.

#define AR5K_SREV_AR5416 0xc0 /* PCI-E */

Definition at line 334 of file ath5k.h.

#define AR5K_SREV_AR5418 0xca /* PCI-E */

Definition at line 335 of file ath5k.h.

#define AR5K_SREV_AR5424 0x90 /* Condor */

Definition at line 328 of file ath5k.h.

#define AR5K_SREV_PHY_2413 0x45

Definition at line 361 of file ath5k.h.

#define AR5K_SREV_PHY_2425 0x70

Definition at line 363 of file ath5k.h.

#define AR5K_SREV_PHY_5211 0x30

Definition at line 357 of file ath5k.h.

#define AR5K_SREV_PHY_5212 0x41

Definition at line 358 of file ath5k.h.

#define AR5K_SREV_PHY_5212A 0x42

Definition at line 359 of file ath5k.h.

#define AR5K_SREV_PHY_5212B 0x43

Definition at line 360 of file ath5k.h.

#define AR5K_SREV_PHY_5413 0x61

Definition at line 362 of file ath5k.h.

#define AR5K_SREV_RAD_2111 0x20

Definition at line 342 of file ath5k.h.

#define AR5K_SREV_RAD_2112 0x40

Definition at line 346 of file ath5k.h.

#define AR5K_SREV_RAD_2112A 0x45

Definition at line 347 of file ath5k.h.

#define AR5K_SREV_RAD_2112B 0x46

Definition at line 348 of file ath5k.h.

#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */

Definition at line 351 of file ath5k.h.

#define AR5K_SREV_RAD_2317 0x80

Definition at line 352 of file ath5k.h.

#define AR5K_SREV_RAD_2413 0x50

Definition at line 349 of file ath5k.h.

#define AR5K_SREV_RAD_2425 0xa2

Definition at line 354 of file ath5k.h.

#define AR5K_SREV_RAD_5110 0x00

Definition at line 339 of file ath5k.h.

#define AR5K_SREV_RAD_5111 0x10

Definition at line 340 of file ath5k.h.

#define AR5K_SREV_RAD_5111A 0x15

Definition at line 341 of file ath5k.h.

#define AR5K_SREV_RAD_5112 0x30

Definition at line 343 of file ath5k.h.

#define AR5K_SREV_RAD_5112A 0x35

Definition at line 344 of file ath5k.h.

#define AR5K_SREV_RAD_5112B 0x36

Definition at line 345 of file ath5k.h.

#define AR5K_SREV_RAD_5133 0xc0

Definition at line 355 of file ath5k.h.

#define AR5K_SREV_RAD_5413 0x60

Definition at line 350 of file ath5k.h.

#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */

Definition at line 353 of file ath5k.h.

#define AR5K_SREV_UNKNOWN 0xffff

Definition at line 310 of file ath5k.h.

#define AR5K_SWITCH_SETTLING 5760

Definition at line 259 of file ath5k.h.

#define AR5K_SWITCH_SETTLING_TURBO 7168

Definition at line 260 of file ath5k.h.

#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0

Definition at line 164 of file ath5k.h.

#define AR5K_TUNE_AIFS 2

Definition at line 179 of file ath5k.h.

#define AR5K_TUNE_AIFS_11B 2

Definition at line 180 of file ath5k.h.

#define AR5K_TUNE_AIFS_XR 0

Definition at line 181 of file ath5k.h.

#define AR5K_TUNE_BEACON_INTERVAL 100

Definition at line 178 of file ath5k.h.

#define AR5K_TUNE_BMISS_THRES 7

Definition at line 176 of file ath5k.h.

#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95

Definition at line 189 of file ath5k.h.

#define AR5K_TUNE_CWMAX 1023

Definition at line 185 of file ath5k.h.

#define AR5K_TUNE_CWMAX_11B 1023

Definition at line 186 of file ath5k.h.

#define AR5K_TUNE_CWMAX_XR 7

Definition at line 187 of file ath5k.h.

#define AR5K_TUNE_CWMIN 15

Definition at line 182 of file ath5k.h.

#define AR5K_TUNE_CWMIN_11B 31

Definition at line 183 of file ath5k.h.

#define AR5K_TUNE_CWMIN_XR 3

Definition at line 184 of file ath5k.h.

#define AR5K_TUNE_DEFAULT_TXPOWER 25

Definition at line 191 of file ath5k.h.

#define AR5K_TUNE_DMA_BEACON_RESP 2

Definition at line 162 of file ath5k.h.

#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)

Definition at line 166 of file ath5k.h.

#define AR5K_TUNE_MAX_TXPOWER 63

Definition at line 190 of file ath5k.h.

#define AR5K_TUNE_MIN_TX_FIFO_THRES 1

Definition at line 165 of file ath5k.h.

#define AR5K_TUNE_NOISE_FLOOR -72

Definition at line 188 of file ath5k.h.

#define AR5K_TUNE_REGISTER_DWELL_TIME 20000

Definition at line 177 of file ath5k.h.

#define AR5K_TUNE_REGISTER_TIMEOUT 20000

Definition at line 167 of file ath5k.h.

#define AR5K_TUNE_RSSI_THRES 129

Definition at line 170 of file ath5k.h.

#define AR5K_TUNE_SW_BEACON_RESP 10

Definition at line 163 of file ath5k.h.

#define AR5K_TUNE_TPC_TXPOWER false

Definition at line 192 of file ath5k.h.

#define AR5K_TXERR_FIFO 0x04

Definition at line 528 of file ath5k.h.

#define AR5K_TXERR_FILT 0x02

Definition at line 527 of file ath5k.h.

#define AR5K_TXERR_XRETRY 0x01

Definition at line 526 of file ath5k.h.

#define AR5K_TXKEYIX_INVALID ((u32) -1)

Definition at line 731 of file ath5k.h.

#define AR5K_TXPOWER_CCK	(	_r,
		_v
	)

Value:

(           \
    (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
)

Definition at line 691 of file ath5k.h.

#define AR5K_TXPOWER_OFDM	(	_r,
		_v
	)

Value:

(           \
    ((0 & 1) << ((_v) + 6)) |               \
    (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
)

Definition at line 686 of file ath5k.h.

#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */

Definition at line 603 of file ath5k.h.

#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */

Definition at line 599 of file ath5k.h.

#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */

Definition at line 600 of file ath5k.h.

#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/

Definition at line 607 of file ath5k.h.

#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */

Definition at line 605 of file ath5k.h.

#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */

Definition at line 606 of file ath5k.h.

#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */

Definition at line 601 of file ath5k.h.

#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/

Definition at line 604 of file ath5k.h.

#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */

Definition at line 597 of file ath5k.h.

#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */

Definition at line 596 of file ath5k.h.

#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */

Definition at line 595 of file ath5k.h.

#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */

Definition at line 602 of file ath5k.h.

#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */

Definition at line 594 of file ath5k.h.

#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */

Definition at line 598 of file ath5k.h.

#define AR5K_TXSTAT_ALTRATE 0x80

Definition at line 525 of file ath5k.h.

#define ATH5K_ERR	(	_sc,
		_fmt,
		...
	)	ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)

Definition at line 101 of file ath5k.h.

#define ATH5K_INFO	(	_sc,
		_fmt,
		...
	)	ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)

Definition at line 95 of file ath5k.h.

#define ATH5K_LED_MAX_NAME_LEN 31

Definition at line 1174 of file ath5k.h.

#define ATH5K_NF_CAL_HIST_MAX 8

Definition at line 1168 of file ath5k.h.

#define ATH5K_PRINTF	(	fmt,
		...
	)	pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)

Definition at line 79 of file ath5k.h.

#define ATH5K_PRINTK	(	_sc,
		_level,
		_fmt,
		...
	)	_ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)

Definition at line 86 of file ath5k.h.

#define ATH5K_PRINTK_LIMIT	(	_sc,
		_level,
		_fmt,
		...
	)

Value:

do {                                    \
    if (net_ratelimit())                        \
        ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__);     \
} while (0)

Definition at line 89 of file ath5k.h.

#define ATH5K_RATE_CODE_11M 0x18

Definition at line 900 of file ath5k.h.

#define ATH5K_RATE_CODE_12M 0x0A

Definition at line 904 of file ath5k.h.

#define ATH5K_RATE_CODE_18M 0x0E

Definition at line 905 of file ath5k.h.

#define ATH5K_RATE_CODE_1M 0x1B

Definition at line 897 of file ath5k.h.

#define ATH5K_RATE_CODE_24M 0x09

Definition at line 906 of file ath5k.h.

#define ATH5K_RATE_CODE_2M 0x1A

Definition at line 898 of file ath5k.h.

#define ATH5K_RATE_CODE_36M 0x0D

Definition at line 907 of file ath5k.h.

#define ATH5K_RATE_CODE_48M 0x08

Definition at line 908 of file ath5k.h.

#define ATH5K_RATE_CODE_54M 0x0C

Definition at line 909 of file ath5k.h.

#define ATH5K_RATE_CODE_5_5M 0x19

Definition at line 899 of file ath5k.h.

#define ATH5K_RATE_CODE_6M 0x0B

Definition at line 902 of file ath5k.h.

#define ATH5K_RATE_CODE_9M 0x0F

Definition at line 903 of file ath5k.h.

#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */

Definition at line 195 of file ath5k.h.

#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 60000 /* 60 sec */

Definition at line 193 of file ath5k.h.

#define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT 10000 /* 10 sec */

Definition at line 194 of file ath5k.h.

#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */

Definition at line 196 of file ath5k.h.

#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */

Definition at line 1252 of file ath5k.h.

#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */

Definition at line 1251 of file ath5k.h.

#define ATH5K_WARN	(	_sc,
		_fmt,
		...
	)	ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)

Definition at line 98 of file ath5k.h.

#define ATH_BCBUF 4 /* number of beacon buffers */

Definition at line 1250 of file ath5k.h.

#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)

Definition at line 1245 of file ath5k.h.

#define ATH_RXBUF 40 /* number of RX buffers */

Definition at line 1248 of file ath5k.h.

#define ATH_STAT_INVALID 0 /* disable hardware accesses */

Definition at line 1281 of file ath5k.h.

#define ATH_STAT_LEDSOFT 2 /* enable LED gpio status */

Definition at line 1283 of file ath5k.h.

#define ATH_STAT_PROMISC 1

Definition at line 1282 of file ath5k.h.

#define ATH_STAT_STARTED 3 /* opened & irqs enabled */

Definition at line 1284 of file ath5k.h.

#define ATH_TXBUF 200 /* number of TX buffers */

Definition at line 1249 of file ath5k.h.

#define CHAN_DEBUG 0

Definition at line 24 of file ath5k.h.

#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */

Definition at line 51 of file ath5k.h.

#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */

Definition at line 50 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */

Definition at line 69 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */

Definition at line 46 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */

Definition at line 52 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */

Definition at line 54 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */

Definition at line 48 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */

Definition at line 56 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */

Definition at line 59 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */

Definition at line 58 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */

Definition at line 49 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */

Definition at line 63 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */

Definition at line 64 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */

Definition at line 65 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */

Definition at line 66 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */

Definition at line 67 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */

Definition at line 68 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */

Definition at line 55 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */

Definition at line 57 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */

Definition at line 53 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */

Definition at line 47 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */

Definition at line 60 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */

Definition at line 61 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */

Definition at line 62 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */

Definition at line 70 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */

Definition at line 72 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */

Definition at line 73 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */

Definition at line 71 of file ath5k.h.

#define TSF_TO_TU ( _tsf ) (u32)((_tsf) >> 10)

Definition at line 750 of file ath5k.h.

Enumeration Type Documentation

enum ath5k_ant_mode

enum ath5k_ant_mode - Antenna operation mode : Default antenna setup : Only antenna A is present : Only antenna B is present : STA locked on a single ap : AP with tx antenna set on tx desc : STA with tx antenna set on tx desc : Debug mode -A -> Rx, B-> Tx- : Used for boundary checks

For more infos on antenna control check out phy.c

Enumerator:

AR5K_ANTMODE_DEFAULT
AR5K_ANTMODE_FIXED_A
AR5K_ANTMODE_FIXED_B
AR5K_ANTMODE_SINGLE_AP
AR5K_ANTMODE_SECTOR_AP
AR5K_ANTMODE_SECTOR_STA
AR5K_ANTMODE_DEBUG
AR5K_ANTMODE_MAX

Definition at line 467 of file ath5k.h.

enum ath5k_bw_mode

enum ath5k_bw_mode - Bandwidth operation mode : 20MHz, default operation : Quarter rate : Half rate : Turbo

Enumerator:

AR5K_BWMODE_DEFAULT
AR5K_BWMODE_5MHZ
AR5K_BWMODE_10MHZ
AR5K_BWMODE_40MHZ

Definition at line 485 of file ath5k.h.

enum ath5k_calibration_mask

enum ath5k_calibration_mask - Mask which calibration is active at the moment : Full calibration (AGC + SHORT) : Short calibration (NF + I/Q) : Noise Floor calibration : Adaptive Noise Immunity

Enumerator:

AR5K_CALIBRATION_FULL
AR5K_CALIBRATION_SHORT
AR5K_CALIBRATION_NF
AR5K_CALIBRATION_ANI

Definition at line 1087 of file ath5k.h.

enum ath5k_dmasize

enum ath5k_dmasize - DMA size definitions (2^(n+2)) : 4Bytes : 8Bytes : 16Bytes : 32Bytes : 64Bytes (Default) : 128Bytes : 256Bytes : 512Bytes

These are used to set DMA burst size on hw

Note: Some platforms can't handle more than 4Bytes be careful on embedded boards.

Enumerator:

AR5K_DMASIZE_4B
AR5K_DMASIZE_8B
AR5K_DMASIZE_16B
AR5K_DMASIZE_32B
AR5K_DMASIZE_64B
AR5K_DMASIZE_128B
AR5K_DMASIZE_256B
AR5K_DMASIZE_512B

Definition at line 833 of file ath5k.h.

enum ath5k_driver_mode

DOC: Atheros XR

Some of this information is based on Documentation from:

http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG

Atheros' eXtended Range - range enhancing extension is a modulation scheme that is supposed to double the link distance between an Atheros XR-enabled client device with an Atheros XR-enabled access point. This is achieved by increasing the receiver sensitivity up to, -105dBm, which is about 20dB above what the 802.11 specifications demand. In addition, new (proprietary) data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.

Please note that can you either use XR or TURBO but you cannot use both, they are exclusive.

Also note that we do not plan to support XR mode at least for now. You can get a mode similar to XR by using 5MHz bwmode. DOC: Atheros SuperAG

In addition to XR we have another modulation scheme called TURBO mode that is supposed to provide a throughput transmission speed up to 40Mbit/s -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two 54Mbit/s 802.11g channels. To use this feature both ends must support it. There is also a distinction between "static" and "dynamic" turbo modes:

Static: is the dumb version: devices set to this mode stick to it until the mode is turned off.

Dynamic: is the intelligent version, the network decides itself if it is ok to use turbo. As soon as traffic is detected on adjacent channels (which would get used in turbo mode), or when a non-turbo station joins the network, turbo mode won't be used until the situation changes again. Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which monitors the used radio band in order to decide whether turbo mode may be used or not.

This article claims Super G sticks to bonding of channels 5 and 6 for USA:

http://www.pcworld.com/article/id,113428-page,1/article.html

The channel bonding seems to be driver specific though.

In addition to TURBO modes we also have the following features for even greater speed-up:

Bursting: allows multiple frames to be sent at once, rather than pausing after each frame. Bursting is a standards-compliant feature that can be used with any Access Point.

Fast frames: increases the amount of information that can be sent per frame, also resulting in a reduction of transmission overhead. It is a proprietary feature that needs to be supported by the Access Point.

Compression: data frames are compressed in real time using a Lempel Ziv algorithm. This is done transparently. Once this feature is enabled, compression and decompression takes place inside the chipset, without putting additional load on the host CPU.

As with XR we also don't plan to support SuperAG features for now. You can get a mode similar to TURBO by using 40MHz bwmode. enum ath5k_driver_mode - PHY operation mode : 802.11a : 802.11b : 801.11g : Used for boundary checks

Do not change the order here, we use these as array indices and it also maps EEPROM structures.

Enumerator:

AR5K_MODE_11A
AR5K_MODE_11B
AR5K_MODE_11G
AR5K_MODE_MAX

Definition at line 447 of file ath5k.h.

enum ath5k_int

enum ath5k_int - Hardware interrupt masks helpers : Frame successfully received : Request RX descriptor/Read RX descriptor : Frame reception failed : No frame received within a specified time period : Reached "End Of List", means we need more RX descriptors : Indicates we got RX FIFO overrun. Note that Rx overrun is not always fatal, on some chips we can continue operation without resetting the card, that's why AR5K_INT_FATAL is not common for all chips. : Mask to identify all RX related interrupts

: Frame transmission success : Request TX descriptor/Read TX status descriptor : Frame transmission failure : Received End Of List for VEOL (Virtual End Of List). The Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's LinkPtr is NULL. For more details, refer to: "http://www.freepatentsonline.com/20030225739.html" : No frame was transmitted within a specified time period : Indicates we got TX FIFO underrun. In such case we should increase the TX trigger threshold. : Mask to identify all TX related interrupts

: Indicates the either Management Information Base counters or one of the PHY error counters reached the maximum value and should be read and cleared. : Software triggered interrupt. : RX PHY Error : RX Key cache miss : SoftWare Beacon Alert - indicates its time to send a beacon that must be handled in software. The alternative is if you have VEOL support, in that case you let the hardware deal with things. : Beacon received with an RSSI value below our threshold : If in STA mode this indicates we have stopped seeing beacons from the AP have associated with, we should probably try to reassociate. When in IBSS mode this might mean we have not received any beacons from any local stations. Note that every station in an IBSS schedules to send beacons at the Target Beacon Transmission Time (TBTT) with a random backoff. : Beacon queue got triggered (DMA beacon alert) while empty. : Beacon with local station's TIM bit set : Beacon with DTIM bit and zero DTIM count received : DTIM sync lost : GPIO interrupt is used for RF Kill switches connected to our GPIO pins. : Beacon timeout, we waited after TBTT but got noting : We waited for CAB traffic after the beacon but got nothing or an incomplete CAB frame sequence. : A queue got it's CBR counter expired : A queue got triggered wile empty : A queue got triggered

: Fatal errors were encountered, typically caused by bus/DMA errors. Indicates we need to reset the card. : Used to clear and set the IER : Signals the card has been removed : Common interrupts shared among MACs with the same bit value

These are mapped to take advantage of some common bits between the MACs, to be able to set intr properties easier. Some of them are not used yet inside hw.c. Most map to the respective hw interrupt value as they are common among different MACs.

Enumerator:

AR5K_INT_RXOK
AR5K_INT_RXDESC
AR5K_INT_RXERR
AR5K_INT_RXNOFRM
AR5K_INT_RXEOL
AR5K_INT_RXORN
AR5K_INT_TXOK
AR5K_INT_TXDESC
AR5K_INT_TXERR
AR5K_INT_TXNOFRM
AR5K_INT_TXEOL
AR5K_INT_TXURN
AR5K_INT_MIB
AR5K_INT_SWI
AR5K_INT_RXPHY
AR5K_INT_RXKCM
AR5K_INT_SWBA
AR5K_INT_BRSSI
AR5K_INT_BMISS
AR5K_INT_FATAL
AR5K_INT_BNR
AR5K_INT_TIM
AR5K_INT_DTIM
AR5K_INT_DTIM_SYNC
AR5K_INT_GPIO
AR5K_INT_BCN_TIMEOUT
AR5K_INT_CAB_TIMEOUT
AR5K_INT_QCBRORN
AR5K_INT_QCBRURN
AR5K_INT_QTRIG
AR5K_INT_GLOBAL
AR5K_INT_TX_ALL
AR5K_INT_RX_ALL
AR5K_INT_COMMON
AR5K_INT_NOCARD

Definition at line 1008 of file ath5k.h.

enum ath5k_pkt_type

enum ath5k_pkt_type - Transmit packet types : Normal data : ATIM : PS-Poll : Beacon : Probe response : PIFS Used on tx control descriptor

Enumerator:

AR5K_PKT_TYPE_NORMAL
AR5K_PKT_TYPE_ATIM
AR5K_PKT_TYPE_PSPOLL
AR5K_PKT_TYPE_BEACON
AR5K_PKT_TYPE_PROBE_RESP
AR5K_PKT_TYPE_PIFS

Definition at line 674 of file ath5k.h.

enum ath5k_power_mode

enum ath5k_power_mode - Power management modes : Undefined : Allow card to sleep if possible : Force card to wake up : Force card to full sleep (DANGEROUS) : Allow to sleep for a specified duration

Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO are also known to have problems on some cards. This is not a big problem though because we can have almost the same effect as FULL_SLEEP by putting card on warm reset (it's almost powered down).

Enumerator:

AR5K_PM_UNDEFINED
AR5K_PM_AUTO
AR5K_PM_AWAKE
AR5K_PM_FULL_SLEEP
AR5K_PM_NETWORK_SLEEP

Definition at line 1107 of file ath5k.h.

enum ath5k_radio

enum ath5k_radio - PHY Chips : RF5110 (Fez) : RF5111 (Sombrero) : RF2112/5112(A) (Derby/Derby2) : RF2413/2414 (Griffin/Griffin-Lite) : RF5413/5414/5424 (Eagle/Condor) : RF2315/2316 (Cobra SoC) : RF2317 (Spider SoC) : RF2425/2417 (Swan/Nalla)

Enumerator:

AR5K_RF5110
AR5K_RF5111
AR5K_RF5112
AR5K_RF2413
AR5K_RF5413
AR5K_RF2316
AR5K_RF2317
AR5K_RF2425

Definition at line 295 of file ath5k.h.

enum ath5k_rfgain

enum ath5k_rfgain - RF Gain optimization engine state : Engine disabled : Probe active : Probe requested : Gain_F needs change

Enumerator:

AR5K_RFGAIN_INACTIVE
AR5K_RFGAIN_ACTIVE
AR5K_RFGAIN_READ_REQUESTED
AR5K_RFGAIN_NEED_CHANGE

Definition at line 765 of file ath5k.h.

enum ath5k_tx_queue

enum ath5k_tx_queue - Queue types used to classify tx queues. : q is unused – see ath5k_hw_release_tx_queue : A normal data queue : The beacon queue : The after-beacon queue : Unscheduled Automatic Power Save Delivery queue

Enumerator:

AR5K_TX_QUEUE_INACTIVE
AR5K_TX_QUEUE_DATA
AR5K_TX_QUEUE_BEACON
AR5K_TX_QUEUE_CAB
AR5K_TX_QUEUE_UAPSD

Definition at line 538 of file ath5k.h.

enum ath5k_tx_queue_id

enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions : Data queue on AR5210 (no QCU available) : Beacon queue on AR5210 (no QCU available) : Data queue min index : Data queue max index : Content after beacon queue : Beacon queue : Urgent Automatic Power Save Delivery,

Each number represents a hw queue. If hw does not support hw queues (eg 5210) all data goes in one queue.

Enumerator:

AR5K_TX_QUEUE_ID_NOQCU_DATA
AR5K_TX_QUEUE_ID_NOQCU_BEACON
AR5K_TX_QUEUE_ID_DATA_MIN
AR5K_TX_QUEUE_ID_DATA_MAX
AR5K_TX_QUEUE_ID_UAPSD
AR5K_TX_QUEUE_ID_CAB
AR5K_TX_QUEUE_ID_BEACON

Definition at line 581 of file ath5k.h.

enum ath5k_tx_queue_subtype

enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues : Background traffic : Best-effort (normal) traffic : Video traffic : Voice traffic

These are the 4 Access Categories as defined in WME spec. 0 is the lowest priority and 4 is the highest. Normal data that hasn't been classified goes to the Best Effort AC.

Enumerator:

AR5K_WME_AC_BK
AR5K_WME_AC_BE
AR5K_WME_AC_VI
AR5K_WME_AC_VO

Definition at line 561 of file ath5k.h.

enum ath5k_version

enum ath5k_version - MAC Chips : AR5210 (Crete) : AR5211 (Oahu/Maui) : AR5212 (Venice) and newer

Enumerator:

AR5K_AR5210
AR5K_AR5211
AR5K_AR5212

Definition at line 278 of file ath5k.h.

Function Documentation

void __printf	(	3	,
		4
	)		const

bool ath5k_channel_ok	(	struct ath5k_hw *	ah,
		struct ieee80211_channel *	channel
	)

ath5k_channel_ok() - Check if a channel is supported by the hw : The &struct ath5k_hw : The &struct ieee80211_channel

Note: We don't do any regulatory domain checks here, it's just a sanity check.

Definition at line 136 of file phy.c.

void ath5k_eeprom_detach ( struct ath5k_hw * ah )

Definition at line 1773 of file eeprom.c.

int ath5k_eeprom_init ( struct ath5k_hw * ah )

Definition at line 1745 of file eeprom.c.

bool ath5k_hw_chan_has_spur_noise	(	struct ath5k_hw *	ah,
		struct ieee80211_channel *	channel
	)

ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise : The &struct ath5k_hw : The &struct ieee80211_channel

Definition at line 159 of file phy.c.

bool ath5k_hw_check_beacon_timers	(	struct ath5k_hw *	ah,
		int	intval
	)

ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct : The &struct ath5k_hw : beacon interval

This is a workaround for IBSS mode

The need for this function arises from the fact that we have 4 separate HW timer registers (TIMER0 - TIMER3), which are closely related to the next beacon target time (NBTT), and that the HW updates these timers separately based on the current TSF value. The hardware increments each timer by the beacon interval, when the local TSF converted to TU is equal to the value stored in the timer.

The reception of a beacon with the same BSSID can update the local HW TSF at any time - this is something we can't avoid. If the TSF jumps to a time which is later than the time stored in a timer, this timer will not be updated until the TSF in TU wraps around at 16 bit (the size of the timers) and reaches the time which is stored in the timer.

The problem is that these timers are closely related to TIMER0 (NBTT) and that they define a time "window". When the TSF jumps between two timers (e.g. ATIM and NBTT), the one in the past will be left behind (not updated), while the one in the future will be updated every beacon interval. This causes the window to get larger, until the TSF wraps around as described above and the timer which was left behind gets updated again. But - because the beacon interval is usually not an exact divisor of the size of the timers (16 bit), an unwanted "window" between these timers has developed!

This is especially important with the ATIM window, because during the ATIM window only ATIM frames and no data frames are allowed to be sent, which creates transmission pauses after each beacon. This symptom has been described as "ramping ping" because ping times increase linearly for some time and then drop down again. A wrong window on the DMA beacon timer has the same effect, so we check for these two conditions.

Returns true if O.K.

Definition at line 793 of file pcu.c.

unsigned int ath5k_hw_clocktoh	(	struct ath5k_hw *	ah,
		unsigned int	clock
	)

ath5k_hw_clocktoh() - Translate hw clock units to usec : The &struct ath5k_hw : value in hw clock units

Translate hw clock units to usecs based on the current hw clock rate.

Returns number of usecs

Definition at line 118 of file reset.c.

void ath5k_hw_deinit ( struct ath5k_hw * ah )

ath5k_hw_deinit() - Free the &struct ath5k_hw : The &struct ath5k_hw

Definition at line 350 of file attach.c.

int ath5k_hw_disable_pspoll ( struct ath5k_hw * ah )

Definition at line 145 of file caps.c.

void ath5k_hw_dma_init ( struct ath5k_hw * ah )

ath5k_hw_dma_init() - Initialize DMA unit : The &struct ath5k_hw

Set DMA size and pre-enable interrupts (driver handles tx/rx buffer setup and dma start/stop)

XXX: Save/restore RXDP/TXDP registers ?

Definition at line 847 of file dma.c.

int ath5k_hw_dma_stop ( struct ath5k_hw * ah )

ath5k_hw_dma_stop() - stop DMA unit : The &struct ath5k_hw

Stop tx/rx DMA and interrupts. Returns -EBUSY if tx or rx dma failed to stop.

XXX: Sometimes DMA unit hangs and we have stuck frames on tx queues, only a reset can fix that.

Definition at line 887 of file dma.c.

int ath5k_hw_enable_pspoll	(	struct ath5k_hw *	ah,
		u8 *	bssid,
		u16	assoc_id
	)

Definition at line 133 of file caps.c.

enum ath5k_rfgain ath5k_hw_gainf_calibrate ( struct ath5k_hw * ah )

ath5k_hw_gainf_calibrate() - Do a gain_F calibration : The &struct ath5k_hw

Main callback for thermal RF gain calibration engine Check for a new gain reading and schedule an adjustment if needed.

Returns one of enum ath5k_rfgain codes

Definition at line 683 of file phy.c.

unsigned int ath5k_hw_get_default_sifs ( struct ath5k_hw * ah )

ath5k_hw_get_default_sifs() - Get the default SIFS for current mode : The &struct ath5k_hw

Definition at line 204 of file pcu.c.

unsigned int ath5k_hw_get_default_slottime ( struct ath5k_hw * ah )

ath5k_hw_get_default_slottime() - Get the default slot time for current mode : The &struct ath5k_hw

Definition at line 173 of file pcu.c.

int ath5k_hw_get_frame_duration	(	struct ath5k_hw *	ah,
		enum ieee80211_band	band,
		int	len,
		struct ieee80211_rate *	rate,
		bool	shortpre
	)

Definition at line 113 of file pcu.c.

u32 ath5k_hw_get_gpio	(	struct ath5k_hw *	ah,
		u32	gpio
	)

ath5k_hw_get_gpio() - Get GPIO state : The &struct ath5k_hw : The GPIO pin to read

Definition at line 142 of file gpio.c.

int ath5k_hw_get_isr	(	struct ath5k_hw *	ah,
		enum ath5k_int *	interrupt_mask
	)

Definition at line 527 of file dma.c.

u32 ath5k_hw_get_rx_filter ( struct ath5k_hw * ah )

ath5k_hw_get_rx_filter() - Get current rx filter : The &struct ath5k_hw

Returns the RX filter by reading rx filter and phy error filter registers. RX filter is used to set the allowed frame types that PCU will accept and pass to the driver. For a list of frame types check out reg.h.

Definition at line 480 of file pcu.c.

u32 ath5k_hw_get_rxdp ( struct ath5k_hw * ah )

ath5k_hw_get_rxdp() - Get RX Descriptor's address : The &struct ath5k_hw

Definition at line 85 of file dma.c.

u64 ath5k_hw_get_tsf64 ( struct ath5k_hw * ah )

ath5k_hw_get_tsf64() - Get the full 64bit TSF : The &struct ath5k_hw

Returns the current TSF

Definition at line 559 of file pcu.c.

int ath5k_hw_get_tx_queueprops	(	struct ath5k_hw *	ah,
		int	queue,
		struct ath5k_txq_info *	queue_info
	)

ath5k_hw_get_tx_queueprops() - Get properties for a transmit queue : The &struct ath5k_hw : One of enum ath5k_tx_queue_id : The &struct ath5k_txq_info to fill

Definition at line 138 of file qcu.c.

u32 ath5k_hw_get_txdp	(	struct ath5k_hw *	ah,
		unsigned int	queue
	)

ath5k_hw_get_txdp() - Get TX Descriptor's address for a specific queue : The &struct ath5k_hw : The hw queue number

Get TX descriptor's address for a specific queue. For 5210 we ignore the queue number and use tx queue type since we only have 2 queues. We use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just read the corresponding TXDP register.

XXX: Is TXDP read and clear ?

Definition at line 353 of file dma.c.

unsigned int ath5k_hw_htoclock	(	struct ath5k_hw *	ah,
		unsigned int	usec
	)

ath5k_hw_htoclock() - Translate usec to hw clock units : The &struct ath5k_hw : value in microseconds

Translate usecs to hw clock units based on the current hw clock rate.

Returns number of clock units

Definition at line 101 of file reset.c.

int ath5k_hw_init ( struct ath5k_hw * ah )

ath5k_hw_init() - Check if hw is supported and init the needed structs : The &struct ath5k_hw associated with the device

Check if the device is supported, perform a POST and initialize the needed structs. Returns -ENOMEM if we don't have memory for the needed structs, -ENODEV if the device is not supported or prints an error msg if something else went wrong.

Definition at line 104 of file attach.c.

void ath5k_hw_init_beacon_timers	(	struct ath5k_hw *	ah,
		u32	next_beacon,
		u32	interval
	)

ath5k_hw_init_beacon_timers() - Initialize beacon timers : The &struct ath5k_hw : Next TBTT : Current beacon interval

This function is used to initialize beacon timers based on current operation mode and settings.

Definition at line 645 of file pcu.c.

int ath5k_hw_init_desc_functions ( struct ath5k_hw * ah )

ath5k_hw_init_desc_functions() - Init function pointers inside ah : The &struct ath5k_hw

Maps the internal descriptor functions to the function pointers on ah, used from above. This is used as an abstraction layer to handle the various chips the same way.

Definition at line 773 of file desc.c.

void ath5k_hw_init_nfcal_hist ( struct ath5k_hw * ah )

ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer : The &struct ath5k_hw

Definition at line 1540 of file phy.c.

int ath5k_hw_init_queues ( struct ath5k_hw * ah )

ath5k_hw_init_queues() - Initialize tx queues : The &struct ath5k_hw

Initializes all tx queues based on information on ah->ah_txq* set by the driver

Definition at line 673 of file qcu.c.

bool ath5k_hw_is_intr_pending ( struct ath5k_hw * ah )

ath5k_hw_is_intr_pending() - Check if we have pending interrupts : The &struct ath5k_hw

Check if we have pending interrupts to process. Returns 1 if we have pending interrupts and 0 if we haven't.

Definition at line 506 of file dma.c.

int ath5k_hw_nic_wakeup	(	struct ath5k_hw *	ah,
		struct ieee80211_channel *	channel
	)

ath5k_hw_nic_wakeup() - Force card out of sleep : The &struct ath5k_hw : The &struct ieee80211_channel

Bring up MAC + PHY Chips and program PLL NOTE: Channel is NULL for the initial wakeup.

Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos

Definition at line 669 of file reset.c.

u32 ath5k_hw_num_tx_pending	(	struct ath5k_hw *	ah,
		unsigned int	queue
	)

DOC: Queue Control Unit (QCU)/DCF Control Unit (DCU) functions

Here we setup parameters for the 12 available TX queues. Note that on the various registers we can usually only map the first 10 of them so basically we have 10 queues to play with. Each queue has a matching QCU that controls when the queue will get triggered and multiple QCUs can be mapped to a single DCU that controls the various DFS parameters for the various queues. In our setup we have a 1:1 mapping between QCUs and DCUs allowing us to have different DFS settings for each queue.

When a frame goes into a TX queue, QCU decides when it'll trigger a transmission based on various criteria (such as how many data we have inside it's buffer or -if it's a beacon queue- if it's time to fire up the queue based on TSF etc), DCU adds backoff, IFSes etc and then a scheduler (arbitrator) decides the priority of each QCU based on it's configuration (e.g. beacons are always transmitted when they leave DCU bypassing all other frames from other queues waiting to be transmitted). After a frame leaves the DCU it goes to PCU for further processing and then to PHY for the actual transmission. ath5k_hw_num_tx_pending() - Get number of pending frames for a given queue : The &struct ath5k_hw : One of enum ath5k_tx_queue_id

Definition at line 63 of file qcu.c.

int ath5k_hw_on_hold ( struct ath5k_hw * ah )

ath5k_hw_on_hold() - Put device on hold : The &struct ath5k_hw

Put MAC and Baseband on warm reset and keep that state (don't clean sleep control register). After this MAC and Baseband are disabled and a full reset is needed to come back. This way we save as much power as possible without putting the card on full sleep.

Returns 0 on success or -EIO on error

Definition at line 607 of file reset.c.

void ath5k_hw_pcu_init	(	struct ath5k_hw *	ah,
		enum nl80211_iftype	op_mode
	)

ath5k_hw_pcu_init() - Initialize PCU : The &struct ath5k_hw : One of enum nl80211_iftype : One of enum ath5k_driver_mode

This function is used to initialize PCU by setting current operation mode and various other settings.

Definition at line 950 of file pcu.c.

int ath5k_hw_phy_calibrate	(	struct ath5k_hw *	ah,
		struct ieee80211_channel *	channel
	)

ath5k_hw_phy_calibrate() - Perform a PHY calibration : The &struct ath5k_hw : The &struct ieee80211_channel

The main function we call from above to perform a short or full PHY calibration based on RF chip and current channel

Definition at line 1857 of file phy.c.

int ath5k_hw_phy_disable ( struct ath5k_hw * ah )

ath5k_hw_phy_disable() - Disable PHY : The &struct ath5k_hw

Definition at line 349 of file phy.c.

int ath5k_hw_phy_init	(	struct ath5k_hw *	ah,
		struct ieee80211_channel *	channel,
		u8	mode,
		bool	fast
	)

Definition at line 3765 of file phy.c.

u16 ath5k_hw_radio_revision	(	struct ath5k_hw *	ah,
		enum ieee80211_band	band
	)

DOC: PHY related functions

Here we handle the low-level functions related to baseband and analog frontend (RF) parts. This is by far the most complex part of the hw code so make sure you know what you are doing.

Here is a list of what this is all about:

Channel setting/switching

Automatic Gain Control (AGC) calibration

Noise Floor calibration

I/Q imbalance calibration (QAM correction)

Calibration due to thermal changes (gain_F)

Spur noise mitigation

RF/PHY initialization for the various operating modes and bwmodes

Antenna control

TX power control per channel/rate/packet type

Also have in mind we never got documentation for most of these functions, what we have comes mostly from Atheros's code, reverse engineering and patent docs/presentations etc. ath5k_hw_radio_revision() - Get the PHY Chip revision : The &struct ath5k_hw : One of enum ieee80211_band

Returns the revision number of a 2GHz, 5GHz or single chip radio.

Definition at line 84 of file phy.c.

int ath5k_hw_read_srev ( struct ath5k_hw * ah )

Definition at line 57 of file ahb.c.

int ath5k_hw_register_timeout	(	struct ath5k_hw *	ah,
		u32	reg,
		u32	flag,
		u32	val,
		bool	is_set
	)

DOC: Reset function and helpers

Here we implement the main reset routine, used to bring the card to a working state and ready to receive. We also handle routines that don't fit on other places such as clock, sleep and power control ath5k_hw_register_timeout() - Poll a register for a flag/field change : The &struct ath5k_hw : The register to read : The flag/field to check on the register : The field value we expect (if we check a field) : Instead of checking if the flag got cleared, check if it got set

Some registers contain flags that indicate that an operation is running. We use this function to poll these registers and check if these flags get cleared. We also use it to poll a register field (containing multiple flags) until it gets a specific value.

Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0

Definition at line 67 of file reset.c.

void ath5k_hw_release_tx_queue	(	struct ath5k_hw *	ah,
		unsigned int	queue
	)

ath5k_hw_release_tx_queue() - Set a transmit queue inactive : The &struct ath5k_hw : One of enum ath5k_tx_queue_id

Definition at line 94 of file qcu.c.

int ath5k_hw_reset	(	struct ath5k_hw *	ah,
		enum nl80211_iftype	op_mode,
		struct ieee80211_channel *	channel,
		bool	fast,
		bool	skip_pcu
	)

ath5k_hw_reset() - The main reset function : The &struct ath5k_hw : One of enum nl80211_iftype : The &struct ieee80211_channel : Enable fast channel switching : Skip pcu initialization

This is the function we call each time we want to (re)initialize the card and pass new settings to hw. We also call it when hw runs into trouble to make it come back to a working state.

Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO on failure.

Definition at line 1146 of file reset.c.

void ath5k_hw_reset_tsf ( struct ath5k_hw * ah )

ath5k_hw_reset_tsf() - Force a TSF reset : The &struct ath5k_hw

Forces a TSF reset on PCU

Definition at line 619 of file pcu.c.

int ath5k_hw_reset_tx_queue	(	struct ath5k_hw *	ah,
		unsigned int	queue
	)

ath5k_hw_reset_tx_queue() - Initialize a single hw queue : The &struct ath5k_hw : One of enum ath5k_tx_queue_id

Set DCF properties for the given transmit queue on DCU and configures all queue-specific parameters.

Definition at line 330 of file qcu.c.

int ath5k_hw_rfgain_opt_init ( struct ath5k_hw * ah )

DOC: RF Gain optimization

This code is used to optimize RF gain on different environments (temperature mostly) based on feedback from a power detector.

It's only used on RF5111 and RF5112, later RF chips seem to have auto adjustment on hw -notice they have a much smaller BANK 7 and no gain optimization ladder-.

For more infos check out this patent doc "http://www.freepatentsonline.com/7400691.html"

This paper describes power drops as seen on the receiver due to probe packets "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues %20of%20Power%20Control.pdf"

And this is the MadWiFi bug entry related to the above "http://madwifi-project.org/ticket/1659" with various measurements and diagrams ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach : The &struct ath5k_hw

Definition at line 420 of file phy.c.

void ath5k_hw_set_antenna_mode	(	struct ath5k_hw *	ah,
		u8	ant_mode
	)

ath5k_hw_set_antenna_mode() - Set antenna operating mode : The &struct ath5k_hw : One of enum ath5k_ant_mode

Definition at line 2298 of file phy.c.

void ath5k_hw_set_antenna_switch	(	struct ath5k_hw *	ah,
		u8	ee_mode
	)

ath5k_hw_set_antenna_switch() - Set up antenna switch table : The &struct ath5k_hw : One of enum ath5k_driver_mode

Switch table comes from EEPROM and includes information on controlling the 2 antenna RX attenuators

Definition at line 2262 of file phy.c.

void ath5k_hw_set_bssid ( struct ath5k_hw * ah )

ath5k_hw_set_bssid() - Set current BSSID on hw : The &struct ath5k_hw

Sets the current BSSID and BSSID mask we have from the common struct into the hardware

Definition at line 396 of file pcu.c.

void ath5k_hw_set_bssid_mask	(	struct ath5k_hw *	ah,
		const u8 *	mask
	)

ath5k_hw_set_bssid_mask() - Filter out bssids we listen : The &struct ath5k_hw : The BSSID mask to set (array of octets)

BSSID masking is a method used by AR5212 and newer hardware to inform PCU which bits of the interface's MAC address should be looked at when trying to decide which packets to ACK. In station mode and AP mode with a single BSS every bit matters since we lock to only one BSS. In AP mode with multiple BSSes (virtual interfaces) not every bit matters because hw must accept frames for all BSSes and so we tweak some bits of our mac address in order to have multiple BSSes.

For more information check out ../hw.c of the common ath module.

Definition at line 445 of file pcu.c.

int ath5k_hw_set_capabilities ( struct ath5k_hw * ah )

Definition at line 33 of file caps.c.

void ath5k_hw_set_clockrate ( struct ath5k_hw * ah )

void ath5k_hw_set_coverage_class	(	struct ath5k_hw *	ah,
		u8	coverage_class
	)

ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class : The &struct ath5k_hw : IEEE 802.11 coverage class number

Sets IFS intervals and ACK/CTS timeouts for given coverage class.

Definition at line 820 of file pcu.c.

int ath5k_hw_set_gpio	(	struct ath5k_hw *	ah,
		u32	gpio,
		u32	val
	)

ath5k_hw_set_gpio() - Set GPIO state : The &struct ath5k_hw : The GPIO pin to set : Value to set (boolean)

Definition at line 159 of file gpio.c.

int ath5k_hw_set_gpio_input	(	struct ath5k_hw *	ah,
		u32	gpio
	)

ath5k_hw_set_gpio_input() - Set GPIO inputs : The &struct ath5k_hw : GPIO pin to set as input

Definition at line 106 of file gpio.c.

void ath5k_hw_set_gpio_intr	(	struct ath5k_hw *	ah,
		unsigned int	gpio,
		u32	interrupt_level
	)

ath5k_hw_set_gpio_intr() - Initialize the GPIO interrupt (RFKill switch) : The &struct ath5k_hw : The GPIO pin to use : True to generate interrupt on active pin (high)

This function is used to set up the GPIO interrupt for the hw RFKill switch. That switch is connected to a GPIO pin and it's number is stored on EEPROM. It can either open or close the circuit to indicate that we should disable RF/Wireless to save power (we also get that from EEPROM).

Definition at line 189 of file gpio.c.

int ath5k_hw_set_gpio_output	(	struct ath5k_hw *	ah,
		u32	gpio
	)

ath5k_hw_set_gpio_output() - Set GPIO outputs : The &struct ath5k_hw : The GPIO pin to set as output

Definition at line 124 of file gpio.c.

int ath5k_hw_set_ifs_intervals	(	struct ath5k_hw *	ah,
		unsigned int	slot_time
	)

ath5k_hw_set_ifs_intervals() - Set global inter-frame spaces on DCU : The &struct ath5k_hw : Slot time in us

Sets the global IFS intervals on DCU (also works on AR5210) for the given slot time and the current bwmode.

Definition at line 565 of file qcu.c.

enum ath5k_int ath5k_hw_set_imr	(	struct ath5k_hw *	ah,
		enum ath5k_int	new_mask
	)

ath5k_hw_set_imr() - Set interrupt mask : The &struct ath5k_hw : The new interrupt mask to be set

Set the interrupt mask in hw to save interrupts. We do that by mapping ath5k_int bits to hw-specific bits to remove abstraction and writing Interrupt Mask Register.

Definition at line 746 of file dma.c.

void ath5k_hw_set_ledstate	(	struct ath5k_hw *	ah,
		unsigned int	state
	)

DOC: GPIO/LED functions

Here we control the 6 bidirectional GPIO pins provided by the hw. We can set a GPIO pin to be an input or an output pin on GPIO control register and then read or set its status from GPIO data input/output registers.

We also control the two LED pins provided by the hw, LED_0 is our "power" LED and LED_1 is our "network activity" LED but many scenarios are available from hw. Vendors might also provide LEDs connected to the GPIO pins, we handle them through the LED subsystem on led.c ath5k_hw_set_ledstate() - Set led state : The &struct ath5k_hw : One of AR5K_LED_*

Used to set the LED blinking state. This only works for the LED connected to the LED_0, LED_1 pins, not the GPIO based.

Definition at line 53 of file gpio.c.

int ath5k_hw_set_lladdr	(	struct ath5k_hw *	ah,
		const u8 *	mac
	)

ath5k_hw_set_lladdr() - Set station id : The &struct ath5k_hw : The card's mac address (array of octets)

Set station id on hw using the provided mac address

Definition at line 368 of file pcu.c.

void ath5k_hw_set_mcast_filter	(	struct ath5k_hw *	ah,
		u32	filter0,
		u32	filter1
	)

ath5k_hw_set_mcast_filter() - Set multicast filter : The &struct ath5k_hw : Lower 32bits of muticast filter : Higher 16bits of multicast filter

Definition at line 463 of file pcu.c.

int ath5k_hw_set_opmode	(	struct ath5k_hw *	ah,
		enum nl80211_iftype	op_mode
	)

ath5k_hw_set_opmode() - Set PCU operating mode : The &struct ath5k_hw : One of enum nl80211_iftype

Configure PCU for the various operating modes (AP/STA etc)

Definition at line 873 of file pcu.c.

void ath5k_hw_set_rx_filter	(	struct ath5k_hw *	ah,
		u32	filter
	)

ath5k_hw_set_rx_filter() - Set rx filter : The &struct ath5k_hw : RX filter mask (see reg.h)

Sets RX filter register and also handles PHY error filter register on 5212 and newer chips so that we have proper PHY error reporting.

Definition at line 509 of file pcu.c.

int ath5k_hw_set_rxdp	(	struct ath5k_hw *	ah,
		u32	phys_addr
	)

ath5k_hw_set_rxdp() - Set RX Descriptor's address : The &struct ath5k_hw : RX descriptor address

Returns -EIO if rx is active

Definition at line 98 of file dma.c.

void ath5k_hw_set_tsf64	(	struct ath5k_hw *	ah,
		u64	tsf64
	)

ath5k_hw_set_tsf64() - Set a new 64bit TSF : The &struct ath5k_hw : The new 64bit TSF

Sets the new TSF

Definition at line 606 of file pcu.c.

int ath5k_hw_set_tx_queueprops	(	struct ath5k_hw *	ah,
		int	queue,
		const struct ath5k_txq_info *	qinfo
	)

ath5k_hw_set_tx_queueprops() - Set properties for a transmit queue : The &struct ath5k_hw : One of enum ath5k_tx_queue_id : The &struct ath5k_txq_info to use

Returns 0 on success or -EIO if queue is inactive

Definition at line 154 of file qcu.c.

void ath5k_hw_set_tx_retry_limits	(	struct ath5k_hw *	ah,
		unsigned int	queue
	)

ath5k_hw_set_tx_retry_limits() - Set tx retry limits on DCU : The &struct ath5k_hw : One of enum ath5k_tx_queue_id

This function is used when initializing a queue, to set retry limits based on ah->ah_retry_* and the chipset used.

Definition at line 287 of file qcu.c.

int ath5k_hw_set_txdp	(	struct ath5k_hw *	ah,
		unsigned int	queue,
		u32	phys_addr
	)

ath5k_hw_set_txdp() - Set TX Descriptor's address for a specific queue : The &struct ath5k_hw : The hw queue number : The physical address

Set TX descriptor's address for a specific queue. For 5210 we ignore the queue number and we use tx queue type since we only have 2 queues so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just set the corresponding TXDP register. Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still active.

Definition at line 396 of file dma.c.

int ath5k_hw_set_txpower_limit	(	struct ath5k_hw *	ah,
		u8	txpower
	)

ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel : The &struct ath5k_hw : The requested tx power limit in 0.5dB steps

This function provides access to ath5k_hw_txpower to the driver in case user or an application changes it while PHY is running.

Definition at line 3738 of file phy.c.

int ath5k_hw_setup_mrr_tx_desc	(	struct ath5k_hw *	ah,
		struct ath5k_desc *	desc,
		u_int	tx_rate1,
		u_int	tx_tries1,
		u_int	tx_rate2,
		u_int	tx_tries2,
		u_int	tx_rate3,
		u_int	tx_tries3
	)

ath5k_hw_setup_mrr_tx_desc() - Initialize an MRR tx control descriptor : The &struct ath5k_hw : The &struct ath5k_desc : HW idx for rate used on transmission series 1 : Max number of retransmissions for transmission series 1 : HW idx for rate used on transmission series 2 : Max number of retransmissions for transmission series 2 : HW idx for rate used on transmission series 3 : Max number of retransmissions for transmission series 3

Multi rate retry (MRR) tx control descriptors are available only on AR5212 MACs, they are part of the normal 4-word tx control descriptor (see above) but we handle them through a separate function for better abstraction.

Returns 0 on success or -EINVAL on invalid input

Definition at line 379 of file desc.c.

int ath5k_hw_setup_rx_desc	(	struct ath5k_hw *	ah,
		struct ath5k_desc *	desc,
		u32	size,
		unsigned int	flags
	)

ath5k_hw_setup_rx_desc() - Initialize an rx control descriptor : The &struct ath5k_hw : The &struct ath5k_desc : RX buffer length in bytes : One of AR5K_RXDESC_* flags

Definition at line 559 of file desc.c.

int ath5k_hw_setup_tx_queue	(	struct ath5k_hw *	ah,
		enum ath5k_tx_queue	queue_type,
		struct ath5k_txq_info *	queue_info
	)

ath5k_hw_setup_tx_queue() - Initialize a transmit queue : The &struct ath5k_hw : One of enum ath5k_tx_queue : The &struct ath5k_txq_info to use

Returns 0 on success, -EINVAL on invalid arguments

Definition at line 203 of file qcu.c.

void ath5k_hw_start_rx_dma ( struct ath5k_hw * ah )

ath5k_hw_start_rx_dma() - Start DMA receive : The &struct ath5k_hw

Definition at line 48 of file dma.c.

void ath5k_hw_start_rx_pcu ( struct ath5k_hw * ah )

ath5k_hw_start_rx_pcu() - Start RX engine : The &struct ath5k_hw

Starts RX engine on PCU so that hw can process RXed frames (ACK etc).

NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma

Definition at line 848 of file pcu.c.

int ath5k_hw_start_tx_dma	(	struct ath5k_hw *	ah,
		unsigned int	queue
	)

ath5k_hw_start_tx_dma() - Start DMA transmit for a specific queue : The &struct ath5k_hw : The hw queue number

Start DMA transmit for a specific queue and since 5210 doesn't have QCU/DCU, set up queue parameters for 5210 here based on queue type (one queue for normal data and one queue for beacons). For queue setup on newer chips check out qcu.c. Returns -EINVAL if queue number is out of range or if queue is already disabled.

NOTE: Must be called after setting up tx control descriptor for that queue (see below).

Definition at line 130 of file dma.c.

int ath5k_hw_stop_beacon_queue	(	struct ath5k_hw *	ah,
		unsigned int	queue
	)

ath5k_hw_stop_beacon_queue() - Stop beacon queue : The &struct ath5k_hw : The queue number

Returns -EIO if queue didn't stop

Definition at line 328 of file dma.c.

void ath5k_hw_stop_rx_pcu ( struct ath5k_hw * ah )

at5k_hw_stop_rx_pcu() - Stop RX engine : The &struct ath5k_hw

Stops RX engine on PCU

Definition at line 860 of file pcu.c.

void ath5k_hw_update_mib_counters ( struct ath5k_hw * ah )

ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics) : The &struct ath5k_hw

Reads MIB counters from PCU and updates sw statistics. Is called after a MIB interrupt, because one of these counters might have reached their maximum and triggered the MIB interrupt, to let us read and clear the counter.

NOTE: Is called in interrupt context!

Definition at line 241 of file pcu.c.

void ath5k_hw_update_noise_floor ( struct ath5k_hw * ah )

ath5k_hw_update_noise_floor() - Update NF on hardware : The &struct ath5k_hw

This is the main function we call to perform a NF calibration, it reads NF from hardware, calculates the median and updates NF on hw.

Definition at line 1598 of file phy.c.

int ath5k_hw_update_tx_triglevel	(	struct ath5k_hw *	ah,
		bool	increase
	)

ath5k_hw_update_tx_triglevel() - Update tx trigger level : The &struct ath5k_hw : Flag to force increase of trigger level

This function increases/decreases the tx trigger level for the tx fifo buffer (aka FIFO threshold) that is used to indicate when PCU flushes the buffer and transmits its data. Lowering this results sending small frames more quickly but can lead to tx underruns, raising it a lot can result other problems. Right now we start with the lowest possible (64Bytes) and if we get tx underrun we increase it using the increase flag. Returns -EIO if we have reached maximum/minimum.

XXX: Link this with tx DMA size ? XXX2: Use it to save interrupts ?

Definition at line 453 of file dma.c.

int ath5k_hw_write_initvals	(	struct ath5k_hw *	ah,
		u8	mode,
		bool	skip_pcu
	)

ath5k_hw_write_initvals() - Write initial chip-specific register dump : The &struct ath5k_hw : One of enum ath5k_driver_mode : Skip PCU registers

Write initial chip-specific register dump, to get the chipset on a clean and ready-to-work state after warm reset.

Definition at line 1440 of file initvals.c.

int ath5k_init_leds ( struct ath5k_hw * ah )

Definition at line 161 of file led.c.

void ath5k_led_enable ( struct ath5k_hw * ah )

Definition at line 90 of file led.c.

void ath5k_led_off ( struct ath5k_hw * ah )

Definition at line 105 of file led.c.

void ath5k_rfkill_hw_start ( struct ath5k_hw * ah )

Definition at line 87 of file rfkill.c.

void ath5k_rfkill_hw_stop ( struct ath5k_hw * ah )

Definition at line 105 of file rfkill.c.

int ath5k_sysfs_register ( struct ath5k_hw * ah )

Definition at line 102 of file sysfs.c.

void ath5k_sysfs_unregister ( struct ath5k_hw * ah )

Definition at line 117 of file sysfs.c.

void ath5k_unregister_leds ( struct ath5k_hw * ah )

Definition at line 155 of file led.c.

Variable Documentation

struct ieee80211_ops ath5k_hw_ops

Definition at line 788 of file mac80211-ops.c.

bool ath5k_modparam_nohwcrypt

Definition at line 73 of file base.c.

void const char const char* fmt

Definition at line 83 of file ath5k.h.

void const char* level

Definition at line 83 of file ath5k.h.

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation