Linux Kernel  3.7.1
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reg.c
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1 #include "wbhal.h"
2 #include "wb35reg_f.h"
3 #include "core.h"
4 
5 /*
6  * ====================================================
7  * Original Phy.h
8  * ====================================================
9  */
10 
11 /*
12  * ====================================================
13  * For MAXIM2825/6/7 Ver. 331 or more
14  *
15  * 0x00 0x000a2
16  * 0x01 0x21cc0
17  * 0x02 0x13802
18  * 0x02 0x1383a
19  *
20  * channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333;
21  * channe1 02 ; 0x03 0x32141 ; 0x04 0x08444;
22  * channe1 03 ; 0x03 0x32143 ; 0x04 0x0aeee;
23  * channe1 04 ; 0x03 0x32142 ; 0x04 0x0b333;
24  * channe1 05 ; 0x03 0x31141 ; 0x04 0x08444;
25  * channe1 06 ; 0x03 0x31143 ; 0x04 0x0aeee;
26  * channe1 07 ; 0x03 0x31142 ; 0x04 0x0b333;
27  * channe1 08 ; 0x03 0x33141 ; 0x04 0x08444;
28  * channe1 09 ; 0x03 0x33143 ; 0x04 0x0aeee;
29  * channe1 10 ; 0x03 0x33142 ; 0x04 0x0b333;
30  * channe1 11 ; 0x03 0x30941 ; 0x04 0x08444;
31  * channe1 12 ; 0x03 0x30943 ; 0x04 0x0aeee;
32  * channe1 13 ; 0x03 0x30942 ; 0x04 0x0b333;
33  *
34  * 0x05 0x28986
35  * 0x06 0x18008
36  * 0x07 0x38400
37  * 0x08 0x05100; 100 Hz DC
38  * 0x08 0x05900; 30 KHz DC
39  * 0x09 0x24f08
40  * 0x0a 0x17e00, 0x17ea0
41  * 0x0b 0x37d80
42  * 0x0c 0x0c900 -- 0x0ca00 (lager power 9db than 0x0c000), 0x0c000
43  */
44 
45 /* MAX2825 (pure b/g) */
46 u32 max2825_rf_data[] = {
47  (0x00<<18) | 0x000a2,
48  (0x01<<18) | 0x21cc0,
49  (0x02<<18) | 0x13806,
50  (0x03<<18) | 0x30142,
51  (0x04<<18) | 0x0b333,
52  (0x05<<18) | 0x289A6,
53  (0x06<<18) | 0x18008,
54  (0x07<<18) | 0x38000,
55  (0x08<<18) | 0x05100,
56  (0x09<<18) | 0x24f08,
57  (0x0A<<18) | 0x14000,
58  (0x0B<<18) | 0x37d80,
59  (0x0C<<18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
60 };
61 
62 u32 max2825_channel_data_24[][3] = {
63  {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 01 */
64  {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 02 */
65  {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 03 */
66  {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 04 */
67  {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 05 */
68  {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 06 */
69  {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 07 */
70  {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 08 */
71  {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 09 */
72  {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 10 */
73  {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 11 */
74  {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 12 */
75  {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 13 */
76  {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
77 };
78 
79 u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
80 
81 /* ========================================== */
82 /* MAX2827 (a/b/g) */
83 u32 max2827_rf_data[] = {
84  (0x00 << 18) | 0x000a2,
85  (0x01 << 18) | 0x21cc0,
86  (0x02 << 18) | 0x13806,
87  (0x03 << 18) | 0x30142,
88  (0x04 << 18) | 0x0b333,
89  (0x05 << 18) | 0x289A6,
90  (0x06 << 18) | 0x18008,
91  (0x07 << 18) | 0x38000,
92  (0x08 << 18) | 0x05100,
93  (0x09 << 18) | 0x24f08,
94  (0x0A << 18) | 0x14000,
95  (0x0B << 18) | 0x37d80,
96  (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
97 };
98 
99 u32 max2827_channel_data_24[][3] = {
100  {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
101  {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
102  {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
103  {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */
104  {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */
105  {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */
106  {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */
107  {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */
108  {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */
109  {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */
110  {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */
111  {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */
112  {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */
113  {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
114 };
115 
116 u32 max2827_channel_data_50[][3] = {
117  {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 36 */
118  {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 40 */
119  {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}, /* channel 44 */
120  {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2A9A6}, /* channel 48 */
121  {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x2A9A6}, /* channel 52 */
122  {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 56 */
123  {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 60 */
124  {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6} /* channel 64 */
125 };
126 
127 u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100};
128 u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300};
129 
130 /* ======================================================= */
131 /* MAX2828 (a/b/g) */
132 u32 max2828_rf_data[] = {
133  (0x00 << 18) | 0x000a2,
134  (0x01 << 18) | 0x21cc0,
135  (0x02 << 18) | 0x13806,
136  (0x03 << 18) | 0x30142,
137  (0x04 << 18) | 0x0b333,
138  (0x05 << 18) | 0x289A6,
139  (0x06 << 18) | 0x18008,
140  (0x07 << 18) | 0x38000,
141  (0x08 << 18) | 0x05100,
142  (0x09 << 18) | 0x24f08,
143  (0x0A << 18) | 0x14000,
144  (0x0B << 18) | 0x37d80,
145  (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
146 };
147 
148 u32 max2828_channel_data_24[][3] = {
149  {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
150  {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
151  {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
152  {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */
153  {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */
154  {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */
155  {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */
156  {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */
157  {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */
158  {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */
159  {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */
160  {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */
161  {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */
162  {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
163 };
164 
165 u32 max2828_channel_data_50[][3] = {
166  {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 36 */
167  {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 40 */
168  {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 44 */
169  {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}, /* channel 48 */
170  {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x289A6}, /* channel 52 */
171  {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 56 */
172  {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 60 */
173  {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6} /* channel 64 */
174 };
175 
176 u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
177 u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
178 
179 /* ========================================================== */
180 /* MAX2829 (a/b/g) */
181 u32 max2829_rf_data[] = {
182  (0x00 << 18) | 0x000a2,
183  (0x01 << 18) | 0x23520,
184  (0x02 << 18) | 0x13802,
185  (0x03 << 18) | 0x30142,
186  (0x04 << 18) | 0x0b333,
187  (0x05 << 18) | 0x28906,
188  (0x06 << 18) | 0x18008,
189  (0x07 << 18) | 0x3B500,
190  (0x08 << 18) | 0x05100,
191  (0x09 << 18) | 0x24f08,
192  (0x0A << 18) | 0x14000,
193  (0x0B << 18) | 0x37d80,
194  (0x0C << 18) | 0x0F300 /* TXVGA=51, (MAX-6 dB) */
195 };
196 
197 u32 max2829_channel_data_24[][3] = {
198  {(3 << 18) | 0x30142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 01 (2412MHz) */
199  {(3 << 18) | 0x32141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 02 (2417MHz) */
200  {(3 << 18) | 0x32143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 03 (2422MHz) */
201  {(3 << 18) | 0x32142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 04 (2427MHz) */
202  {(3 << 18) | 0x31141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 05 (2432MHz) */
203  {(3 << 18) | 0x31143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 06 (2437MHz) */
204  {(3 << 18) | 0x31142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 07 (2442MHz) */
205  {(3 << 18) | 0x33141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 08 (2447MHz) */
206  {(3 << 18) | 0x33143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 09 (2452MHz) */
207  {(3 << 18) | 0x33142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 10 (2457MHz) */
208  {(3 << 18) | 0x30941, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 11 (2462MHz) */
209  {(3 << 18) | 0x30943, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 12 (2467MHz) */
210  {(3 << 18) | 0x30942, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 13 (2472MHz) */
211  {(3 << 18) | 0x32941, (4 << 18) | 0x09999, (5 << 18) | 0x289C6}, /* 14 (2484MHz) */
212 };
213 
214 u32 max2829_channel_data_50[][4] = {
215  {36, (3 << 18) | 0x33cc3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 36 (5.180GHz) */
216  {40, (3 << 18) | 0x302c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 40 (5.200GHz) */
217  {44, (3 << 18) | 0x302c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 44 (5.220GHz) */
218  {48, (3 << 18) | 0x322c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 48 (5.240GHz) */
219  {52, (3 << 18) | 0x312c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 52 (5.260GHz) */
220  {56, (3 << 18) | 0x332c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 56 (5.280GHz) */
221  {60, (3 << 18) | 0x30ac0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 60 (5.300GHz) */
222  {64, (3 << 18) | 0x30ac2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 64 (5.320GHz) */
223 
224  {100, (3 << 18) | 0x30ec0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 100 (5.500GHz) */
225  {104, (3 << 18) | 0x30ec2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 104 (5.520GHz) */
226  {108, (3 << 18) | 0x32ec1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 108 (5.540GHz) */
227  {112, (3 << 18) | 0x31ec1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 112 (5.560GHz) */
228  {116, (3 << 18) | 0x33ec3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 116 (5.580GHz) */
229  {120, (3 << 18) | 0x301c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 120 (5.600GHz) */
230  {124, (3 << 18) | 0x301c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 124 (5.620GHz) */
231  {128, (3 << 18) | 0x321c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 128 (5.640GHz) */
232  {132, (3 << 18) | 0x311c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 132 (5.660GHz) */
233  {136, (3 << 18) | 0x331c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 136 (5.680GHz) */
234  {140, (3 << 18) | 0x309c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 140 (5.700GHz) */
235 
236  {149, (3 << 18) | 0x329c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 149 (5.745GHz) */
237  {153, (3 << 18) | 0x319c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 153 (5.765GHz) */
238  {157, (3 << 18) | 0x339c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 157 (5.785GHz) */
239  {161, (3 << 18) | 0x305c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 161 (5.805GHz) */
240 
241  /* Japan */
242  { 184, (3 << 18) | 0x308c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 184 (4.920GHz) */
243  { 188, (3 << 18) | 0x328c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 188 (4.940GHz) */
244  { 192, (3 << 18) | 0x318c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 192 (4.960GHz) */
245  { 196, (3 << 18) | 0x338c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 196 (4.980GHz) */
246  { 8, (3 << 18) | 0x324c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 8 (5.040GHz) */
247  { 12, (3 << 18) | 0x314c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 12 (5.060GHz) */
248  { 16, (3 << 18) | 0x334c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 16 (5.080GHz) */
249  { 34, (3 << 18) | 0x31cc2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 34 (5.170GHz) */
250  { 38, (3 << 18) | 0x33cc1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 38 (5.190GHz) */
251  { 42, (3 << 18) | 0x302c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 42 (5.210GHz) */
252  { 46, (3 << 18) | 0x322c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 46 (5.230GHz) */
253 };
254 
255 /*
256  * ====================================================================
257  * For MAXIM2825/6/7 Ver. 317 or less
258  *
259  * 0x00 0x00080
260  * 0x01 0x214c0
261  * 0x02 0x13802
262  *
263  * 2.4GHz Channels
264  * channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc
265  * channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111
266  * channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb
267  * channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc
268  * channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111
269  * channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb
270  * channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc
271  * channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111
272  * channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb
273  * channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc
274  * channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111
275  * channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb
276  * channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc
277  *
278  * 5.0Ghz Channels
279  * channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333
280  * channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000
281  * channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333
282  * channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999
283  * channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666
284  * channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc
285  * channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000
286  * channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333
287  *
288  * 2.4GHz band ; 0x05 0x28986;
289  * 5.0GHz band ; 0x05 0x2a986
290  * 0x06 0x18008
291  * 0x07 0x38400
292  * 0x08 0x05108
293  * 0x09 0x27ff8
294  * 0x0a 0x14000
295  * 0x0b 0x37f99
296  * 0x0c 0x0c000
297  * ====================================================================
298  */
299 u32 maxim_317_rf_data[] = {
300  (0x00 << 18) | 0x000a2,
301  (0x01 << 18) | 0x214c0,
302  (0x02 << 18) | 0x13802,
303  (0x03 << 18) | 0x30143,
304  (0x04 << 18) | 0x0accc,
305  (0x05 << 18) | 0x28986,
306  (0x06 << 18) | 0x18008,
307  (0x07 << 18) | 0x38400,
308  (0x08 << 18) | 0x05108,
309  (0x09 << 18) | 0x27ff8,
310  (0x0A << 18) | 0x14000,
311  (0x0B << 18) | 0x37f99,
312  (0x0C << 18) | 0x0c000
313 };
314 
315 u32 maxim_317_channel_data_24[][3] = {
316  {(0x03 << 18) | 0x30143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 01 */
317  {(0x03 << 18) | 0x32140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 02 */
318  {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 03 */
319  {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 04 */
320  {(0x03 << 18) | 0x31140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 05 */
321  {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 06 */
322  {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 07 */
323  {(0x03 << 18) | 0x33140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 08 */
324  {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 09 */
325  {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 10 */
326  {(0x03 << 18) | 0x30940, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 11 */
327  {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 12 */
328  {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986} /* channe1 13 */
329 };
330 
331 u32 maxim_317_channel_data_50[][3] = {
332  {(0x03 << 18) | 0x33cc0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a986}, /* channel 36 */
333  {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a986}, /* channel 40 */
334  {(0x03 << 18) | 0x302c3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a986}, /* channel 44 */
335  {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09666, (0x05 << 18) | 0x2a986}, /* channel 48 */
336  {(0x03 << 18) | 0x312c2, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2a986}, /* channel 52 */
337  {(0x03 << 18) | 0x332c0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a99e}, /* channel 56 */
338  {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a99e}, /* channel 60 */
339  {(0x03 << 18) | 0x30ac3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a99e} /* channel 64 */
340 };
341 
342 u32 maxim_317_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
343 u32 maxim_317_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
344 
345 /*
346  * ===================================================================
347  * AL2230 MP (Mass Production Version)
348  * RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004
349  * 20-bit length and LSB first
350  *
351  * Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC;
352  * Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD;
353  * Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC;
354  * Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD;
355  * Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC;
356  * Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD;
357  * Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC;
358  * Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD;
359  * Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC;
360  * Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD;
361  * Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC;
362  * Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD;
363  * Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC;
364  * Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666;
365  *
366  * 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low
367  * 0x02 0x481DC; RXDCOC BW 30Khz for RXHP low
368  *
369  * 0x03 0xCFFF0
370  * 0x04 0x23800
371  * 0x05 0xA3B72
372  * 0x06 0x6DA01
373  * 0x07 0xE1688
374  * 0x08 0x11600
375  * 0x09 0x99E02
376  * 0x0A 0x5DDB0
377  * 0x0B 0xD9900
378  * 0x0C 0x3FFBD
379  * 0x0D 0xB0000
380  * 0x0F 0xF00A0
381  *
382  * RF Calibration for Airoha AL2230
383  *
384  * 0x0f 0xf00a0 ; Initial Setting
385  * 0x0f 0xf00b0 ; Activate TX DCC
386  * 0x0f 0xf02a0 ; Activate Phase Calibration
387  * 0x0f 0xf00e0 ; Activate Filter RC Calibration
388  * 0x0f 0xf00a0 ; Restore Initial Setting
389  * ==================================================================
390  */
391 u32 al2230_rf_data[] = {
392  (0x00 << 20) | 0x09EFC,
393  (0x01 << 20) | 0x8CCCC,
394  (0x02 << 20) | 0x40058,
395  (0x03 << 20) | 0xCFFF0,
396  (0x04 << 20) | 0x24100,
397  (0x05 << 20) | 0xA3B2F,
398  (0x06 << 20) | 0x6DA01,
399  (0x07 << 20) | 0xE3628,
400  (0x08 << 20) | 0x11600,
401  (0x09 << 20) | 0x9DC02,
402  (0x0A << 20) | 0x5ddb0,
403  (0x0B << 20) | 0xD9900,
404  (0x0C << 20) | 0x3FFBD,
405  (0x0D << 20) | 0xB0000,
406  (0x0F << 20) | 0xF01A0
407 };
408 
409 u32 al2230s_rf_data[] = {
410  (0x00 << 20) | 0x09EFC,
411  (0x01 << 20) | 0x8CCCC,
412  (0x02 << 20) | 0x40058,
413  (0x03 << 20) | 0xCFFF0,
414  (0x04 << 20) | 0x24100,
415  (0x05 << 20) | 0xA3B2F,
416  (0x06 << 20) | 0x6DA01,
417  (0x07 << 20) | 0xE3628,
418  (0x08 << 20) | 0x11600,
419  (0x09 << 20) | 0x9DC02,
420  (0x0A << 20) | 0x5DDB0,
421  (0x0B << 20) | 0xD9900,
422  (0x0C << 20) | 0x3FFBD,
423  (0x0D << 20) | 0xB0000,
424  (0x0F << 20) | 0xF01A0
425 };
426 
427 u32 al2230_channel_data_24[][2] = {
428  {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 01 */
429  {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 02 */
430  {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 03 */
431  {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 04 */
432  {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 05 */
433  {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 06 */
434  {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 07 */
435  {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 08 */
436  {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCC}, /* channe1 09 */
437  {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCD}, /* channe1 10 */
438  {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCC}, /* channe1 11 */
439  {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCD}, /* channe1 12 */
440  {(0x00 << 20) | 0x03EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 13 */
441  {(0x00 << 20) | 0x03E7C, (0x01 << 20) | 0x86666} /* channe1 14 */
442 };
443 
444 /* Current setting. u32 airoha_power_data_24[] = {(0x09 << 20) | 0x90202, (0x09 << 20) | 0x96602, (0x09 << 20) | 0x97602}; */
445 #define AIROHA_TXVGA_LOW_INDEX 31 /* Index for 0x90202 */
446 #define AIROHA_TXVGA_MIDDLE_INDEX 12 /* Index for 0x96602 */
447 #define AIROHA_TXVGA_HIGH_INDEX 8 /* Index for 0x97602 1.0.24.0 1.0.28.0 */
448 
449 u32 al2230_txvga_data[][2] = {
450  /* value , index */
451  {0x090202, 0},
452  {0x094202, 2},
453  {0x092202, 4},
454  {0x096202, 6},
455  {0x091202, 8},
456  {0x095202, 10},
457  {0x093202, 12},
458  {0x097202, 14},
459  {0x090A02, 16},
460  {0x094A02, 18},
461  {0x092A02, 20},
462  {0x096A02, 22},
463  {0x091A02, 24},
464  {0x095A02, 26},
465  {0x093A02, 28},
466  {0x097A02, 30},
467  {0x090602, 32},
468  {0x094602, 34},
469  {0x092602, 36},
470  {0x096602, 38},
471  {0x091602, 40},
472  {0x095602, 42},
473  {0x093602, 44},
474  {0x097602, 46},
475  {0x090E02, 48},
476  {0x098E02, 49},
477  {0x094E02, 50},
478  {0x09CE02, 51},
479  {0x092E02, 52},
480  {0x09AE02, 53},
481  {0x096E02, 54},
482  {0x09EE02, 55},
483  {0x091E02, 56},
484  {0x099E02, 57},
485  {0x095E02, 58},
486  {0x09DE02, 59},
487  {0x093E02, 60},
488  {0x09BE02, 61},
489  {0x097E02, 62},
490  {0x09FE02, 63}
491 };
492 
493 /*
494  * ==========================================
495  * For Airoha AL7230, 2.4Ghz band
496  * 24bit, MSB first
497  */
498 
499 /* channel independent registers: */
500 u32 al7230_rf_data_24[] = {
501  (0x00 << 24) | 0x003790,
502  (0x01 << 24) | 0x133331,
503  (0x02 << 24) | 0x841FF2,
504  (0x03 << 24) | 0x3FDFA3,
505  (0x04 << 24) | 0x7FD784,
506  (0x05 << 24) | 0x802B55,
507  (0x06 << 24) | 0x56AF36,
508  (0x07 << 24) | 0xCE0207,
509  (0x08 << 24) | 0x6EBC08,
510  (0x09 << 24) | 0x221BB9,
511  (0x0A << 24) | 0xE0000A,
512  (0x0B << 24) | 0x08071B,
513  (0x0C << 24) | 0x000A3C,
514  (0x0D << 24) | 0xFFFFFD,
515  (0x0E << 24) | 0x00000E,
516  (0x0F << 24) | 0x1ABA8F
517 };
518 
519 u32 al7230_channel_data_24[][2] = {
520  {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331}, /* channe1 01 */
521  {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x1B3331}, /* channe1 02 */
522  {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x033331}, /* channe1 03 */
523  {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x0B3331}, /* channe1 04 */
524  {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x133331}, /* channe1 05 */
525  {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x1B3331}, /* channe1 06 */
526  {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x033331}, /* channe1 07 */
527  {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x0B3331}, /* channe1 08 */
528  {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x133331}, /* channe1 09 */
529  {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x1B3331}, /* channe1 10 */
530  {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x033331}, /* channe1 11 */
531  {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x0B3331}, /* channe1 12 */
532  {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x133331}, /* channe1 13 */
533  {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x066661} /* channel 14 */
534 };
535 
536 /* channel independent registers: */
537 u32 al7230_rf_data_50[] = {
538  (0x00 << 24) | 0x0FF520,
539  (0x01 << 24) | 0x000001,
540  (0x02 << 24) | 0x451FE2,
541  (0x03 << 24) | 0x5FDFA3,
542  (0x04 << 24) | 0x6FD784,
543  (0x05 << 24) | 0x853F55,
544  (0x06 << 24) | 0x56AF36,
545  (0x07 << 24) | 0xCE0207,
546  (0x08 << 24) | 0x6EBC08,
547  (0x09 << 24) | 0x221BB9,
548  (0x0A << 24) | 0xE0600A,
549  (0x0B << 24) | 0x08044B,
550  (0x0C << 24) | 0x00143C,
551  (0x0D << 24) | 0xFFFFFD,
552  (0x0E << 24) | 0x00000E,
553  (0x0F << 24) | 0x12BACF /* 5Ghz default state */
554 };
555 
556 u32 al7230_channel_data_5[][4] = {
557  /* channel dependent registers: 0x00, 0x01 and 0x04 */
558  /* 11J =========== */
559  {184, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 184 */
560  {188, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 188 */
561  {192, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 192 */
562  {196, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 196 */
563  {8, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 008 */
564  {12, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 012 */
565  {16, (0x00 << 24) | 0x0FF550, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 016 */
566  {34, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 034 */
567  {38, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x100001, (0x04 << 24) | 0x77F784}, /* channel 038 */
568  {42, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x1AAAA1, (0x04 << 24) | 0x77F784}, /* channel 042 */
569  {46, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 046 */
570  /* 11 A/H ========= */
571  {36, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 036 */
572  {40, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 040 */
573  {44, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 044 */
574  {48, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 048 */
575  {52, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 052 */
576  {56, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 056 */
577  {60, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 060 */
578  {64, (0x00 << 24) | 0x0FF590, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 064 */
579  {100, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 100 */
580  {104, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 104 */
581  {108, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 108 */
582  {112, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 112 */
583  {116, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 116 */
584  {120, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 120 */
585  {124, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 124 */
586  {128, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 128 */
587  {132, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 132 */
588  {136, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 136 */
589  {140, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 140 */
590  {149, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 149 */
591  {153, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784}, /* channel 153 */
592  {157, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x0D5551, (0x04 << 24) | 0x77F784}, /* channel 157 */
593  {161, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 161 */
594  {165, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784} /* channel 165 */
595 };
596 
597 /*
598  * RF Calibration <=== Register 0x0F
599  * 0x0F 0x1ABA8F; start from 2.4Ghz default state
600  * 0x0F 0x9ABA8F; TXDC compensation
601  * 0x0F 0x3ABA8F; RXFIL adjustment
602  * 0x0F 0x1ABA8F; restore 2.4Ghz default state
603  */
604 
605 /* TXVGA Mapping Table <=== Register 0x0B */
606 u32 al7230_txvga_data[][2] = {
607  {0x08040B, 0}, /* TXVGA = 0; */
608  {0x08041B, 1}, /* TXVGA = 1; */
609  {0x08042B, 2}, /* TXVGA = 2; */
610  {0x08043B, 3}, /* TXVGA = 3; */
611  {0x08044B, 4}, /* TXVGA = 4; */
612  {0x08045B, 5}, /* TXVGA = 5; */
613  {0x08046B, 6}, /* TXVGA = 6; */
614  {0x08047B, 7}, /* TXVGA = 7; */
615  {0x08048B, 8}, /* TXVGA = 8; */
616  {0x08049B, 9}, /* TXVGA = 9; */
617  {0x0804AB, 10}, /* TXVGA = 10; */
618  {0x0804BB, 11}, /* TXVGA = 11; */
619  {0x0804CB, 12}, /* TXVGA = 12; */
620  {0x0804DB, 13}, /* TXVGA = 13; */
621  {0x0804EB, 14}, /* TXVGA = 14; */
622  {0x0804FB, 15}, /* TXVGA = 15; */
623  {0x08050B, 16}, /* TXVGA = 16; */
624  {0x08051B, 17}, /* TXVGA = 17; */
625  {0x08052B, 18}, /* TXVGA = 18; */
626  {0x08053B, 19}, /* TXVGA = 19; */
627  {0x08054B, 20}, /* TXVGA = 20; */
628  {0x08055B, 21}, /* TXVGA = 21; */
629  {0x08056B, 22}, /* TXVGA = 22; */
630  {0x08057B, 23}, /* TXVGA = 23; */
631  {0x08058B, 24}, /* TXVGA = 24; */
632  {0x08059B, 25}, /* TXVGA = 25; */
633  {0x0805AB, 26}, /* TXVGA = 26; */
634  {0x0805BB, 27}, /* TXVGA = 27; */
635  {0x0805CB, 28}, /* TXVGA = 28; */
636  {0x0805DB, 29}, /* TXVGA = 29; */
637  {0x0805EB, 30}, /* TXVGA = 30; */
638  {0x0805FB, 31}, /* TXVGA = 31; */
639  {0x08060B, 32}, /* TXVGA = 32; */
640  {0x08061B, 33}, /* TXVGA = 33; */
641  {0x08062B, 34}, /* TXVGA = 34; */
642  {0x08063B, 35}, /* TXVGA = 35; */
643  {0x08064B, 36}, /* TXVGA = 36; */
644  {0x08065B, 37}, /* TXVGA = 37; */
645  {0x08066B, 38}, /* TXVGA = 38; */
646  {0x08067B, 39}, /* TXVGA = 39; */
647  {0x08068B, 40}, /* TXVGA = 40; */
648  {0x08069B, 41}, /* TXVGA = 41; */
649  {0x0806AB, 42}, /* TXVGA = 42; */
650  {0x0806BB, 43}, /* TXVGA = 43; */
651  {0x0806CB, 44}, /* TXVGA = 44; */
652  {0x0806DB, 45}, /* TXVGA = 45; */
653  {0x0806EB, 46}, /* TXVGA = 46; */
654  {0x0806FB, 47}, /* TXVGA = 47; */
655  {0x08070B, 48}, /* TXVGA = 48; */
656  {0x08071B, 49}, /* TXVGA = 49; */
657  {0x08072B, 50}, /* TXVGA = 50; */
658  {0x08073B, 51}, /* TXVGA = 51; */
659  {0x08074B, 52}, /* TXVGA = 52; */
660  {0x08075B, 53}, /* TXVGA = 53; */
661  {0x08076B, 54}, /* TXVGA = 54; */
662  {0x08077B, 55}, /* TXVGA = 55; */
663  {0x08078B, 56}, /* TXVGA = 56; */
664  {0x08079B, 57}, /* TXVGA = 57; */
665  {0x0807AB, 58}, /* TXVGA = 58; */
666  {0x0807BB, 59}, /* TXVGA = 59; */
667  {0x0807CB, 60}, /* TXVGA = 60; */
668  {0x0807DB, 61}, /* TXVGA = 61; */
669  {0x0807EB, 62}, /* TXVGA = 62; */
670  {0x0807FB, 63}, /* TXVGA = 63; */
671 };
672 /* ============================================= */
673 
674 /*
675  * W89RF242 RFIC SPI programming initial data
676  * Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
677  */
678 u32 w89rf242_rf_data[] = {
679  (0x00 << 24) | 0xF86100, /* 3E184; MODA (0x00) -- Normal mode ; calibration off */
680  (0x01 << 24) | 0xEFFFC2, /* 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on */
681  (0x02 << 24) | 0x102504, /* 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA */
682  (0x03 << 24) | 0x026286, /* 0098A; FCHN (0x03) -- default CH7, 2442MHz */
683  (0x04 << 24) | 0x000208, /* 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C */
684  (0x05 << 24) | 0x24C60A, /* 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D */
685  (0x06 << 24) | 0x3432CC, /* 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input */
686  (0x07 << 24) | 0x0C68CE, /* 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 */
687  (0x08 << 24) | 0x100010, /* 04000; TCAL (0x08) -- for LO */
688  (0x09 << 24) | 0x004012, /* 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) */
689  (0x0A << 24) | 0x704014, /* 1C100; RCALB (0x0A) */
690  (0x0B << 24) | 0x18BDD6, /* 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B */
691  (0x0C << 24) | 0x575558, /* 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner */
692  (0x0D << 24) | 0x55545A, /* 15555 ; IBSB (0x0D) */
693  (0x0E << 24) | 0x5557DC, /* 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F */
694  (0x10 << 24) | 0x000C20, /* 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB */
695  (0x11 << 24) | 0x0C0022, /* 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) */
696  (0x12 << 24) | 0x000024 /* TMODC (0x12) -- Turn OFF Temperature sensor */
697 };
698 
699 u32 w89rf242_channel_data_24[][2] = {
700  {(0x03 << 24) | 0x025B06, (0x04 << 24) | 0x080408}, /* channe1 01 */
701  {(0x03 << 24) | 0x025C46, (0x04 << 24) | 0x080408}, /* channe1 02 */
702  {(0x03 << 24) | 0x025D86, (0x04 << 24) | 0x080408}, /* channe1 03 */
703  {(0x03 << 24) | 0x025EC6, (0x04 << 24) | 0x080408}, /* channe1 04 */
704  {(0x03 << 24) | 0x026006, (0x04 << 24) | 0x080408}, /* channe1 05 */
705  {(0x03 << 24) | 0x026146, (0x04 << 24) | 0x080408}, /* channe1 06 */
706  {(0x03 << 24) | 0x026286, (0x04 << 24) | 0x080408}, /* channe1 07 */
707  {(0x03 << 24) | 0x0263C6, (0x04 << 24) | 0x080408}, /* channe1 08 */
708  {(0x03 << 24) | 0x026506, (0x04 << 24) | 0x080408}, /* channe1 09 */
709  {(0x03 << 24) | 0x026646, (0x04 << 24) | 0x080408}, /* channe1 10 */
710  {(0x03 << 24) | 0x026786, (0x04 << 24) | 0x080408}, /* channe1 11 */
711  {(0x03 << 24) | 0x0268C6, (0x04 << 24) | 0x080408}, /* channe1 12 */
712  {(0x03 << 24) | 0x026A06, (0x04 << 24) | 0x080408}, /* channe1 13 */
713  {(0x03 << 24) | 0x026D06, (0x04 << 24) | 0x080408} /* channe1 14 */
714 };
715 
716 u32 w89rf242_power_data_24[] = {(0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A};
717 
718 u32 w89rf242_txvga_old_mapping[][2] = {
719  {0, 0} , /* New <-> Old */
720  {1, 1} ,
721  {2, 2} ,
722  {3, 3} ,
723  {4, 4} ,
724  {6, 5} ,
725  {8, 6},
726  {10, 7},
727  {12, 8},
728  {14, 9},
729  {16, 10},
730  {18, 11},
731  {20, 12},
732  {22, 13},
733  {24, 14},
734  {26, 15},
735  {28, 16},
736  {30, 17},
737  {32, 18},
738  {34, 19},
739 };
740 
741 u32 w89rf242_txvga_data[][5] = {
742  /* low gain mode */
743  {(0x05 << 24) | 0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131}, /* min gain */
744  {(0x05 << 24) | 0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131},
745  {(0x05 << 24) | 0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131}, /* (default) +14dBm (ANT) */
746  {(0x05 << 24) | 0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131},
747 
748  /* TXVGA=0x10 */
749  {(0x05 << 24) | 0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838},
750  {(0x05 << 24) | 0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B},
751 
752  /* TXVGA=0x11 */
753  { (0x05 << 24) | 0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333},
754  { (0x05 << 24) | 0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737},
755 
756  /* TXVGA=0x12 */
757  {(0x05 << 24) | 0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030},
758  {(0x05 << 24) | 0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434},
759 
760  /* TXVGA=0x13 */
761  {(0x05 << 24) | 0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030},
762  {(0x05 << 24) | 0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232},
763 
764  /* TXVGA=0x14 */
765  {(0x05 << 24) | 0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131},
766  {(0x05 << 24) | 0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434},
767 
768  /* TXVGA=0x15 */
769  {(0x05 << 24) | 0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131},
770  {(0x05 << 24) | 0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434},
771 
772  /* TXVGA=0x16 */
773  {(0x05 << 24) | 0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131},
774  {(0x05 << 24) | 0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535},
775 
776  /* TXVGA=0x17 */
777  {(0x05 << 24) | 0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F},
778  {(0x05 << 24) | 0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131},
779 
780  /* TXVGA=0x18 */
781  {(0x05 << 24) | 0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E},
782  {(0x05 << 24) | 0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030},
783 
784  /* TXVGA=0x19 */
785  {(0x05 << 24) | 0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D},
786  {(0x05 << 24) | 0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030},
787 
788  /* TXVGA=0x1A */
789  {(0x05 << 24) | 0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E},
790  {(0x05 << 24) | 0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131},
791 
792  /* TXVGA=0x1B */
793  {(0x05 << 24) | 0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030},
794  {(0x05 << 24) | 0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434},
795 
796  /* TXVGA=0x1C */
797  {(0x05 << 24) | 0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131},
798  {(0x05 << 24) | 0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636},
799 
800  /* TXVGA=0x1D */
801  {(0x05 << 24) | 0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737},
802  {(0x05 << 24) | 0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B},
803 
804  /* TXVGA=0x1E */
805  {(0x05 << 24) | 0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B},
806  {(0x05 << 24) | 0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141},
807 
808  /* TXVGA=0x1F */
809  {(0x05 << 24) | 0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242}
810 };
811 
812 /* ================================================================================================== */
813 
814 
815 
816 /*
817  * =============================================================================================================
818  * Uxx_ReadEthernetAddress --
819  *
820  * Routine Description:
821  * Reads in the Ethernet address from the IC.
822  *
823  * Arguments:
824  * pHwData - The pHwData structure
825  *
826  * Return Value:
827  *
828  * The address is stored in EthernetIDAddr.
829  * =============================================================================================================
830  */
831 void Uxx_ReadEthernetAddress(struct hw_data *pHwData)
832 {
833  u32 ltmp;
834 
835  /*
836  * Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change.
837  * Only unplug and plug again can make hardware read EEPROM again.
838  */
839  Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08000000); /* Start EEPROM access + Read + address(0x0d) */
840  Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
841  *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16) ltmp);
842  Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08010000); /* Start EEPROM access + Read + address(0x0d) */
843  Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
844  *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16) ltmp);
845  Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08020000); /* Start EEPROM access + Read + address(0x0d) */
846  Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
847  *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16) ltmp);
848  *(u16 *)(pHwData->PermanentMacAddress + 6) = 0;
849  Wb35Reg_WriteSync(pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress));
850  Wb35Reg_WriteSync(pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress + 4)));
851 }
852 
853 
854 /*
855  * ===============================================================================================================
856  * CardGetMulticastBit --
857  * Description:
858  * For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to.
859  * Calls CardComputeCrc() to determine the CRC value.
860  * Arguments:
861  * Address - the address
862  * Byte - the byte that it hashes to
863  * Value - will have a 1 in the relevant bit
864  * Return Value:
865  * None.
866  * ==============================================================================================================
867  */
868 void CardGetMulticastBit(u8 Address[ETH_ALEN], u8 *Byte, u8 *Value)
869 {
870  u32 Crc;
871  u32 BitNumber;
872 
873  /* First compute the CRC. */
874  Crc = CardComputeCrc(Address, ETH_ALEN);
875 
876  /* The computed CRC is bit0~31 from left to right */
877  /* At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 */
878  BitNumber = (u32) ((Crc >> 26) & 0x3f);
879 
880  *Byte = (u8) (BitNumber >> 3); /* 900514 original (BitNumber / 8) */
881  *Value = (u8) ((u8) 1 << (BitNumber % 8));
882 }
883 
884 void Uxx_power_on_procedure(struct hw_data *pHwData)
885 {
886  u32 ltmp, loop;
887 
888  if (pHwData->phy_type <= RF_MAXIM_V1)
889  Wb35Reg_WriteSync(pHwData, 0x03d4, 0xffffff38);
890  else {
891  Wb35Reg_WriteSync(pHwData, 0x03f4, 0xFF5807FF);
892  Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */
893  msleep(10);
894  Wb35Reg_WriteSync(pHwData, 0x03d4, 0xb8); /* REG_ON RF_RSTN on, and */
895  msleep(10);
896  ltmp = 0x4968;
897  if ((pHwData->phy_type == RF_WB_242) ||
898  (RF_WB_242_1 == pHwData->phy_type))
899  ltmp = 0x4468;
900 
901  Wb35Reg_WriteSync(pHwData, 0x03d0, ltmp);
902  Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
903 
904  msleep(20);
905  Wb35Reg_ReadSync(pHwData, 0x03d0, &ltmp);
906  loop = 500; /* Wait for 5 second */
907  while (!(ltmp & 0x20) && loop--) {
908  msleep(10);
909  if (!Wb35Reg_ReadSync(pHwData, 0x03d0, &ltmp))
910  break;
911  }
912 
913  Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */
914  }
915 
916  Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */
917  msleep(10);
918 
919  /* Set burst write delay */
920  Wb35Reg_WriteSync(pHwData, 0x03f8, 0x7ff);
921 }
922 
923 void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp , char number)
924 {
925  u8 i;
926 
927  for (i = 0; i < number; i++) {
928  pHwData->phy_para[i] = al7230_rf_data_24[i];
929  pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i] & 0xffffff);
930  }
931 }
932 
933 void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp, char number)
934 {
935  u8 i;
936 
937  for (i = 0; i < number; i++) {
938  pHwData->phy_para[i] = al7230_rf_data_50[i];
939  pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i] & 0xffffff);
940  }
941 }
942 
943 
944 /*
945  * =============================================================================================================
946  * RFSynthesizer_initial --
947  * =============================================================================================================
948  */
949 void RFSynthesizer_initial(struct hw_data *pHwData)
950 {
951  u32 altmp[32];
952  u32 *pltmp = altmp;
953  u32 ltmp;
954  u8 number = 0x00; /* The number of register vale */
955  u8 i;
956 
957  /*
958  * bit[31] SPI Enable.
959  * 1=perform synthesizer program operation. This bit will
960  * cleared automatically after the operation is completed.
961  * bit[30] SPI R/W Control
962  * 0=write, 1=read
963  * bit[29:24] SPI Data Format Length
964  * bit[17:4 ] RF Data bits.
965  * bit[3 :0 ] RF address.
966  */
967  switch (pHwData->phy_type) {
968  case RF_MAXIM_2825:
969  case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
970  number = ARRAY_SIZE(max2825_rf_data);
971  for (i = 0; i < number; i++) {
972  pHwData->phy_para[i] = max2825_rf_data[i]; /* Backup Rf parameter */
973  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_rf_data[i], 18);
974  }
975  break;
976  case RF_MAXIM_2827:
977  number = ARRAY_SIZE(max2827_rf_data);
978  for (i = 0; i < number; i++) {
979  pHwData->phy_para[i] = max2827_rf_data[i];
980  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_rf_data[i], 18);
981  }
982  break;
983  case RF_MAXIM_2828:
984  number = ARRAY_SIZE(max2828_rf_data);
985  for (i = 0; i < number; i++) {
986  pHwData->phy_para[i] = max2828_rf_data[i];
987  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_rf_data[i], 18);
988  }
989  break;
990  case RF_MAXIM_2829:
991  number = ARRAY_SIZE(max2829_rf_data);
992  for (i = 0; i < number; i++) {
993  pHwData->phy_para[i] = max2829_rf_data[i];
994  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_rf_data[i], 18);
995  }
996  break;
997  case RF_AIROHA_2230:
998  number = ARRAY_SIZE(al2230_rf_data);
999  for (i = 0; i < number; i++) {
1000  pHwData->phy_para[i] = al2230_rf_data[i];
1001  pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[i], 20);
1002  }
1003  break;
1004  case RF_AIROHA_2230S:
1005  number = ARRAY_SIZE(al2230s_rf_data);
1006  for (i = 0; i < number; i++) {
1007  pHwData->phy_para[i] = al2230s_rf_data[i];
1008  pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230s_rf_data[i], 20);
1009  }
1010  break;
1011  case RF_AIROHA_7230:
1012  /* Start to fill RF parameters, PLL_ON should be pulled low. */
1013  Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
1014  pr_debug("* PLL_ON low\n");
1015  number = ARRAY_SIZE(al7230_rf_data_24);
1016  Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1017  break;
1018  case RF_WB_242:
1019  case RF_WB_242_1:
1020  number = ARRAY_SIZE(w89rf242_rf_data);
1021  for (i = 0; i < number; i++) {
1022  ltmp = w89rf242_rf_data[i];
1023  if (i == 4) { /* Update the VCO trim from EEPROM */
1024  ltmp &= ~0xff0; /* Mask bit4 ~bit11 */
1025  ltmp |= pHwData->VCO_trim << 4;
1026  }
1027 
1028  pHwData->phy_para[i] = ltmp;
1029  pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(ltmp, 24);
1030  }
1031  break;
1032  }
1033 
1034  pHwData->phy_number = number;
1035 
1036  /* The 16 is the maximum capability of hardware. Here use 12 */
1037  if (number > 12) {
1038  for (i = 0; i < 12; i++) /* For Al2230 */
1039  Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]);
1040 
1041  pltmp += 12;
1042  number -= 12;
1043  }
1044 
1045  /* Write to register. number must less and equal than 16 */
1046  for (i = 0; i < number; i++)
1047  Wb35Reg_WriteSync(pHwData, 0x864, pltmp[i]);
1048 
1049  /* Calibration only 1 time */
1050  if (pHwData->CalOneTime)
1051  return;
1052  pHwData->CalOneTime = 1;
1053 
1054  switch (pHwData->phy_type) {
1055  case RF_AIROHA_2230:
1056  ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x07 << 20) | 0xE168E, 20);
1057  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1058  msleep(10);
1059  ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[7], 20);
1060  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1061  msleep(10);
1062  case RF_AIROHA_2230S:
1063  Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */
1064  msleep(10);
1065  Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
1066  msleep(10);
1067  Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */
1068  Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */
1069  msleep(10);
1070  /* ========================================================= */
1071 
1072  /* The follow code doesn't use the burst-write mode */
1073  ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F<<20) | 0xF01A0, 20);
1074  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1075 
1076  ltmp = pHwData->reg.BB5C & 0xfffff000;
1077  Wb35Reg_WriteSync(pHwData, 0x105c, ltmp);
1078  pHwData->reg.BB50 |= 0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START) */
1079  Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1080  msleep(5);
1081 
1082  ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01B0, 20);
1083  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1084  msleep(5);
1085 
1086  ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01E0, 20);
1087  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1088  msleep(5);
1089 
1090  ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20);
1091  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp) ;
1092 
1093  Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
1094  pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1095  Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1096  break;
1097  case RF_AIROHA_7230:
1098  /* RF parameters have filled completely, PLL_ON should be pulled high */
1099  Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
1100  pr_debug("* PLL_ON high\n");
1101 
1102  /* 2.4GHz */
1103  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1104  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1105  msleep(5);
1106  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1107  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1108  msleep(5);
1109  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1110  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1111  msleep(5);
1112 
1113  /* 5GHz */
1114  Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
1115  pr_debug("* PLL_ON low\n");
1116 
1117  number = ARRAY_SIZE(al7230_rf_data_50);
1118  Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1119  /* Write to register. number must less and equal than 16 */
1120  for (i = 0; i < number; i++)
1121  Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]);
1122  msleep(5);
1123 
1124  Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
1125  pr_debug("* PLL_ON high\n");
1126 
1127  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1128  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1129  msleep(5);
1130  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1131  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1132  msleep(5);
1133  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1134  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1135  msleep(5);
1136  break;
1137  case RF_WB_242:
1138  case RF_WB_242_1:
1139  /* for FA5976A */
1140  ltmp = pHwData->reg.BB5C & 0xfffff000;
1141  Wb35Reg_WriteSync(pHwData, 0x105c, ltmp);
1142  Wb35Reg_WriteSync(pHwData, 0x1058, 0);
1143  pHwData->reg.BB50 |= 0x3; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1144  Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1145 
1146  /* ----- Calibration (1). VCO frequency calibration */
1147  /* Calibration (1a.0). Synthesizer reset */
1148  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00101E, 24);
1149  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1150  msleep(5);
1151  /* Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time */
1152  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFE69c0, 24);
1153  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1154  msleep(2);
1155 
1156  /* ----- Calibration (2). TX baseband Gm-C filter auto-tuning */
1157  /* Calibration (2a). turn off ENCAL signal */
1158  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24);
1159  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1160  /* Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) */
1161  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24);
1162  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1163  /* Calibration (2b). send TX reset signal */
1164  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00201E, 24);
1165  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1166  /* Calibration (2c). turn-on TX Gm-C filter auto-tuning */
1167  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFCEBC0, 24);
1168  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1169  udelay(150); /* Sleep 150 us */
1170  /* turn off ENCAL signal */
1171  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24);
1172  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1173 
1174  /* ----- Calibration (3). RX baseband Gm-C filter auto-tuning */
1175  /* Calibration (3a). turn off ENCAL signal */
1176  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1177  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1178  /* Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default;) */
1179  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24);
1180  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1181  /* Calibration (3b). send RX reset signal */
1182  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00401E, 24);
1183  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1184  /* Calibration (3c). turn-on RX Gm-C filter auto-tuning */
1185  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFEEDC0, 24);
1186  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1187  udelay(150); /* Sleep 150 us */
1188  /* Calibration (3e). turn off ENCAL signal */
1189  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1190  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1191 
1192  /* ----- Calibration (4). TX LO leakage calibration */
1193  /* Calibration (4a). TX LO leakage calibration */
1194  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFD6BC0, 24);
1195  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1196  udelay(150); /* Sleep 150 us */
1197 
1198  /* ----- Calibration (5). RX DC offset calibration */
1199  /* Calibration (5a). turn off ENCAL signal and set to RX SW DC calibration mode */
1200  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1201  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1202  /* Calibration (5b). turn off AGC servo-loop & RSSI */
1203  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEBFFC2, 24);
1204  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1205 
1206  /* for LNA=11 -------- */
1207  /* Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 */
1208  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x343FCC, 24);
1209  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1210  /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1211  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1212  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1213  msleep(2);
1214  /* Calibration (5f). turn off ENCAL signal */
1215  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1216  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1217 
1218  /* for LNA=10 -------- */
1219  /* Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 */
1220  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x342FCC, 24);
1221  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1222  /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1223  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1224  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1225  msleep(2);
1226  /* Calibration (5f). turn off ENCAL signal */
1227  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1228  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1229 
1230  /* for LNA=01 -------- */
1231  /* Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 */
1232  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x341FCC, 24);
1233  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1234  /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1235  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1236  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1237  msleep(2);
1238  /* Calibration (5f). turn off ENCAL signal */
1239  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1240  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1241 
1242  /* for LNA=00 -------- */
1243  /* Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 */
1244  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x340FCC, 24);
1245  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1246  /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1247  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1248  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1249  msleep(2);
1250  /* Calibration (5f). turn off ENCAL signal */
1251  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1252  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1253  /* Calibration (5g). turn on AGC servo-loop */
1254  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEFFFC2, 24);
1255  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1256 
1257  /* ----- Calibration (7). Switch RF chip to normal mode */
1258  /* 0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode */
1259  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF86100, 24);
1260  Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1261  msleep(5);
1262  break;
1263  }
1264 }
1265 
1266 void BBProcessor_AL7230_2400(struct hw_data *pHwData)
1267 {
1268  struct wb35_reg *reg = &pHwData->reg;
1269  u32 pltmp[12];
1270 
1271  pltmp[0] = 0x16A8337A; /* 0x1000 AGC_Ctrl1 */
1272  pltmp[1] = 0x9AFF9AA6; /* 0x1004 AGC_Ctrl2 */
1273  pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1274  pltmp[3] = 0xFFF72031; /* 0x100c AGC_Ctrl4 */
1275  reg->BB0C = 0xFFF72031;
1276  pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */
1277  pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */
1278  pltmp[6] = 0xF2211111; /* 0x1018 AGC_Ctrl7 */
1279  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1280  pltmp[8] = 0x06443440; /* 0x1020 AGC_Ctrl9 */
1281  pltmp[9] = 0xA8002A79; /* 0x1024 AGC_Ctrl10 */
1282  pltmp[10] = 0x40000528;
1283  pltmp[11] = 0x232D7F30; /* 0x102c A_ACQ_Ctrl */
1284  reg->BB2C = 0x232D7F30;
1285  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1286 
1287  pltmp[0] = 0x00002c54; /* 0x1030 B_ACQ_Ctrl */
1288  reg->BB30 = 0x00002c54;
1289  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1290  pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1291  pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1292  reg->BB3C = 0x00000000;
1293  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1294  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1295  pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */
1296  pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */
1297  pltmp[8] = 0x2B106208; /* 0x1050 MODE_Ctrl */
1298  reg->BB50 = 0x2B106208;
1299  pltmp[9] = 0; /* 0x1054 */
1300  reg->BB54 = 0x00000000;
1301  pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1302  reg->BB58 = 0x52524242;
1303  pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1304  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1305 }
1306 
1307 void BBProcessor_AL7230_5000(struct hw_data *pHwData)
1308 {
1309  struct wb35_reg *reg = &pHwData->reg;
1310  u32 pltmp[12];
1311 
1312  pltmp[0] = 0x16AA6678; /* 0x1000 AGC_Ctrl1 */
1313  pltmp[1] = 0x9AFFA0B2; /* 0x1004 AGC_Ctrl2 */
1314  pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1315  pltmp[3] = 0xEFFF233E; /* 0x100c AGC_Ctrl4 */
1316  reg->BB0C = 0xEFFF233E;
1317  pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */
1318  pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */
1319  pltmp[6] = 0xF2432111; /* 0x1018 AGC_Ctrl7 */
1320  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1321  pltmp[8] = 0x05C43440; /* 0x1020 AGC_Ctrl9 */
1322  pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1323  pltmp[10] = 0x40000528;
1324  pltmp[11] = 0x232FDF30;/* 0x102c A_ACQ_Ctrl */
1325  reg->BB2C = 0x232FDF30;
1326  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1327 
1328  pltmp[0] = 0x80002C7C; /* 0x1030 B_ACQ_Ctrl */
1329  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1330  pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1331  pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1332  reg->BB3C = 0x00000000;
1333  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1334  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1335  pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */
1336  pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */
1337  pltmp[8] = 0x2B107208; /* 0x1050 MODE_Ctrl */
1338  reg->BB50 = 0x2B107208;
1339  pltmp[9] = 0; /* 0x1054 */
1340  reg->BB54 = 0x00000000;
1341  pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1342  reg->BB58 = 0x52524242;
1343  pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1344  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1345 }
1346 
1347 /*
1348  * ===========================================================================
1349  * BBProcessorPowerupInit --
1350  *
1351  * Description:
1352  * Initialize the Baseband processor.
1353  *
1354  * Arguments:
1355  * pHwData - Handle of the USB Device.
1356  *
1357  * Return values:
1358  * None.
1359  *============================================================================
1360  */
1361 void BBProcessor_initial(struct hw_data *pHwData)
1362 {
1363  struct wb35_reg *reg = &pHwData->reg;
1364  u32 i, pltmp[12];
1365 
1366  switch (pHwData->phy_type) {
1367  case RF_MAXIM_V1: /* Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1368  pltmp[0] = 0x16F47E77; /* 0x1000 AGC_Ctrl1 */
1369  pltmp[1] = 0x9AFFAEA4; /* 0x1004 AGC_Ctrl2 */
1370  pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1371  pltmp[3] = 0xEFFF1A34; /* 0x100c AGC_Ctrl4 */
1372  reg->BB0C = 0xEFFF1A34;
1373  pltmp[4] = 0x0FABE0B7; /* 0x1010 AGC_Ctrl5 */
1374  pltmp[5] = 0x00CAA332; /* 0x1014 AGC_Ctrl6 */
1375  pltmp[6] = 0xF6632111; /* 0x1018 AGC_Ctrl7 */
1376  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1377  pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1378  pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1379  pltmp[10] = (pHwData->phy_type == 3) ? 0x40000a28 : 0x40000228; /* 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) */
1380  pltmp[11] = 0x232FDF30; /* 0x102c A_ACQ_Ctrl */
1381  reg->BB2C = 0x232FDF30; /* Modify for 33's 1.0.95.xxx version, antenna 1 */
1382  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1383 
1384  pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1385  reg->BB30 = 0x00002C54;
1386  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1387  pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */
1388  pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1389  reg->BB3C = 0x00000000;
1390  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1391  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1392  pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */
1393  pltmp[7] = 0x0E00FEFF; /* 0x104c 11b TX RC filter */
1394  pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1395  reg->BB50 = 0x27106208;
1396  pltmp[9] = 0; /* 0x1054 */
1397  reg->BB54 = 0x00000000;
1398  pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */
1399  reg->BB58 = 0x64646464;
1400  pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1401  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1402 
1403  Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1404  break;
1405 
1406  case RF_MAXIM_2825:
1407  case RF_MAXIM_2827:
1408  case RF_MAXIM_2828:
1409  pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */
1410  pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */
1411  pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1412  pltmp[3] = 0xefff1a34; /* 0x100c AGC_Ctrl4 */
1413  reg->BB0C = 0xefff1a34;
1414  pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */
1415  pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1416  pltmp[6] = 0xf6632111; /* 0x1018 AGC_Ctrl7 */
1417  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1418  pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1419  pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1420  pltmp[10] = 0x40000528;
1421  pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */
1422  reg->BB2C = 0x232fdf30; /* antenna 1 */
1423  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1424 
1425  pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1426  reg->BB30 = 0x00002C54;
1427  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1428  pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */
1429  pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1430  reg->BB3C = 0x00000000;
1431  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1432  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1433  pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */
1434  pltmp[7] = 0x0D00FDFF; /* 0x104c 11b TX RC filter */
1435  pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1436  reg->BB50 = 0x27106208;
1437  pltmp[9] = 0; /* 0x1054 */
1438  reg->BB54 = 0x00000000;
1439  pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */
1440  reg->BB58 = 0x64646464;
1441  pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */
1442  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1443 
1444  Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1445  break;
1446 
1447  case RF_MAXIM_2829:
1448  pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */
1449  pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */
1450  pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1451  pltmp[3] = 0xf4ff1632; /* 0x100c AGC_Ctrl4 */
1452  reg->BB0C = 0xf4ff1632;
1453  pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */
1454  pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1455  pltmp[6] = 0xf8632112; /* 0x1018 AGC_Ctrl7 */
1456  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1457  pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1458  pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1459  pltmp[10] = 0x40000528;
1460  pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */
1461  reg->BB2C = 0x232fdf30; /* antenna 1 */
1462  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1463 
1464  pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1465  reg->BB30 = 0x00002C54;
1466  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1467  pltmp[2] = 0x5b2c8769; /* 0x1038 B_TXRX_Ctrl */
1468  pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1469  reg->BB3C = 0x00000000;
1470  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1471  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1472  pltmp[6] = 0x002c2617; /* 0x1048 11b TX RC filter */
1473  pltmp[7] = 0x0800feff; /* 0x104c 11b TX RC filter */
1474  pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1475  reg->BB50 = 0x27106208;
1476  pltmp[9] = 0; /* 0x1054 */
1477  reg->BB54 = 0x00000000;
1478  pltmp[10] = 0x64644a4a; /* 0x1058 IQ_Alpha */
1479  reg->BB58 = 0x64646464;
1480  pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */
1481  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1482  Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1483  break;
1484  case RF_AIROHA_2230:
1485  pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */
1486  pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */
1487  pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1488  pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */
1489  reg->BB0C = 0xFFFd203c;
1490  pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */
1491  pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1492  pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */
1493  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1494  pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */
1495  pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1496  pltmp[10] = 0X40000528;
1497  pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */
1498  reg->BB2C = 0x232dfF30; /* antenna 1 */
1499  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1500 
1501  pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1502  reg->BB30 = 0x00002C54;
1503  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1504  pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1505  pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1506  reg->BB3C = 0x00000000;
1507  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1508  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1509  pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */
1510  reg->BB48 = BB48_DEFAULT_AL2230_11G; /* 20051221 ch14 */
1511  pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */
1512  reg->BB4C = BB4C_DEFAULT_AL2230_11G;
1513  pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */
1514  reg->BB50 = 0x27106200;
1515  pltmp[9] = 0; /* 0x1054 */
1516  reg->BB54 = 0x00000000;
1517  pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1518  reg->BB58 = 0x52524242;
1519  pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1520  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1521 
1522  Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1523  break;
1524  case RF_AIROHA_2230S:
1525  pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */
1526  pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */
1527  pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1528  pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */
1529  reg->BB0C = 0xFFFd203c;
1530  pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */
1531  pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1532  pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */
1533  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1534  pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */
1535  pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1536  pltmp[10] = 0X40000528;
1537  pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */
1538  reg->BB2C = 0x232dfF30; /* antenna 1 */
1539  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1540 
1541  pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1542  reg->BB30 = 0x00002C54;
1543  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1544  pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1545  pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1546  reg->BB3C = 0x00000000;
1547  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1548  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1549  pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */
1550  reg->BB48 = BB48_DEFAULT_AL2230_11G; /* ch14 */
1551  pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */
1552  reg->BB4C = BB4C_DEFAULT_AL2230_11G;
1553  pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */
1554  reg->BB50 = 0x27106200;
1555  pltmp[9] = 0; /* 0x1054 */
1556  reg->BB54 = 0x00000000;
1557  pltmp[10] = 0x52523232; /* 0x1058 IQ_Alpha */
1558  reg->BB58 = 0x52523232;
1559  pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1560  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1561 
1562  Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1563  break;
1564  case RF_AIROHA_7230:
1565  BBProcessor_AL7230_2400(pHwData);
1566 
1567  Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1568  break;
1569  case RF_WB_242:
1570  case RF_WB_242_1:
1571  pltmp[0] = 0x16A8525D; /* 0x1000 AGC_Ctrl1 */
1572  pltmp[1] = 0x9AFF9ABA; /* 0x1004 AGC_Ctrl2 */
1573  pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1574  pltmp[3] = 0xEEE91C32; /* 0x100c AGC_Ctrl4 */
1575  reg->BB0C = 0xEEE91C32;
1576  pltmp[4] = 0x0FACDCC5; /* 0x1010 AGC_Ctrl5 */
1577  pltmp[5] = 0x000AA344; /* 0x1014 AGC_Ctrl6 */
1578  pltmp[6] = 0x22222221; /* 0x1018 AGC_Ctrl7 */
1579  pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1580  pltmp[8] = 0x04CC3440; /* 0x1020 AGC_Ctrl9 */
1581  pltmp[9] = 0xA9002A79; /* 0x1024 AGC_Ctrl10 */
1582  pltmp[10] = 0x40000528; /* 0x1028 */
1583  pltmp[11] = 0x23457F30; /* 0x102c A_ACQ_Ctrl */
1584  reg->BB2C = 0x23457F30;
1585  Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1586 
1587  pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1588  reg->BB30 = 0x00002C54;
1589  pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1590  pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1591  pltmp[3] = pHwData->BB3c_cal; /* 0x103c 11a TX LS filter */
1592  reg->BB3C = pHwData->BB3c_cal;
1593  pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1594  pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1595  pltmp[6] = BB48_DEFAULT_WB242_11G; /* 0x1048 11b TX RC filter */
1596  reg->BB48 = BB48_DEFAULT_WB242_11G;
1597  pltmp[7] = BB4C_DEFAULT_WB242_11G; /* 0x104c 11b TX RC filter */
1598  reg->BB4C = BB4C_DEFAULT_WB242_11G;
1599  pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1600  reg->BB50 = 0x27106208;
1601  pltmp[9] = pHwData->BB54_cal; /* 0x1054 */
1602  reg->BB54 = pHwData->BB54_cal;
1603  pltmp[10] = 0x52523131; /* 0x1058 IQ_Alpha */
1604  reg->BB58 = 0x52523131;
1605  pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1606  Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1607 
1608  Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1609  break;
1610  }
1611 
1612  /* Fill the LNA table */
1613  reg->LNAValue[0] = (u8) (reg->BB0C & 0xff);
1614  reg->LNAValue[1] = 0;
1615  reg->LNAValue[2] = (u8) ((reg->BB0C & 0xff00) >> 8);
1616  reg->LNAValue[3] = 0;
1617 
1618  /* Fill SQ3 table */
1619  for (i = 0; i < MAX_SQ3_FILTER_SIZE; i++)
1620  reg->SQ3_filter[i] = 0x2f; /* half of Bit 0 ~ 6 */
1621 }
1622 
1623 void set_tx_power_per_channel_max2829(struct hw_data *pHwData, struct chan_info Channel)
1624 {
1625  RFSynthesizer_SetPowerIndex(pHwData, 100);
1626 }
1627 
1628 void set_tx_power_per_channel_al2230(struct hw_data *pHwData, struct chan_info Channel)
1629 {
1630  u8 index = 100;
1631 
1632  if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1633  index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1634 
1635  RFSynthesizer_SetPowerIndex(pHwData, index);
1636 }
1637 
1638 void set_tx_power_per_channel_al7230(struct hw_data *pHwData, struct chan_info Channel)
1639 {
1640  u8 i, index = 100;
1641 
1642  switch (Channel.band) {
1643  case BAND_TYPE_DSSS:
1644  case BAND_TYPE_OFDM_24:
1645  if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1646  index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1647  break;
1648  case BAND_TYPE_OFDM_5:
1649  for (i = 0; i < 35; i++) {
1650  if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) {
1651  if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff)
1652  index = pHwData->TxVgaFor50[i].TxVgaValue;
1653  break;
1654  }
1655  }
1656  break;
1657  }
1658  RFSynthesizer_SetPowerIndex(pHwData, index);
1659 }
1660 
1661 void set_tx_power_per_channel_wb242(struct hw_data *pHwData, struct chan_info Channel)
1662 {
1663  u8 index = 100;
1664 
1665  switch (Channel.band) {
1666  case BAND_TYPE_DSSS:
1667  case BAND_TYPE_OFDM_24:
1668  if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1669  index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1670  break;
1671  case BAND_TYPE_OFDM_5:
1672  break;
1673  }
1674  RFSynthesizer_SetPowerIndex(pHwData, index);
1675 }
1676 
1677 /*
1678  * ==========================================================================
1679  * RFSynthesizer_SwitchingChannel --
1680  *
1681  * Description:
1682  * Swithch the RF channel.
1683  *
1684  * Arguments:
1685  * pHwData - Handle of the USB Device.
1686  * Channel - The channel no.
1687  *
1688  * Return values:
1689  * None.
1690  * ===========================================================================
1691  */
1692 void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info Channel)
1693 {
1694  struct wb35_reg *reg = &pHwData->reg;
1695  u32 pltmp[16]; /* The 16 is the maximum capability of hardware */
1696  u32 count, ltmp;
1697  u8 i, j, number;
1698  u8 ChnlTmp;
1699 
1700  switch (pHwData->phy_type) {
1701  case RF_MAXIM_2825:
1702  case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1703 
1704  if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */
1705  for (i = 0; i < 3; i++)
1706  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_channel_data_24[Channel.ChanNo-1][i], 18);
1707  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1708  }
1709  RFSynthesizer_SetPowerIndex(pHwData, 100);
1710  break;
1711  case RF_MAXIM_2827:
1712  if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */
1713  for (i = 0; i < 3; i++)
1714  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_24[Channel.ChanNo-1][i], 18);
1715  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1716  } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */
1717  ChnlTmp = (Channel.ChanNo - 36) / 4;
1718  for (i = 0; i < 3; i++)
1719  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_50[ChnlTmp][i], 18);
1720  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1721  }
1722  RFSynthesizer_SetPowerIndex(pHwData, 100);
1723  break;
1724  case RF_MAXIM_2828:
1725  if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */
1726  for (i = 0; i < 3; i++)
1727  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_24[Channel.ChanNo-1][i], 18);
1728  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1729  } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */
1730  ChnlTmp = (Channel.ChanNo - 36) / 4;
1731  for (i = 0; i < 3; i++)
1732  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_50[ChnlTmp][i], 18);
1733  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1734  }
1735  RFSynthesizer_SetPowerIndex(pHwData, 100);
1736  break;
1737  case RF_MAXIM_2829:
1738  if (Channel.band <= BAND_TYPE_OFDM_24) {
1739  for (i = 0; i < 3; i++)
1740  pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_24[Channel.ChanNo-1][i], 18);
1741  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1742  } else if (Channel.band == BAND_TYPE_OFDM_5) {
1743  count = ARRAY_SIZE(max2829_channel_data_50);
1744 
1745  for (i = 0; i < count; i++) {
1746  if (max2829_channel_data_50[i][0] == Channel.ChanNo) {
1747  for (j = 0; j < 3; j++)
1748  pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_50[i][j+1], 18);
1749  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1750 
1751  if ((max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946) {
1752  ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A906, 18);
1753  Wb35Reg_Write(pHwData, 0x0864, ltmp);
1754  } else { /* 0x2A9C6 */
1755  ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A986, 18);
1756  Wb35Reg_Write(pHwData, 0x0864, ltmp);
1757  }
1758  }
1759  }
1760  }
1761  set_tx_power_per_channel_max2829(pHwData, Channel);
1762  break;
1763  case RF_AIROHA_2230:
1764  case RF_AIROHA_2230S:
1765  if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */
1766  for (i = 0; i < 2; i++)
1767  pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_channel_data_24[Channel.ChanNo-1][i], 20);
1768  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT);
1769  }
1770  set_tx_power_per_channel_al2230(pHwData, Channel);
1771  break;
1772  case RF_AIROHA_7230:
1773  /* Channel independent registers */
1774  if (Channel.band != pHwData->band) {
1775  if (Channel.band <= BAND_TYPE_OFDM_24) {
1776  /* Update BB register */
1777  BBProcessor_AL7230_2400(pHwData);
1778 
1779  number = ARRAY_SIZE(al7230_rf_data_24);
1780  Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1781  } else {
1782  /* Update BB register */
1783  BBProcessor_AL7230_5000(pHwData);
1784 
1785  number = ARRAY_SIZE(al7230_rf_data_50);
1786  Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1787  }
1788 
1789  /* Write to register. number must less and equal than 16 */
1790  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, number, NO_INCREMENT);
1791  pr_debug("Band changed\n");
1792  }
1793 
1794  if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */
1795  for (i = 0; i < 2; i++)
1796  pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff);
1797  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT);
1798  } else if (Channel.band == BAND_TYPE_OFDM_5) {
1799  /* Update Reg12 */
1800  if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165)) {
1801  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c;
1802  Wb35Reg_Write(pHwData, 0x0864, ltmp);
1803  } else { /* reg12 = 0x00147c at Channel 4920 ~ 5320 */
1804  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c;
1805  Wb35Reg_Write(pHwData, 0x0864, ltmp);
1806  }
1807 
1808  count = ARRAY_SIZE(al7230_channel_data_5);
1809 
1810  for (i = 0; i < count; i++) {
1811  if (al7230_channel_data_5[i][0] == Channel.ChanNo) {
1812  for (j = 0; j < 3; j++)
1813  pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_5[i][j+1] & 0xffffff);
1814  Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1815  }
1816  }
1817  }
1818  set_tx_power_per_channel_al7230(pHwData, Channel);
1819  break;
1820  case RF_WB_242:
1821  case RF_WB_242_1:
1822 
1823  if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */
1824  ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_channel_data_24[Channel.ChanNo-1][0], 24);
1825  Wb35Reg_Write(pHwData, 0x864, ltmp);
1826  }
1827  set_tx_power_per_channel_wb242(pHwData, Channel);
1828  break;
1829  }
1830 
1831  if (Channel.band <= BAND_TYPE_OFDM_24) {
1832  /* BB: select 2.4 GHz, bit[12-11]=00 */
1833  reg->BB50 &= ~(BIT(11) | BIT(12));
1834  Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */
1835  /* MAC: select 2.4 GHz, bit[5]=0 */
1836  reg->M78_ERPInformation &= ~BIT(5);
1837  Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation);
1838  /* enable 11b Baseband */
1839  reg->BB30 &= ~BIT(31);
1840  Wb35Reg_Write(pHwData, 0x1030, reg->BB30);
1841  } else if (Channel.band == BAND_TYPE_OFDM_5) {
1842  /* BB: select 5 GHz */
1843  reg->BB50 &= ~(BIT(11) | BIT(12));
1844  if (Channel.ChanNo <= 64)
1845  reg->BB50 |= BIT(12); /* 10-5.25GHz */
1846  else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124))
1847  reg->BB50 |= BIT(11); /* 01-5.48GHz */
1848  else if ((Channel.ChanNo >= 128) && (Channel.ChanNo <= 161))
1849  reg->BB50 |= (BIT(12) | BIT(11)); /* 11-5.775GHz */
1850  else /* Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 */
1851  reg->BB50 |= BIT(12);
1852  Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */
1853 
1854  /* (1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 */
1855  /* (2) BB30 has been updated previously. */
1856  if (pHwData->phy_type != RF_AIROHA_7230) {
1857  /* MAC: select 5 GHz, bit[5]=1 */
1858  reg->M78_ERPInformation |= BIT(5);
1859  Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation);
1860 
1861  /* disable 11b Baseband */
1862  reg->BB30 |= BIT(31);
1863  Wb35Reg_Write(pHwData, 0x1030, reg->BB30);
1864  }
1865  }
1866 }
1867 
1868 /*
1869  * Set the tx power directly from DUT GUI, not from the EEPROM.
1870  * Return the current setting
1871  */
1872 u8 RFSynthesizer_SetPowerIndex(struct hw_data *pHwData, u8 PowerIndex)
1873 {
1874  u32 Band = pHwData->band;
1875  u8 index = 0;
1876 
1877  if (pHwData->power_index == PowerIndex)
1878  return PowerIndex;
1879 
1880  if (RF_MAXIM_2825 == pHwData->phy_type) {
1881  /* Channel 1 - 13 */
1882  index = RFSynthesizer_SetMaxim2825Power(pHwData, PowerIndex);
1883  } else if (RF_MAXIM_2827 == pHwData->phy_type) {
1884  if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */
1885  index = RFSynthesizer_SetMaxim2827_24Power(pHwData, PowerIndex);
1886  else /* Channel 36 - 64 */
1887  index = RFSynthesizer_SetMaxim2827_50Power(pHwData, PowerIndex);
1888  } else if (RF_MAXIM_2828 == pHwData->phy_type) {
1889  if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */
1890  index = RFSynthesizer_SetMaxim2828_24Power(pHwData, PowerIndex);
1891  else /* Channel 36 - 64 */
1892  index = RFSynthesizer_SetMaxim2828_50Power(pHwData, PowerIndex);
1893  } else if (RF_AIROHA_2230 == pHwData->phy_type) {
1894  /* Power index: 0 ~ 63 --- Channel 1 - 14 */
1895  index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex);
1896  index = (u8) al2230_txvga_data[index][1];
1897  } else if (RF_AIROHA_2230S == pHwData->phy_type) {
1898  /* Power index: 0 ~ 63 --- Channel 1 - 14 */
1899  index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex);
1900  index = (u8) al2230_txvga_data[index][1];
1901  } else if (RF_AIROHA_7230 == pHwData->phy_type) {
1902  /* Power index: 0 ~ 63 */
1903  index = RFSynthesizer_SetAiroha7230Power(pHwData, PowerIndex);
1904  index = (u8)al7230_txvga_data[index][1];
1905  } else if ((RF_WB_242 == pHwData->phy_type) ||
1906  (RF_WB_242_1 == pHwData->phy_type)) {
1907  /* Power index: 0 ~ 19 for original. New range is 0 ~ 33 */
1908  index = RFSynthesizer_SetWinbond242Power(pHwData, PowerIndex);
1909  index = (u8)w89rf242_txvga_data[index][1];
1910  }
1911 
1912  pHwData->power_index = index; /* Backup current */
1913  return index;
1914 }
1915 
1916 /* -- Sub function */
1917 u8 RFSynthesizer_SetMaxim2828_24Power(struct hw_data *pHwData, u8 index)
1918 {
1919  u32 PowerData;
1920  if (index > 1)
1921  index = 1;
1922  PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_24[index], 18);
1923  Wb35Reg_Write(pHwData, 0x0864, PowerData);
1924  return index;
1925 }
1926 
1927 u8 RFSynthesizer_SetMaxim2828_50Power(struct hw_data *pHwData, u8 index)
1928 {
1929  u32 PowerData;
1930  if (index > 1)
1931  index = 1;
1932  PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_50[index], 18);
1933  Wb35Reg_Write(pHwData, 0x0864, PowerData);
1934  return index;
1935 }
1936 
1937 u8 RFSynthesizer_SetMaxim2827_24Power(struct hw_data *pHwData, u8 index)
1938 {
1939  u32 PowerData;
1940  if (index > 1)
1941  index = 1;
1942  PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_24[index], 18);
1943  Wb35Reg_Write(pHwData, 0x0864, PowerData);
1944  return index;
1945 }
1946 
1947 u8 RFSynthesizer_SetMaxim2827_50Power(struct hw_data *pHwData, u8 index)
1948 {
1949  u32 PowerData;
1950  if (index > 1)
1951  index = 1;
1952  PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_50[index], 18);
1953  Wb35Reg_Write(pHwData, 0x0864, PowerData);
1954  return index;
1955 }
1956 
1957 u8 RFSynthesizer_SetMaxim2825Power(struct hw_data *pHwData, u8 index)
1958 {
1959  u32 PowerData;
1960  if (index > 1)
1961  index = 1;
1962  PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_power_data_24[index], 18);
1963  Wb35Reg_Write(pHwData, 0x0864, PowerData);
1964  return index;
1965 }
1966 
1967 u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *pHwData, u8 index)
1968 {
1969  u32 PowerData;
1970  u8 i, count;
1971 
1972  count = ARRAY_SIZE(al2230_txvga_data);
1973  for (i = 0; i < count; i++) {
1974  if (al2230_txvga_data[i][1] >= index)
1975  break;
1976  }
1977  if (i == count)
1978  i--;
1979 
1980  PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_txvga_data[i][0], 20);
1981  Wb35Reg_Write(pHwData, 0x0864, PowerData);
1982  return i;
1983 }
1984 
1985 u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *pHwData, u8 index)
1986 {
1987  u32 PowerData;
1988  u8 i, count;
1989 
1990  count = ARRAY_SIZE(al7230_txvga_data);
1991  for (i = 0; i < count; i++) {
1992  if (al7230_txvga_data[i][1] >= index)
1993  break;
1994  }
1995  if (i == count)
1996  i--;
1997  PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0] & 0xffffff);
1998  Wb35Reg_Write(pHwData, 0x0864, PowerData);
1999  return i;
2000 }
2001 
2002 u8 RFSynthesizer_SetWinbond242Power(struct hw_data *pHwData, u8 index)
2003 {
2004  u32 PowerData;
2005  u8 i, count;
2006 
2007  count = ARRAY_SIZE(w89rf242_txvga_data);
2008  for (i = 0; i < count; i++) {
2009  if (w89rf242_txvga_data[i][1] >= index)
2010  break;
2011  }
2012  if (i == count)
2013  i--;
2014 
2015  /* Set TxVga into RF */
2016  PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_txvga_data[i][0], 24);
2017  Wb35Reg_Write(pHwData, 0x0864, PowerData);
2018 
2019  /* Update BB48 BB4C BB58 for high precision txvga */
2020  Wb35Reg_Write(pHwData, 0x1048, w89rf242_txvga_data[i][2]);
2021  Wb35Reg_Write(pHwData, 0x104c, w89rf242_txvga_data[i][3]);
2022  Wb35Reg_Write(pHwData, 0x1058, w89rf242_txvga_data[i][4]);
2023 
2024  return i;
2025 }
2026 
2027 /*
2028  * ===========================================================================
2029  * Dxx_initial --
2030  * Mxx_initial --
2031  *
2032  * Routine Description:
2033  * Initial the hardware setting and module variable
2034  * ===========================================================================
2035  */
2036 void Dxx_initial(struct hw_data *pHwData)
2037 {
2038  struct wb35_reg *reg = &pHwData->reg;
2039 
2040  /*
2041  * Old IC: Single mode only.
2042  * New IC: operation decide by Software set bit[4]. 1:multiple 0: single
2043  */
2044  reg->D00_DmaControl = 0xc0000004; /* Txon, Rxon, multiple Rx for new 4k DMA */
2045  /* Txon, Rxon, single Rx for old 8k ASIC */
2046  if (!HAL_USB_MODE_BURST(pHwData))
2047  reg->D00_DmaControl = 0xc0000000; /* Txon, Rxon, single Rx for new 4k DMA */
2048 
2049  Wb35Reg_WriteSync(pHwData, 0x0400, reg->D00_DmaControl);
2050 }
2051 
2052 void Mxx_initial(struct hw_data *pHwData)
2053 {
2054  struct wb35_reg *reg = &pHwData->reg;
2055  u32 tmp;
2056  u32 pltmp[11];
2057  u16 i;
2058 
2059 
2060  /*
2061  * ======================================================
2062  * Initial Mxx register
2063  * ======================================================
2064  */
2065 
2066  /* M00 bit set */
2067  reg->M00_MacControl = 0x80000000; /* Solve beacon sequence number stop by hardware */
2068 
2069  /* M24 disable enter power save, BB RxOn and enable NAV attack */
2070  reg->M24_MacControl = 0x08040042;
2071  pltmp[0] = reg->M24_MacControl;
2072 
2073  pltmp[1] = 0; /* Skip M28, because no initialize value is required. */
2074 
2075  /* M2C CWmin and CWmax setting */
2076  pHwData->cwmin = DEFAULT_CWMIN;
2077  pHwData->cwmax = DEFAULT_CWMAX;
2078  reg->M2C_MacControl = DEFAULT_CWMIN << 10;
2079  reg->M2C_MacControl |= DEFAULT_CWMAX;
2080  pltmp[2] = reg->M2C_MacControl;
2081 
2082  /* M30 BSSID */
2083  pltmp[3] = *(u32 *)pHwData->bssid;
2084 
2085  /* M34 */
2086  pHwData->AID = DEFAULT_AID;
2087  tmp = *(u16 *) (pHwData->bssid + 4);
2088  tmp |= DEFAULT_AID << 16;
2089  pltmp[4] = tmp;
2090 
2091  /* M38 */
2092  reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT << 8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
2093  pltmp[5] = reg->M38_MacControl;
2094 
2095  /* M3C */
2096  tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
2097  reg->M3C_MacControl = tmp;
2098  pltmp[6] = tmp;
2099 
2100  /* M40 */
2101  pHwData->slot_time_select = DEFAULT_SLOT_TIME;
2102  tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME;
2103  reg->M40_MacControl = tmp;
2104  pltmp[7] = tmp;
2105 
2106  /* M44 */
2107  tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; /* *1024 */
2108  reg->M44_MacControl = tmp;
2109  pltmp[8] = tmp;
2110 
2111  /* M48 */
2112  pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
2113  pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
2114  tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME;
2115  reg->M48_MacControl = tmp;
2116  pltmp[9] = tmp;
2117 
2118  /* M4C */
2119  reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
2120  pltmp[10] = reg->M4C_MacStatus;
2121 
2122  for (i = 0; i < 11; i++)
2123  Wb35Reg_WriteSync(pHwData, 0x0824 + i * 4, pltmp[i]);
2124 
2125  /* M60 */
2126  Wb35Reg_WriteSync(pHwData, 0x0860, 0x12481248);
2127  reg->M60_MacControl = 0x12481248;
2128 
2129  /* M68 */
2130  Wb35Reg_WriteSync(pHwData, 0x0868, 0x00050900);
2131  reg->M68_MacControl = 0x00050900;
2132 
2133  /* M98 */
2134  Wb35Reg_WriteSync(pHwData, 0x0898, 0xffff8888);
2135  reg->M98_MacControl = 0xffff8888;
2136 }
2137 
2138 
2139 void Uxx_power_off_procedure(struct hw_data *pHwData)
2140 {
2141  /* SW, PMU reset and turn off clock */
2142  Wb35Reg_WriteSync(pHwData, 0x03b0, 3);
2143  Wb35Reg_WriteSync(pHwData, 0x03f0, 0xf9);
2144 }
2145 
2146 /*Decide the TxVga of every channel */
2147 void GetTxVgaFromEEPROM(struct hw_data *pHwData)
2148 {
2149  u32 i, j, ltmp;
2150  u16 Value[MAX_TXVGA_EEPROM];
2151  u8 *pctmp;
2152  u8 ctmp = 0;
2153 
2154  /* Get the entire TxVga setting in EEPROM */
2155  for (i = 0; i < MAX_TXVGA_EEPROM; i++) {
2156  Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000 + 0x00010000 * i);
2157  Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
2158  Value[i] = (u16) (ltmp & 0xffff); /* Get 16 bit available */
2159  Value[i] = cpu_to_le16(Value[i]); /* [7:0]2412 [7:0]2417 .... */
2160  }
2161 
2162  /* Adjust the filed which fills with reserved value. */
2163  pctmp = (u8 *) Value;
2164  for (i = 0; i < (MAX_TXVGA_EEPROM * 2); i++) {
2165  if (pctmp[i] != 0xff)
2166  ctmp = pctmp[i];
2167  else
2168  pctmp[i] = ctmp;
2169  }
2170 
2171  /* Adjust WB_242 to WB_242_1 TxVga scale */
2172  if (pHwData->phy_type == RF_WB_242) {
2173  for (i = 0; i < 4; i++) { /* Only 2412 2437 2462 2484 case must be modified */
2174  for (j = 0; j < ARRAY_SIZE(w89rf242_txvga_old_mapping); j++) {
2175  if (pctmp[i] < (u8) w89rf242_txvga_old_mapping[j][1]) {
2176  pctmp[i] = (u8) w89rf242_txvga_old_mapping[j][0];
2177  break;
2178  }
2179  }
2180 
2181  if (j == ARRAY_SIZE(w89rf242_txvga_old_mapping))
2182  pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0];
2183  }
2184  }
2185 
2186  memcpy(pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM * 2); /* MAX_TXVGA_EEPROM is u16 count */
2187  EEPROMTxVgaAdjust(pHwData);
2188 }
2189 
2190 /*
2191  * This function will affect the TxVga parameter in HAL. If hal_set_current_channel
2192  * or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
2193  * TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
2194  * This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
2195  */
2196 void EEPROMTxVgaAdjust(struct hw_data *pHwData)
2197 {
2198  u8 *pTxVga = pHwData->TxVgaSettingInEEPROM;
2199  s16 i, stmp;
2200 
2201  /* -- 2.4G -- */
2202  /* channel 1 ~ 5 */
2203  stmp = pTxVga[1] - pTxVga[0];
2204  for (i = 0; i < 5; i++)
2205  pHwData->TxVgaFor24[i] = pTxVga[0] + stmp * i / 4;
2206  /* channel 6 ~ 10 */
2207  stmp = pTxVga[2] - pTxVga[1];
2208  for (i = 5; i < 10; i++)
2209  pHwData->TxVgaFor24[i] = pTxVga[1] + stmp * (i - 5) / 4;
2210  /* channel 11 ~ 13 */
2211  stmp = pTxVga[3] - pTxVga[2];
2212  for (i = 10; i < 13; i++)
2213  pHwData->TxVgaFor24[i] = pTxVga[2] + stmp * (i - 10) / 2;
2214  /* channel 14 */
2215  pHwData->TxVgaFor24[13] = pTxVga[3];
2216 
2217  /* -- 5G -- */
2218  if (pHwData->phy_type == RF_AIROHA_7230) {
2219  /* channel 184 */
2220  pHwData->TxVgaFor50[0].ChanNo = 184;
2221  pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4];
2222  /* channel 196 */
2223  pHwData->TxVgaFor50[3].ChanNo = 196;
2224  pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5];
2225  /* interpolate */
2226  pHwData->TxVgaFor50[1].ChanNo = 188;
2227  pHwData->TxVgaFor50[2].ChanNo = 192;
2228  stmp = pTxVga[5] - pTxVga[4];
2229  pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp / 3;
2230  pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp * 2 / 3;
2231 
2232  /* channel 16 */
2233  pHwData->TxVgaFor50[6].ChanNo = 16;
2234  pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6];
2235  pHwData->TxVgaFor50[4].ChanNo = 8;
2236  pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6];
2237  pHwData->TxVgaFor50[5].ChanNo = 12;
2238  pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6];
2239 
2240  /* channel 36 */
2241  pHwData->TxVgaFor50[8].ChanNo = 36;
2242  pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7];
2243  pHwData->TxVgaFor50[7].ChanNo = 34;
2244  pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7];
2245  pHwData->TxVgaFor50[9].ChanNo = 38;
2246  pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7];
2247 
2248  /* channel 40 */
2249  pHwData->TxVgaFor50[10].ChanNo = 40;
2250  pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8];
2251  /* channel 48 */
2252  pHwData->TxVgaFor50[14].ChanNo = 48;
2253  pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9];
2254  /* interpolate */
2255  pHwData->TxVgaFor50[11].ChanNo = 42;
2256  pHwData->TxVgaFor50[12].ChanNo = 44;
2257  pHwData->TxVgaFor50[13].ChanNo = 46;
2258  stmp = pTxVga[9] - pTxVga[8];
2259  pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp / 4;
2260  pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp * 2 / 4;
2261  pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp * 3 / 4;
2262 
2263  /* channel 52 */
2264  pHwData->TxVgaFor50[15].ChanNo = 52;
2265  pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10];
2266  /* channel 64 */
2267  pHwData->TxVgaFor50[18].ChanNo = 64;
2268  pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11];
2269  /* interpolate */
2270  pHwData->TxVgaFor50[16].ChanNo = 56;
2271  pHwData->TxVgaFor50[17].ChanNo = 60;
2272  stmp = pTxVga[11] - pTxVga[10];
2273  pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp / 3;
2274  pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp * 2 / 3;
2275 
2276  /* channel 100 */
2277  pHwData->TxVgaFor50[19].ChanNo = 100;
2278  pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12];
2279  /* channel 112 */
2280  pHwData->TxVgaFor50[22].ChanNo = 112;
2281  pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13];
2282  /* interpolate */
2283  pHwData->TxVgaFor50[20].ChanNo = 104;
2284  pHwData->TxVgaFor50[21].ChanNo = 108;
2285  stmp = pTxVga[13] - pTxVga[12];
2286  pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp / 3;
2287  pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp * 2 / 3;
2288 
2289  /* channel 128 */
2290  pHwData->TxVgaFor50[26].ChanNo = 128;
2291  pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14];
2292  /* interpolate */
2293  pHwData->TxVgaFor50[23].ChanNo = 116;
2294  pHwData->TxVgaFor50[24].ChanNo = 120;
2295  pHwData->TxVgaFor50[25].ChanNo = 124;
2296  stmp = pTxVga[14] - pTxVga[13];
2297  pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp / 4;
2298  pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp * 2 / 4;
2299  pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp * 3 / 4;
2300 
2301  /* channel 140 */
2302  pHwData->TxVgaFor50[29].ChanNo = 140;
2303  pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15];
2304  /* interpolate */
2305  pHwData->TxVgaFor50[27].ChanNo = 132;
2306  pHwData->TxVgaFor50[28].ChanNo = 136;
2307  stmp = pTxVga[15] - pTxVga[14];
2308  pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp / 3;
2309  pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp * 2 / 3;
2310 
2311  /* channel 149 */
2312  pHwData->TxVgaFor50[30].ChanNo = 149;
2313  pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16];
2314  /* channel 165 */
2315  pHwData->TxVgaFor50[34].ChanNo = 165;
2316  pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17];
2317  /* interpolate */
2318  pHwData->TxVgaFor50[31].ChanNo = 153;
2319  pHwData->TxVgaFor50[32].ChanNo = 157;
2320  pHwData->TxVgaFor50[33].ChanNo = 161;
2321  stmp = pTxVga[17] - pTxVga[16];
2322  pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp / 4;
2323  pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp * 2 / 4;
2324  pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp * 3 / 4;
2325  }
2326 }
2327 
2328 void BBProcessor_RateChanging(struct hw_data *pHwData, u8 rate)
2329 {
2330  struct wb35_reg *reg = &pHwData->reg;
2331  unsigned char Is11bRate;
2332 
2333  Is11bRate = (rate % 6) ? 1 : 0;
2334  switch (pHwData->phy_type) {
2335  case RF_AIROHA_2230:
2336  case RF_AIROHA_2230S:
2337  if (Is11bRate) {
2338  if ((reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
2339  (reg->BB4C != BB4C_DEFAULT_AL2230_11B)) {
2340  Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11B);
2341  Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B);
2342  }
2343  } else {
2344  if ((reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
2345  (reg->BB4C != BB4C_DEFAULT_AL2230_11G)) {
2346  Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11G);
2347  Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G);
2348  }
2349  }
2350  break;
2351  case RF_WB_242:
2352  if (Is11bRate) {
2353  if ((reg->BB48 != BB48_DEFAULT_WB242_11B) &&
2354  (reg->BB4C != BB4C_DEFAULT_WB242_11B)) {
2355  reg->BB48 = BB48_DEFAULT_WB242_11B;
2356  reg->BB4C = BB4C_DEFAULT_WB242_11B;
2357  Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11B);
2358  Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11B);
2359  }
2360  } else {
2361  if ((reg->BB48 != BB48_DEFAULT_WB242_11G) &&
2362  (reg->BB4C != BB4C_DEFAULT_WB242_11G)) {
2363  reg->BB48 = BB48_DEFAULT_WB242_11G;
2364  reg->BB4C = BB4C_DEFAULT_WB242_11G;
2365  Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11G);
2366  Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11G);
2367  }
2368  }
2369  break;
2370  }
2371 }
2372 
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