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radeonfb.h
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1 #ifndef __RADEONFB_H__
2 #define __RADEONFB_H__
3 
4 #ifdef CONFIG_FB_RADEON_DEBUG
5 #define DEBUG 1
6 #endif
7 
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/delay.h>
12 #include <linux/pci.h>
13 #include <linux/fb.h>
14 
15 
16 #ifdef CONFIG_FB_RADEON_I2C
17 #include <linux/i2c.h>
18 #include <linux/i2c-algo-bit.h>
19 #endif
20 
21 #include <asm/io.h>
22 
23 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
24 #include <asm/prom.h>
25 #endif
26 
27 #include <video/radeon.h>
28 
29 /***************************************************************
30  * Most of the definitions here are adapted right from XFree86 *
31  ***************************************************************/
32 
33 
34 /*
35  * Chip families. Must fit in the low 16 bits of a long word
36  */
37 enum radeon_family {
38  CHIP_FAMILY_UNKNOW,
39  CHIP_FAMILY_LEGACY,
40  CHIP_FAMILY_RADEON,
41  CHIP_FAMILY_RV100,
42  CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
43  CHIP_FAMILY_RV200,
44  CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
45  RS250 (IGP 7000) */
46  CHIP_FAMILY_R200,
47  CHIP_FAMILY_RV250,
48  CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
49  CHIP_FAMILY_RV280,
50  CHIP_FAMILY_R300,
51  CHIP_FAMILY_R350,
52  CHIP_FAMILY_RV350,
53  CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
54  CHIP_FAMILY_R420, /* R420/R423/M18 */
55  CHIP_FAMILY_RC410,
56  CHIP_FAMILY_RS400,
57  CHIP_FAMILY_RS480,
58  CHIP_FAMILY_LAST,
59 };
60 
61 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
62  ((rinfo)->family == CHIP_FAMILY_RV200) || \
63  ((rinfo)->family == CHIP_FAMILY_RS100) || \
64  ((rinfo)->family == CHIP_FAMILY_RS200) || \
65  ((rinfo)->family == CHIP_FAMILY_RV250) || \
66  ((rinfo)->family == CHIP_FAMILY_RV280) || \
67  ((rinfo)->family == CHIP_FAMILY_RS300))
68 
69 
70 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
71  ((rinfo)->family == CHIP_FAMILY_RV350) || \
72  ((rinfo)->family == CHIP_FAMILY_R350) || \
73  ((rinfo)->family == CHIP_FAMILY_RV380) || \
74  ((rinfo)->family == CHIP_FAMILY_R420) || \
75  ((rinfo)->family == CHIP_FAMILY_RC410) || \
76  ((rinfo)->family == CHIP_FAMILY_RS480))
77 
78 /*
79  * Chip flags
80  */
81 enum radeon_chip_flags {
82  CHIP_FAMILY_MASK = 0x0000ffffUL,
83  CHIP_FLAGS_MASK = 0xffff0000UL,
84  CHIP_IS_MOBILITY = 0x00010000UL,
85  CHIP_IS_IGP = 0x00020000UL,
86  CHIP_HAS_CRTC2 = 0x00040000UL,
87 };
88 
89 /*
90  * Errata workarounds
91  */
92 enum radeon_errata {
93  CHIP_ERRATA_R300_CG = 0x00000001,
94  CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
95  CHIP_ERRATA_PLL_DELAY = 0x00000004,
96 };
97 
98 
99 /*
100  * Monitor types
101  */
102 enum radeon_montype {
103  MT_NONE = 0,
104  MT_CRT, /* CRT */
105  MT_LCD, /* LCD */
106  MT_DFP, /* DVI */
107  MT_CTV, /* composite TV */
108  MT_STV /* S-Video out */
109 };
110 
111 /*
112  * DDC i2c ports
113  */
114 enum ddc_type {
115  ddc_none,
116  ddc_monid,
117  ddc_dvi,
118  ddc_vga,
119  ddc_crt2,
120 };
121 
122 /*
123  * Connector types
124  */
125 enum conn_type {
126  conn_none,
127  conn_proprietary,
128  conn_crt,
129  conn_DVI_I,
130  conn_DVI_D,
131 };
132 
133 
134 /*
135  * PLL infos
136  */
137 struct pll_info {
138  int ppll_max;
139  int ppll_min;
140  int sclk, mclk;
141  int ref_div;
142  int ref_clk;
143 };
144 
145 
146 /*
147  * This structure contains the various registers manipulated by this
148  * driver for setting or restoring a mode. It's mostly copied from
149  * XFree's RADEONSaveRec structure. A few chip settings might still be
150  * tweaked without beeing reflected or saved in these registers though
151  */
152 struct radeon_regs {
153  /* Common registers */
154  u32 ovr_clr;
155  u32 ovr_wid_left_right;
156  u32 ovr_wid_top_bottom;
157  u32 ov0_scale_cntl;
158  u32 mpp_tb_config;
159  u32 mpp_gp_config;
160  u32 subpic_cntl;
161  u32 viph_control;
162  u32 i2c_cntl_1;
163  u32 gen_int_cntl;
164  u32 cap0_trig_cntl;
165  u32 cap1_trig_cntl;
166  u32 bus_cntl;
167  u32 surface_cntl;
168  u32 bios_5_scratch;
169 
170  /* Other registers to save for VT switches or driver load/unload */
171  u32 dp_datatype;
172  u32 rbbm_soft_reset;
173  u32 clock_cntl_index;
174  u32 amcgpio_en_reg;
175  u32 amcgpio_mask;
176 
177  /* Surface/tiling registers */
178  u32 surf_lower_bound[8];
179  u32 surf_upper_bound[8];
180  u32 surf_info[8];
181 
182  /* CRTC registers */
183  u32 crtc_gen_cntl;
184  u32 crtc_ext_cntl;
185  u32 dac_cntl;
186  u32 crtc_h_total_disp;
187  u32 crtc_h_sync_strt_wid;
188  u32 crtc_v_total_disp;
189  u32 crtc_v_sync_strt_wid;
190  u32 crtc_offset;
191  u32 crtc_offset_cntl;
192  u32 crtc_pitch;
193  u32 disp_merge_cntl;
194  u32 grph_buffer_cntl;
195  u32 crtc_more_cntl;
196 
197  /* CRTC2 registers */
198  u32 crtc2_gen_cntl;
199  u32 dac2_cntl;
200  u32 disp_output_cntl;
201  u32 disp_hw_debug;
202  u32 disp2_merge_cntl;
203  u32 grph2_buffer_cntl;
204  u32 crtc2_h_total_disp;
205  u32 crtc2_h_sync_strt_wid;
206  u32 crtc2_v_total_disp;
207  u32 crtc2_v_sync_strt_wid;
208  u32 crtc2_offset;
209  u32 crtc2_offset_cntl;
210  u32 crtc2_pitch;
211 
212  /* Flat panel regs */
213  u32 fp_crtc_h_total_disp;
214  u32 fp_crtc_v_total_disp;
215  u32 fp_gen_cntl;
216  u32 fp2_gen_cntl;
217  u32 fp_h_sync_strt_wid;
218  u32 fp2_h_sync_strt_wid;
219  u32 fp_horz_stretch;
220  u32 fp_panel_cntl;
221  u32 fp_v_sync_strt_wid;
222  u32 fp2_v_sync_strt_wid;
223  u32 fp_vert_stretch;
224  u32 lvds_gen_cntl;
225  u32 lvds_pll_cntl;
226  u32 tmds_crc;
227  u32 tmds_transmitter_cntl;
228 
229  /* Computed values for PLL */
230  u32 dot_clock_freq;
231  int feedback_div;
232  int post_div;
233 
234  /* PLL registers */
235  u32 ppll_div_3;
236  u32 ppll_ref_div;
237  u32 vclk_ecp_cntl;
238  u32 clk_cntl_index;
239 
240  /* Computed values for PLL2 */
241  u32 dot_clock_freq_2;
242  int feedback_div_2;
243  int post_div_2;
244 
245  /* PLL2 registers */
246  u32 p2pll_ref_div;
247  u32 p2pll_div_0;
248  u32 htotal_cntl2;
249 
250  /* Palette */
251  int palette_valid;
252 };
253 
254 struct panel_info {
255  int xres, yres;
256  int valid;
257  int clock;
258  int hOver_plus, hSync_width, hblank;
259  int vOver_plus, vSync_width, vblank;
260  int hAct_high, vAct_high, interlaced;
261  int pwr_delay;
262  int use_bios_dividers;
263  int ref_divider;
264  int post_divider;
265  int fbk_divider;
266 };
267 
268 struct radeonfb_info;
269 
270 #ifdef CONFIG_FB_RADEON_I2C
271 struct radeon_i2c_chan {
272  struct radeonfb_info *rinfo;
273  u32 ddc_reg;
274  struct i2c_adapter adapter;
275  struct i2c_algo_bit_data algo;
276 };
277 #endif
278 
279 enum radeon_pm_mode {
280  radeon_pm_none = 0, /* Nothing supported */
281  radeon_pm_d2 = 0x00000001, /* Can do D2 state */
282  radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
283 };
284 
285 typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
286 
287 struct radeonfb_info {
288  struct fb_info *info;
289 
290  struct radeon_regs state;
291  struct radeon_regs init_state;
292 
293  char name[50];
294 
295  unsigned long mmio_base_phys;
296  unsigned long fb_base_phys;
297 
298  void __iomem *mmio_base;
299  void __iomem *fb_base;
300 
301  unsigned long fb_local_base;
302 
303  struct pci_dev *pdev;
304 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
305  struct device_node *of_node;
306 #endif
307 
308  void __iomem *bios_seg;
309  int fp_bios_start;
310 
311  u32 pseudo_palette[16];
312  struct { u8 red, green, blue, pad; }
313  palette[256];
314 
315  int chipset;
316  u8 family;
317  u8 rev;
318  unsigned int errata;
319  unsigned long video_ram;
320  unsigned long mapped_vram;
321  int vram_width;
322  int vram_ddr;
323 
324  int pitch, bpp, depth;
325 
326  int has_CRTC2;
327  int is_mobility;
328  int is_IGP;
329  int reversed_DAC;
330  int reversed_TMDS;
331  struct panel_info panel_info;
332  int mon1_type;
333  u8 *mon1_EDID;
334  struct fb_videomode *mon1_modedb;
335  int mon1_dbsize;
336  int mon2_type;
337  u8 *mon2_EDID;
338 
339  u32 dp_gui_master_cntl;
340 
341  struct pll_info pll;
342 
343  int mtrr_hdl;
344 
345  int pm_reg;
346  u32 save_regs[100];
347  int asleep;
348  int lock_blank;
349  int dynclk;
350  int no_schedule;
351  enum radeon_pm_mode pm_mode;
352  reinit_function_ptr reinit_func;
353 
354  /* Lock on register access */
355  spinlock_t reg_lock;
356 
357  /* Timer used for delayed LVDS operations */
358  struct timer_list lvds_timer;
359  u32 pending_lvds_gen_cntl;
360 
361 #ifdef CONFIG_FB_RADEON_I2C
362  struct radeon_i2c_chan i2c[4];
363 #endif
364 };
365 
366 
367 #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
368 
369 
370 /*
371  * IO macros
372  */
373 
374 /* Note about this function: we have some rare cases where we must not schedule,
375  * this typically happen with our special "wake up early" hook which allows us to
376  * wake up the graphic chip (and thus get the console back) before everything else
377  * on some machines that support that mechanism. At this point, interrupts are off
378  * and scheduling is not permitted
379  */
380 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
381 {
382  if (rinfo->no_schedule || oops_in_progress)
383  mdelay(ms);
384  else
385  msleep(ms);
386 }
387 
388 
389 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
390 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
391 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
392 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
393 #define INREG(addr) readl((rinfo->mmio_base)+addr)
394 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
395 
396 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
397  u32 val, u32 mask)
398 {
399  unsigned long flags;
400  unsigned int tmp;
401 
402  spin_lock_irqsave(&rinfo->reg_lock, flags);
403  tmp = INREG(addr);
404  tmp &= (mask);
405  tmp |= (val);
406  OUTREG(addr, tmp);
407  spin_unlock_irqrestore(&rinfo->reg_lock, flags);
408 }
409 
410 #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
411 
412 /*
413  * Note about PLL register accesses:
414  *
415  * I have removed the spinlock on them on purpose. The driver now
416  * expects that it will only manipulate the PLL registers in normal
417  * task environment, where radeon_msleep() will be called, protected
418  * by a semaphore (currently the console semaphore) so that no conflict
419  * will happen on the PLL register index.
420  *
421  * With the latest changes to the VT layer, this is guaranteed for all
422  * calls except the actual drawing/blits which aren't supposed to use
423  * the PLL registers anyway
424  *
425  * This is very important for the workarounds to work properly. The only
426  * possible exception to this rule is the call to unblank(), which may
427  * be done at irq time if an oops is in progress.
428  */
429 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
430 {
431  if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
432  return;
433 
434  (void)INREG(CLOCK_CNTL_DATA);
435  (void)INREG(CRTC_GEN_CNTL);
436 }
437 
438 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
439 {
440  if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
441  /* we can't deal with posted writes here ... */
442  _radeon_msleep(rinfo, 5);
443  }
444  if (rinfo->errata & CHIP_ERRATA_R300_CG) {
445  u32 save, tmp;
446  save = INREG(CLOCK_CNTL_INDEX);
447  tmp = save & ~(0x3f | PLL_WR_EN);
448  OUTREG(CLOCK_CNTL_INDEX, tmp);
449  tmp = INREG(CLOCK_CNTL_DATA);
450  OUTREG(CLOCK_CNTL_INDEX, save);
451  }
452 }
453 
454 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
455 {
456  u32 data;
457 
458  OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
459  radeon_pll_errata_after_index(rinfo);
460  data = INREG(CLOCK_CNTL_DATA);
461  radeon_pll_errata_after_data(rinfo);
462  return data;
463 }
464 
465 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
466  u32 val)
467 {
468 
469  OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
470  radeon_pll_errata_after_index(rinfo);
471  OUTREG(CLOCK_CNTL_DATA, val);
472  radeon_pll_errata_after_data(rinfo);
473 }
474 
475 
476 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
477  u32 val, u32 mask)
478 {
479  unsigned int tmp;
480 
481  tmp = __INPLL(rinfo, index);
482  tmp &= (mask);
483  tmp |= (val);
484  __OUTPLL(rinfo, index, tmp);
485 }
486 
487 
488 #define INPLL(addr) __INPLL(rinfo, addr)
489 #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
490 #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
491 
492 
493 #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
494 #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
495  (readb(rinfo->bios_seg + (v) + 1) << 8))
496 #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
497  (readb(rinfo->bios_seg + (v) + 1) << 8) | \
498  (readb(rinfo->bios_seg + (v) + 2) << 16) | \
499  (readb(rinfo->bios_seg + (v) + 3) << 24))
500 
501 /*
502  * Inline utilities
503  */
504 static inline int round_div(int num, int den)
505 {
506  return (num + (den / 2)) / den;
507 }
508 
509 static inline int var_to_depth(const struct fb_var_screeninfo *var)
510 {
511  if (var->bits_per_pixel != 16)
512  return var->bits_per_pixel;
513  return (var->green.length == 5) ? 15 : 16;
514 }
515 
516 static inline u32 radeon_get_dstbpp(u16 depth)
517 {
518  switch (depth) {
519  case 8:
520  return DST_8BPP;
521  case 15:
522  return DST_15BPP;
523  case 16:
524  return DST_16BPP;
525  case 32:
526  return DST_32BPP;
527  default:
528  return 0;
529  }
530 }
531 
532 /*
533  * 2D Engine helper routines
534  */
535 
536 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
537 {
538  int i;
539 
540  for (i=0; i<2000000; i++) {
541  if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
542  return;
543  udelay(1);
544  }
545  printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
546 }
547 
548 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
549 {
550  int i;
551 
552  /* Initiate flush */
553  OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
554  ~RB2D_DC_FLUSH_ALL);
555 
556  /* Ensure FIFO is empty, ie, make sure the flush commands
557  * has reached the cache
558  */
559  _radeon_fifo_wait (rinfo, 64);
560 
561  /* Wait for the flush to complete */
562  for (i=0; i < 2000000; i++) {
563  if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
564  return;
565  udelay(1);
566  }
567  printk(KERN_ERR "radeonfb: Flush Timeout !\n");
568 }
569 
570 
571 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
572 {
573  int i;
574 
575  /* ensure FIFO is empty before waiting for idle */
576  _radeon_fifo_wait (rinfo, 64);
577 
578  for (i=0; i<2000000; i++) {
579  if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
580  radeon_engine_flush (rinfo);
581  return;
582  }
583  udelay(1);
584  }
585  printk(KERN_ERR "radeonfb: Idle Timeout !\n");
586 }
587 
588 
589 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
590 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
591 #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
592 
593 
594 /* I2C Functions */
595 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
596 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
597 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
598 
599 /* PM Functions */
600 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
601 extern int radeonfb_pci_resume(struct pci_dev *pdev);
602 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
603 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
604 
605 /* Monitor probe functions */
606 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
607  const char *monitor_layout, int ignore_edid);
608 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
609 extern int radeon_match_mode(struct radeonfb_info *rinfo,
610  struct fb_var_screeninfo *dest,
611  const struct fb_var_screeninfo *src);
612 
613 /* Accel functions */
614 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
615 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
616 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
617 extern int radeonfb_sync(struct fb_info *info);
618 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
619 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
620 
621 /* Other functions */
622 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
623 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
624  int reg_only);
625 
626 /* Backlight functions */
627 #ifdef CONFIG_FB_RADEON_BACKLIGHT
628 extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
629 extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
630 #else
631 static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
632 static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
633 #endif
634 
635 #endif /* __RADEONFB_H__ */
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