Go to the source code of this file.
| #define cfgCPU_DEFAULTS 0x0007 |
| #define cfgIND_ADDR_A_0 0x0000 |
| #define cfgIND_ADDR_A_1 0x0001 |
| #define cfgIND_ADDR_A_2 0x0002 |
| #define cfgIND_ADDR_B_0 0x0008 |
| #define cfgIND_ADDR_B_1 0x0009 |
| #define cfgIND_ADDR_B_2 0x000A |
| #define cfgIND_DATA_A 0x0003 |
| #define cfgIND_DATA_B 0x000B |
| #define cfgINTF_CNTL 0x0005 |
| #define cfgPM4_RPTR 0x000C |
| #define cfgPM4_WRPTR_0 0x000E |
| #define cfgPM4_WRPTR_1 0x000F |
| #define cfgREG_BASE 0x0004 |
| #define cfgSCRATCH 0x000D |
| #define CHIP_ID_W100 0x57411002 |
| #define CHIP_ID_W3200 0x56441002 |
| #define CHIP_ID_W3220 0x57441002 |
| #define defCFGREG_BASE 0x00000000 |
| #define defCIF_IO 0x000C0902 |
| #define defCPU_DEFAULTS 0x00000006 |
| #define defHW_INT 0x00000000 |
| #define defINTF_CNTL 0x00000011 |
| #define defMC_EXT_MEM_LOCATION 0x07ff0000 |
| #define defTC_MISMATCH 0x00000000 |
| #define defWRAP_START_DIR 0x00000000 |
| #define defWRAP_TOP_DIR 0x00000000 |
| #define DP_SRC_MEM_RECTANGULAR 2 |
| #define GMC_BRUSH_NONE 15 |
| #define GMC_BRUSH_SOLID_COLOR 13 |
| #define MEM_EXT_BASE_VALUE 0x800000 |
| #define MEM_INT_BASE_VALUE 0x100000 |
| #define MEM_INT_SIZE 0x05ffff |
| #define MEM_WINDOW_BASE 0x100000 |
| #define MEM_WINDOW_SIZE 0xf00000 |
| #define mmACTIVE_H_DISP 0x0424 |
| #define mmACTIVE_V_DISP 0x0428 |
| #define mmBM_CONFIG 0x0A1C |
| #define mmBM_DEBUG 0x0A24 |
| #define mmBM_EXT_MEM_BANDWIDTH 0x0A00 |
| #define mmBM_MEM_EXT_CNTL 0x0A0C |
| #define mmBM_MEM_EXT_TIMING_CNTL 0x0A08 |
| #define mmBM_MEM_IO_CNTL 0x0A18 |
| #define mmBM_MEM_MODE_REG 0x0A10 |
| #define mmBM_OFFSET 0x0A04 |
| #define mmBM_PERF2_COUNTERS 0x0A34 |
| #define mmBM_PERF2_MON_CNTL 0x0A30 |
| #define mmBM_PERF_COUNTERS 0x0A2C |
| #define mmBM_PERF_MON_CNTL 0x0A28 |
| #define mmBM_STATUS 0x0A20 |
| #define mmBRIGHTNESS_CNTL 0x045C |
| #define mmBRUSH_OFFSET 0x108C |
| #define mmBRUSH_Y_X 0x1074 |
| #define mmCFGREG_BASE 0x001C |
| #define mmCHIP_STRAP 0x0534 |
| #define mmCIF_CNTL 0x0018 |
| #define mmCIF_READ_DBG 0x0024 |
| #define mmCIF_WRITE_DBG 0x0028 |
| #define mmCLK_PIN_CNTL 0x0080 |
| #define mmCLK_TEST_CNTL 0x0094 |
| #define mmCRTC_ALW 0x04FC |
| #define mmCRTC_ALW_VPOS 0x0500 |
| #define mmCRTC_CV4_END 0x0510 |
| #define mmCRTC_CV4_HPOS 0x0514 |
| #define mmCRTC_CV4_START 0x050C |
| #define mmCRTC_DCLK 0x049C |
| #define mmCRTC_DEFAULT_COUNT 0x04E0 |
| #define mmCRTC_ECK 0x051C |
| #define mmCRTC_FRAME 0x04B0 |
| #define mmCRTC_FRAME_VPOS 0x04B4 |
| #define mmCRTC_GCLK 0x04A8 |
| #define mmCRTC_GCLK_EXT 0x04F8 |
| #define mmCRTC_GOE 0x04AC |
| #define mmCRTC_PS1_ACTIVE 0x04F0 |
| #define mmCRTC_PS1_NACTIVE 0x04F4 |
| #define mmCRTC_PS2 0x04E8 |
| #define mmCRTC_PS2_VPOS 0x04EC |
| #define mmCRTC_PSK 0x0504 |
| #define mmCRTC_PSK_HPOS 0x0508 |
| #define mmCRTC_REV 0x0494 |
| #define mmCRTC_TOTAL 0x0420 |
| #define mmCRTC_VPOS_GS 0x04A4 |
| #define mmDEBUG_BUS_CNTL 0x053C |
| #define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC |
| #define mmDEFAULT_PITCH_OFFSET 0x10A0 |
| #define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8 |
| #define mmDISP_CRC_SIG 0x04DC |
| #define mmDISP_DB_BUF_CNTL 0x04D8 |
| #define mmDISP_DEBUG 0x04D4 |
| #define mmDISP_DEBUG2 0x0538 |
| #define mmDISP_INT_CNTL 0x0488 |
| #define mmDP_BRUSH_FRGD_CLR 0x107C |
| #define mmDP_CNTL_DST_DIR 0x11CC |
| #define mmDP_DATATYPE 0x12C4 |
| #define mmDP_GUI_MASTER_CNTL 0x106C |
| #define mmDP_WRITE_MSK 0x12CC |
| #define mmDST_OFFSET 0x1004 |
| #define mmDST_PITCH 0x1008 |
| #define mmDST_WIDTH_HEIGHT 0x1198 |
| #define mmE2_ARITHMETIC_CNTL 0x1220 |
| #define mmENG_CNTL 0x13E8 |
| #define mmENG_PERF_CNT 0x13F0 |
| #define mmFILTER_COEF 0x1214 |
| #define mmGAMMA_SLOPE 0x0548 |
| #define mmGAMMA_VALUE1 0x0540 |
| #define mmGAMMA_VALUE2 0x0544 |
| #define mmGEN_INT_CNTL 0x0200 |
| #define mmGEN_INT_STATUS 0x0204 |
| #define mmGEN_STATUS 0x054C |
| #define mmGENLCD_CNTL1 0x04CC |
| #define mmGENLCD_CNTL2 0x04D0 |
| #define mmGENLCD_CNTL3 0x0524 |
| #define mmGLOBAL_ALPHA 0x1210 |
| #define mmGPIO_CNTL1 0x04BC |
| #define mmGPIO_CNTL2 0x04C0 |
| #define mmGPIO_CNTL3 0x052C |
| #define mmGPIO_CNTL4 0x0530 |
| #define mmGPIO_DATA 0x04B8 |
| #define mmGPIO_DATA2 0x0528 |
| #define mmGRAPHIC_CTRL 0x0414 |
| #define mmGRAPHIC_H_DISP 0x042C |
| #define mmGRAPHIC_KEY 0x0438 |
| #define mmGRAPHIC_OFFSET 0x0418 |
| #define mmGRAPHIC_PITCH 0x041C |
| #define mmGRAPHIC_V_DISP 0x0430 |
| #define mmIDCT_AUTH 0x0C0C |
| #define mmIDCT_AUTH_CONTROL 0x0C08 |
| #define mmIDCT_CONTROL 0x0C3C |
| #define mmIDCT_LEVELS 0x0C04 |
| #define mmIDCT_RUNS 0x0C00 |
| #define mmISYNC_CNTL 0x1404 |
| #define mmLCD_BACKGROUND_COLOR 0x04E4 |
| #define mmLCD_FORMAT 0x0410 |
| #define mmLCDD_CNTL1 0x04C4 |
| #define mmLCDD_CNTL2 0x04C8 |
| #define mmMC_BIST_COLLAR_READ 0x01A8 |
| #define mmMC_BIST_CTRL 0x01A4 |
| #define mmMC_DEBUG 0x01A0 |
| #define mmMC_EXT_MEM_LOCATION 0x0190 |
| #define mmMC_FB_LOCATION 0x0188 |
| #define mmMC_PERF_COUNTERS 0x01B4 |
| #define mmMC_PERF_MON_CNTL 0x01B0 |
| #define mmMEM_CNTL 0x0180 |
| #define mmMEM_EXT_CNTL 0x018C |
| #define mmMEM_EXT_TIMING_CNTL 0x0194 |
| #define mmMEM_IO_CNTL 0x019C |
| #define mmMEM_SDRAM_MODE_REG 0x0198 |
| #define mmMVC_CNTL_START 0x11E0 |
| #define mmNQWAIT_UNTIL 0x0150 |
| #define mmPCLK_CNTL 0x0090 |
| #define mmPLL_CNTL 0x0088 |
| #define mmPLL_REF_FB_DIV 0x0084 |
| #define mmPWRMGT_CNTL 0x0098 |
| #define mmPWRMGT_STATUS 0x009C |
| #define mmRBBM_CNTL 0x0144 |
| #define mmRBBM_STATUS 0x0140 |
| #define mmREFRESH_CNTL 0x0520 |
| #define mmREVISION_ID 0x0004 |
| #define mmSC_BOTTOM_RIGHT 0x11C0 |
| #define mmSC_TOP_LEFT 0x11BC |
| #define mmSCLK_CNTL 0x008C |
| #define mmSCRATCH_ADDR 0x0284 |
| #define mmSCRATCH_UMSK 0x0280 |
| #define mmSRC_OFFSET 0x11AC |
| #define mmSRC_PITCH 0x11B0 |
| #define mmSRC_SC_BOTTOM_RIGHT 0x11C4 |
| #define mmTC_MISMATCH 0x01AC |
| #define mmVIDEO_CTRL 0x0434 |
| #define mmWAIT_UNTIL 0x1400 |
| #define mmWRAP_BUF_A 0x0008 |
| #define mmWRAP_BUF_B 0x000C |
| #define mmWRAP_START_DIR 0x0014 |
| #define mmWRAP_TOP_DIR 0x0010 |
| #define ROP3_PATCOPY 0xf0 |
| #define ROP3_SRCCOPY 0xcc |
| #define SRC_DATATYPE_EQU_DST 3 |
| #define TESTCLK_SRC_PCLK 0x03 |
| #define TESTCLK_SRC_PLL 0x01 |
| #define TESTCLK_SRC_SCLK 0x02 |
| #define TESTCLK_SRC_XTAL 0x06 |
| #define W100_CFG_BASE 0x0 |
| #define W100_CFG_LEN 0x10 |
| #define W100_REG_BASE 0x10000 |
| #define W100_REG_LEN 0x2000 |
| #define WRAP_BUF_BASE_VALUE 0x80000 |
| #define WRAP_BUF_TOP_VALUE 0xbffff |
mcontroller : adapter info structure for old mimd_t apps
: base address : irq number : number of logical drives : pci bus : pci device : pci function : pci id : vendor id : slot number : unique id
Definition at line 171 of file esd_usb2.c.
| unsigned char access_ind_addr_a |
| unsigned char access_ind_addr_b |
| unsigned char access_scratch_reg |
| u32 compensate_wait_rd_size |
| u32 dis_addr_comp_in_16bit |
| u32 dis_invalidate_by_ops_chnl |
| u32 dis_load_same_byte_addr_cond |
| u32 dis_packer_ful_during_rbbm_timeout |
| u32 dis_pre_fetch_cntl_sm |
| u32 dis_rd_fetch_trig_from_ind_addr |
| u32 dis_rd_same_byte_to_trig_fetch |
| u32 dis_reg_rd_fetch_trig |
| u32 dis_ring_buf_to_force_dec |
| u32 dis_rop_src_uses_dst_w_h |
| u32 dis_src_uses_dst_dirmaj |
| u32 dis_timeout_during_rbbm |
| u32 dly_second_rd_fetch_trig |
| u32 en_block_rd_when_packer_is_not_emp |
| u32 en_dword_split_to_rbbm |
| u32 en_halt_when_reqi_err |
| u32 en_one_clk_setup_before_wait |
| unsigned char en_read_buf_mode |
| u32 en_wait_to_compensate_dq_prop_dly |
| u32 err_reqi_during_idle_clk |
| u32 err_two_reqi_during_ful |
| u32 force_3dclk_when_2dclk |
| u32 gmc_dst_pitch_offset_cntl |
| u32 gmc_src_pitch_offset_cntl |
| u32 interrupt_active_high |
| u32 one_clk_invalidate_pulse |
| unsigned char pack_wr_data |
| unsigned char rd_data_rdy_a |
| unsigned char rd_data_rdy_b |
| unsigned char rd_fetch_scratch |
| unsigned char rd_fetch_trigger_a |
| unsigned char rd_fetch_trigger_b |
| unsigned char transition_size |
| unsigned char unpack_rd_data |
| u32 unpacker_pre_fetch_trig_gen |
| u32 wait_asserted_timeout_val |
1.8.2