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dss_features.c
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1 /*
2  * linux/drivers/video/omap2/dss/dss_features.c
3  *
4  * Copyright (C) 2010 Texas Instruments
5  * Author: Archit Taneja <[email protected]>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program. If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/err.h>
23 #include <linux/slab.h>
24 
25 #include <video/omapdss.h>
26 #include <plat/cpu.h>
27 
28 #include "dss.h"
29 #include "dss_features.h"
30 
31 /* Defines a generic omap register field */
32 struct dss_reg_field {
33  u8 start, end;
34 };
35 
36 struct dss_param_range {
37  int min, max;
38 };
39 
40 struct omap_dss_features {
41  const struct dss_reg_field *reg_fields;
42  const int num_reg_fields;
43 
44  const enum dss_feat_id *features;
45  const int num_features;
46 
47  const int num_mgrs;
48  const int num_ovls;
49  const int num_wbs;
50  const enum omap_display_type *supported_displays;
51  const enum omap_dss_output_id *supported_outputs;
52  const enum omap_color_mode *supported_color_modes;
53  const enum omap_overlay_caps *overlay_caps;
54  const char * const *clksrc_names;
55  const struct dss_param_range *dss_params;
56 
57  const enum omap_dss_rotation_type supported_rotation_types;
58 
59  const u32 buffer_size_unit;
60  const u32 burst_size_unit;
61 };
62 
63 /* This struct is assigned to one of the below during initialization */
64 static const struct omap_dss_features *omap_current_dss_features;
65 
66 static const struct dss_reg_field omap2_dss_reg_fields[] = {
67  [FEAT_REG_FIRHINC] = { 11, 0 },
68  [FEAT_REG_FIRVINC] = { 27, 16 },
69  [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
70  [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
71  [FEAT_REG_FIFOSIZE] = { 8, 0 },
72  [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
73  [FEAT_REG_VERTICALACCU] = { 25, 16 },
74  [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
75  [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
76  [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
77  [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
78  [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
79 };
80 
81 static const struct dss_reg_field omap3_dss_reg_fields[] = {
82  [FEAT_REG_FIRHINC] = { 12, 0 },
83  [FEAT_REG_FIRVINC] = { 28, 16 },
84  [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
85  [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
86  [FEAT_REG_FIFOSIZE] = { 10, 0 },
87  [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
88  [FEAT_REG_VERTICALACCU] = { 25, 16 },
89  [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
90  [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
91  [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
92  [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
93  [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
94 };
95 
96 static const struct dss_reg_field omap4_dss_reg_fields[] = {
97  [FEAT_REG_FIRHINC] = { 12, 0 },
98  [FEAT_REG_FIRVINC] = { 28, 16 },
99  [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
100  [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
101  [FEAT_REG_FIFOSIZE] = { 15, 0 },
102  [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
103  [FEAT_REG_VERTICALACCU] = { 26, 16 },
104  [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
105  [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
106  [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
107  [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
108  [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
109 };
110 
111 static const struct dss_reg_field omap5_dss_reg_fields[] = {
112  [FEAT_REG_FIRHINC] = { 12, 0 },
113  [FEAT_REG_FIRVINC] = { 28, 16 },
114  [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
115  [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
116  [FEAT_REG_FIFOSIZE] = { 15, 0 },
117  [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
118  [FEAT_REG_VERTICALACCU] = { 26, 16 },
119  [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
120  [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
121  [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
122  [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
123  [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
124 };
125 
126 static const enum omap_display_type omap2_dss_supported_displays[] = {
127  /* OMAP_DSS_CHANNEL_LCD */
128  OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
129 
130  /* OMAP_DSS_CHANNEL_DIGIT */
131  OMAP_DISPLAY_TYPE_VENC,
132 };
133 
134 static const enum omap_display_type omap3430_dss_supported_displays[] = {
135  /* OMAP_DSS_CHANNEL_LCD */
136  OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
137  OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
138 
139  /* OMAP_DSS_CHANNEL_DIGIT */
140  OMAP_DISPLAY_TYPE_VENC,
141 };
142 
143 static const enum omap_display_type omap3630_dss_supported_displays[] = {
144  /* OMAP_DSS_CHANNEL_LCD */
145  OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
146  OMAP_DISPLAY_TYPE_DSI,
147 
148  /* OMAP_DSS_CHANNEL_DIGIT */
149  OMAP_DISPLAY_TYPE_VENC,
150 };
151 
152 static const enum omap_display_type omap4_dss_supported_displays[] = {
153  /* OMAP_DSS_CHANNEL_LCD */
154  OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
155 
156  /* OMAP_DSS_CHANNEL_DIGIT */
157  OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
158 
159  /* OMAP_DSS_CHANNEL_LCD2 */
160  OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
161  OMAP_DISPLAY_TYPE_DSI,
162 };
163 
164 static const enum omap_display_type omap5_dss_supported_displays[] = {
165  /* OMAP_DSS_CHANNEL_LCD */
166  OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
167  OMAP_DISPLAY_TYPE_DSI,
168 
169  /* OMAP_DSS_CHANNEL_DIGIT */
170  OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
171 
172  /* OMAP_DSS_CHANNEL_LCD2 */
173  OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
174  OMAP_DISPLAY_TYPE_DSI,
175 };
176 
177 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
178  /* OMAP_DSS_CHANNEL_LCD */
179  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
180 
181  /* OMAP_DSS_CHANNEL_DIGIT */
182  OMAP_DSS_OUTPUT_VENC,
183 };
184 
185 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
186  /* OMAP_DSS_CHANNEL_LCD */
187  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
188  OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
189 
190  /* OMAP_DSS_CHANNEL_DIGIT */
191  OMAP_DSS_OUTPUT_VENC,
192 };
193 
194 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
195  /* OMAP_DSS_CHANNEL_LCD */
196  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
197  OMAP_DSS_OUTPUT_DSI1,
198 
199  /* OMAP_DSS_CHANNEL_DIGIT */
200  OMAP_DSS_OUTPUT_VENC,
201 };
202 
203 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
204  /* OMAP_DSS_CHANNEL_LCD */
205  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
206  OMAP_DSS_OUTPUT_DSI1,
207 
208  /* OMAP_DSS_CHANNEL_DIGIT */
209  OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI |
210  OMAP_DSS_OUTPUT_DPI,
211 
212  /* OMAP_DSS_CHANNEL_LCD2 */
213  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
214  OMAP_DSS_OUTPUT_DSI2,
215 };
216 
217 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
218  /* OMAP_DSS_CHANNEL_LCD */
219  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
220  OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
221 
222  /* OMAP_DSS_CHANNEL_DIGIT */
223  OMAP_DSS_OUTPUT_HDMI | OMAP_DSS_OUTPUT_DPI,
224 
225  /* OMAP_DSS_CHANNEL_LCD2 */
226  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
227  OMAP_DSS_OUTPUT_DSI1,
228 
229  /* OMAP_DSS_CHANNEL_LCD3 */
230  OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
231  OMAP_DSS_OUTPUT_DSI2,
232 };
233 
234 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
235  /* OMAP_DSS_GFX */
236  OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
237  OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
238  OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
239  OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
240 
241  /* OMAP_DSS_VIDEO1 */
242  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
243  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
244  OMAP_DSS_COLOR_UYVY,
245 
246  /* OMAP_DSS_VIDEO2 */
247  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
248  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
249  OMAP_DSS_COLOR_UYVY,
250 };
251 
252 static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
253  /* OMAP_DSS_GFX */
254  OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
255  OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
256  OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
257  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
258  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
259  OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
260 
261  /* OMAP_DSS_VIDEO1 */
262  OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
263  OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
264  OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
265 
266  /* OMAP_DSS_VIDEO2 */
267  OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
268  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
269  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
270  OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
271  OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
272 };
273 
274 static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
275  /* OMAP_DSS_GFX */
276  OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
277  OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
278  OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
279  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
280  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
281  OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
282  OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
283  OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
284 
285  /* OMAP_DSS_VIDEO1 */
286  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
287  OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
288  OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
289  OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
290  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
291  OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
292  OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
293  OMAP_DSS_COLOR_RGBX32,
294 
295  /* OMAP_DSS_VIDEO2 */
296  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
297  OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
298  OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
299  OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
300  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
301  OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
302  OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
303  OMAP_DSS_COLOR_RGBX32,
304 
305  /* OMAP_DSS_VIDEO3 */
306  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
307  OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
308  OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
309  OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
310  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
311  OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
312  OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
313  OMAP_DSS_COLOR_RGBX32,
314 
315  /* OMAP_DSS_WB */
316  OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
317  OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
318  OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
319  OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
320  OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
321  OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
322  OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
323  OMAP_DSS_COLOR_RGBX32,
324 };
325 
326 static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
327  /* OMAP_DSS_GFX */
328  OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
329 
330  /* OMAP_DSS_VIDEO1 */
331  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
332  OMAP_DSS_OVL_CAP_REPLICATION,
333 
334  /* OMAP_DSS_VIDEO2 */
335  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
336  OMAP_DSS_OVL_CAP_REPLICATION,
337 };
338 
339 static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
340  /* OMAP_DSS_GFX */
341  OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
342  OMAP_DSS_OVL_CAP_REPLICATION,
343 
344  /* OMAP_DSS_VIDEO1 */
345  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
346  OMAP_DSS_OVL_CAP_REPLICATION,
347 
348  /* OMAP_DSS_VIDEO2 */
349  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
350  OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
351 };
352 
353 static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
354  /* OMAP_DSS_GFX */
355  OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
356  OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
357 
358  /* OMAP_DSS_VIDEO1 */
359  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
360  OMAP_DSS_OVL_CAP_REPLICATION,
361 
362  /* OMAP_DSS_VIDEO2 */
363  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
364  OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
365  OMAP_DSS_OVL_CAP_REPLICATION,
366 };
367 
368 static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
369  /* OMAP_DSS_GFX */
370  OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
371  OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
372  OMAP_DSS_OVL_CAP_REPLICATION,
373 
374  /* OMAP_DSS_VIDEO1 */
375  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
376  OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
377  OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
378 
379  /* OMAP_DSS_VIDEO2 */
380  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
381  OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
382  OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
383 
384  /* OMAP_DSS_VIDEO3 */
385  OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
386  OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
387  OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
388 };
389 
390 static const char * const omap2_dss_clk_source_names[] = {
391  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
392  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
393  [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
394 };
395 
396 static const char * const omap3_dss_clk_source_names[] = {
397  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
398  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
399  [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
400 };
401 
402 static const char * const omap4_dss_clk_source_names[] = {
403  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
404  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
405  [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
406  [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
407  [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
408 };
409 
410 static const char * const omap5_dss_clk_source_names[] = {
411  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DPLL_DSI1_A_CLK1",
412  [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DPLL_DSI1_A_CLK2",
413  [OMAP_DSS_CLK_SRC_FCK] = "DSS_CLK",
414  [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1",
415  [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DPLL_DSI1_C_CLK2",
416 };
417 
418 static const struct dss_param_range omap2_dss_param_range[] = {
419  [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
420  [FEAT_PARAM_DSS_PCD] = { 2, 255 },
421  [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
422  [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
423  [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
424  [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
425  [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
426  [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
427  [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
428  /*
429  * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
430  * scaler cannot scale a image with width more than 768.
431  */
432  [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
433  [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
434  [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
435 };
436 
437 static const struct dss_param_range omap3_dss_param_range[] = {
438  [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
439  [FEAT_PARAM_DSS_PCD] = { 1, 255 },
440  [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
441  [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
442  [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
443  [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
444  [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
445  [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
446  [FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
447  [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
448  [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
449  [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
450  [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
451 };
452 
453 static const struct dss_param_range omap4_dss_param_range[] = {
454  [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
455  [FEAT_PARAM_DSS_PCD] = { 1, 255 },
456  [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
457  [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
458  [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
459  [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
460  [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
461  [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
462  [FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
463  [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
464  [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
465  [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
466  [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
467 };
468 
469 static const struct dss_param_range omap5_dss_param_range[] = {
470  [FEAT_PARAM_DSS_FCK] = { 0, 200000000 },
471  [FEAT_PARAM_DSS_PCD] = { 1, 255 },
472  [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
473  [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
474  [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
475  [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
476  [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
477  [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
478  [FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
479  [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
480  [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
481  [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
482  [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
483 };
484 
485 static const enum dss_feat_id omap2_dss_feat_list[] = {
486  FEAT_LCDENABLEPOL,
487  FEAT_LCDENABLESIGNAL,
488  FEAT_PCKFREEENABLE,
489  FEAT_FUNCGATED,
490  FEAT_ROWREPEATENABLE,
491  FEAT_RESIZECONF,
492 };
493 
494 static const enum dss_feat_id omap3430_dss_feat_list[] = {
495  FEAT_LCDENABLEPOL,
496  FEAT_LCDENABLESIGNAL,
497  FEAT_PCKFREEENABLE,
498  FEAT_FUNCGATED,
499  FEAT_LINEBUFFERSPLIT,
500  FEAT_ROWREPEATENABLE,
501  FEAT_RESIZECONF,
502  FEAT_DSI_PLL_FREQSEL,
503  FEAT_DSI_REVERSE_TXCLKESC,
504  FEAT_VENC_REQUIRES_TV_DAC_CLK,
505  FEAT_CPR,
506  FEAT_PRELOAD,
507  FEAT_FIR_COEF_V,
508  FEAT_ALPHA_FIXED_ZORDER,
509  FEAT_FIFO_MERGE,
510  FEAT_OMAP3_DSI_FIFO_BUG,
511  FEAT_DPI_USES_VDDS_DSI,
512 };
513 
514 static const enum dss_feat_id am35xx_dss_feat_list[] = {
515  FEAT_LCDENABLEPOL,
516  FEAT_LCDENABLESIGNAL,
517  FEAT_PCKFREEENABLE,
518  FEAT_FUNCGATED,
519  FEAT_LINEBUFFERSPLIT,
520  FEAT_ROWREPEATENABLE,
521  FEAT_RESIZECONF,
522  FEAT_DSI_PLL_FREQSEL,
523  FEAT_DSI_REVERSE_TXCLKESC,
524  FEAT_VENC_REQUIRES_TV_DAC_CLK,
525  FEAT_CPR,
526  FEAT_PRELOAD,
527  FEAT_FIR_COEF_V,
528  FEAT_ALPHA_FIXED_ZORDER,
529  FEAT_FIFO_MERGE,
530  FEAT_OMAP3_DSI_FIFO_BUG,
531 };
532 
533 static const enum dss_feat_id omap3630_dss_feat_list[] = {
534  FEAT_LCDENABLEPOL,
535  FEAT_LCDENABLESIGNAL,
536  FEAT_PCKFREEENABLE,
537  FEAT_FUNCGATED,
538  FEAT_LINEBUFFERSPLIT,
539  FEAT_ROWREPEATENABLE,
540  FEAT_RESIZECONF,
541  FEAT_DSI_PLL_PWR_BUG,
542  FEAT_DSI_PLL_FREQSEL,
543  FEAT_CPR,
544  FEAT_PRELOAD,
545  FEAT_FIR_COEF_V,
546  FEAT_ALPHA_FIXED_ZORDER,
547  FEAT_FIFO_MERGE,
548  FEAT_OMAP3_DSI_FIFO_BUG,
549 };
550 
551 static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
552  FEAT_MGR_LCD2,
553  FEAT_CORE_CLK_DIV,
554  FEAT_LCD_CLK_SRC,
555  FEAT_DSI_DCS_CMD_CONFIG_VC,
556  FEAT_DSI_VC_OCP_WIDTH,
557  FEAT_DSI_GNQ,
558  FEAT_HANDLE_UV_SEPARATE,
559  FEAT_ATTR2,
560  FEAT_CPR,
561  FEAT_PRELOAD,
562  FEAT_FIR_COEF_V,
563  FEAT_ALPHA_FREE_ZORDER,
564  FEAT_FIFO_MERGE,
565  FEAT_BURST_2D,
566 };
567 
568 static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
569  FEAT_MGR_LCD2,
570  FEAT_CORE_CLK_DIV,
571  FEAT_LCD_CLK_SRC,
572  FEAT_DSI_DCS_CMD_CONFIG_VC,
573  FEAT_DSI_VC_OCP_WIDTH,
574  FEAT_DSI_GNQ,
575  FEAT_HDMI_CTS_SWMODE,
576  FEAT_HANDLE_UV_SEPARATE,
577  FEAT_ATTR2,
578  FEAT_CPR,
579  FEAT_PRELOAD,
580  FEAT_FIR_COEF_V,
581  FEAT_ALPHA_FREE_ZORDER,
582  FEAT_FIFO_MERGE,
583  FEAT_BURST_2D,
584 };
585 
586 static const enum dss_feat_id omap4_dss_feat_list[] = {
587  FEAT_MGR_LCD2,
588  FEAT_CORE_CLK_DIV,
589  FEAT_LCD_CLK_SRC,
590  FEAT_DSI_DCS_CMD_CONFIG_VC,
591  FEAT_DSI_VC_OCP_WIDTH,
592  FEAT_DSI_GNQ,
593  FEAT_HDMI_CTS_SWMODE,
594  FEAT_HDMI_AUDIO_USE_MCLK,
595  FEAT_HANDLE_UV_SEPARATE,
596  FEAT_ATTR2,
597  FEAT_CPR,
598  FEAT_PRELOAD,
599  FEAT_FIR_COEF_V,
600  FEAT_ALPHA_FREE_ZORDER,
601  FEAT_FIFO_MERGE,
602  FEAT_BURST_2D,
603 };
604 
605 static const enum dss_feat_id omap5_dss_feat_list[] = {
606  FEAT_MGR_LCD2,
607  FEAT_CORE_CLK_DIV,
608  FEAT_LCD_CLK_SRC,
609  FEAT_DSI_DCS_CMD_CONFIG_VC,
610  FEAT_DSI_VC_OCP_WIDTH,
611  FEAT_DSI_GNQ,
612  FEAT_HDMI_CTS_SWMODE,
613  FEAT_HDMI_AUDIO_USE_MCLK,
614  FEAT_HANDLE_UV_SEPARATE,
615  FEAT_ATTR2,
616  FEAT_CPR,
617  FEAT_PRELOAD,
618  FEAT_FIR_COEF_V,
619  FEAT_ALPHA_FREE_ZORDER,
620  FEAT_FIFO_MERGE,
621  FEAT_BURST_2D,
622  FEAT_DSI_PLL_SELFREQDCO,
623  FEAT_DSI_PLL_REFSEL,
624  FEAT_DSI_PHY_DCC,
625 };
626 
627 /* OMAP2 DSS Features */
628 static const struct omap_dss_features omap2_dss_features = {
629  .reg_fields = omap2_dss_reg_fields,
630  .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
631 
632  .features = omap2_dss_feat_list,
633  .num_features = ARRAY_SIZE(omap2_dss_feat_list),
634 
635  .num_mgrs = 2,
636  .num_ovls = 3,
637  .supported_displays = omap2_dss_supported_displays,
638  .supported_outputs = omap2_dss_supported_outputs,
639  .supported_color_modes = omap2_dss_supported_color_modes,
640  .overlay_caps = omap2_dss_overlay_caps,
641  .clksrc_names = omap2_dss_clk_source_names,
642  .dss_params = omap2_dss_param_range,
643  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
644  .buffer_size_unit = 1,
645  .burst_size_unit = 8,
646 };
647 
648 /* OMAP3 DSS Features */
649 static const struct omap_dss_features omap3430_dss_features = {
650  .reg_fields = omap3_dss_reg_fields,
651  .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
652 
653  .features = omap3430_dss_feat_list,
654  .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
655 
656  .num_mgrs = 2,
657  .num_ovls = 3,
658  .supported_displays = omap3430_dss_supported_displays,
659  .supported_outputs = omap3430_dss_supported_outputs,
660  .supported_color_modes = omap3_dss_supported_color_modes,
661  .overlay_caps = omap3430_dss_overlay_caps,
662  .clksrc_names = omap3_dss_clk_source_names,
663  .dss_params = omap3_dss_param_range,
664  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
665  .buffer_size_unit = 1,
666  .burst_size_unit = 8,
667 };
668 
669 /*
670  * AM35xx DSS Features. This is basically OMAP3 DSS Features without the
671  * vdds_dsi regulator.
672  */
673 static const struct omap_dss_features am35xx_dss_features = {
674  .reg_fields = omap3_dss_reg_fields,
675  .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
676 
677  .features = am35xx_dss_feat_list,
678  .num_features = ARRAY_SIZE(am35xx_dss_feat_list),
679 
680  .num_mgrs = 2,
681  .num_ovls = 3,
682  .supported_displays = omap3430_dss_supported_displays,
683  .supported_outputs = omap3430_dss_supported_outputs,
684  .supported_color_modes = omap3_dss_supported_color_modes,
685  .overlay_caps = omap3430_dss_overlay_caps,
686  .clksrc_names = omap3_dss_clk_source_names,
687  .dss_params = omap3_dss_param_range,
688  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
689  .buffer_size_unit = 1,
690  .burst_size_unit = 8,
691 };
692 
693 static const struct omap_dss_features omap3630_dss_features = {
694  .reg_fields = omap3_dss_reg_fields,
695  .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
696 
697  .features = omap3630_dss_feat_list,
698  .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
699 
700  .num_mgrs = 2,
701  .num_ovls = 3,
702  .supported_displays = omap3630_dss_supported_displays,
703  .supported_outputs = omap3630_dss_supported_outputs,
704  .supported_color_modes = omap3_dss_supported_color_modes,
705  .overlay_caps = omap3630_dss_overlay_caps,
706  .clksrc_names = omap3_dss_clk_source_names,
707  .dss_params = omap3_dss_param_range,
708  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
709  .buffer_size_unit = 1,
710  .burst_size_unit = 8,
711 };
712 
713 /* OMAP4 DSS Features */
714 /* For OMAP4430 ES 1.0 revision */
715 static const struct omap_dss_features omap4430_es1_0_dss_features = {
716  .reg_fields = omap4_dss_reg_fields,
717  .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
718 
719  .features = omap4430_es1_0_dss_feat_list,
720  .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
721 
722  .num_mgrs = 3,
723  .num_ovls = 4,
724  .num_wbs = 1,
725  .supported_displays = omap4_dss_supported_displays,
726  .supported_outputs = omap4_dss_supported_outputs,
727  .supported_color_modes = omap4_dss_supported_color_modes,
728  .overlay_caps = omap4_dss_overlay_caps,
729  .clksrc_names = omap4_dss_clk_source_names,
730  .dss_params = omap4_dss_param_range,
731  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
732  .buffer_size_unit = 16,
733  .burst_size_unit = 16,
734 };
735 
736 /* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
737 static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
738  .reg_fields = omap4_dss_reg_fields,
739  .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
740 
741  .features = omap4430_es2_0_1_2_dss_feat_list,
742  .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
743 
744  .num_mgrs = 3,
745  .num_ovls = 4,
746  .num_wbs = 1,
747  .supported_displays = omap4_dss_supported_displays,
748  .supported_outputs = omap4_dss_supported_outputs,
749  .supported_color_modes = omap4_dss_supported_color_modes,
750  .overlay_caps = omap4_dss_overlay_caps,
751  .clksrc_names = omap4_dss_clk_source_names,
752  .dss_params = omap4_dss_param_range,
753  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
754  .buffer_size_unit = 16,
755  .burst_size_unit = 16,
756 };
757 
758 /* For all the other OMAP4 versions */
759 static const struct omap_dss_features omap4_dss_features = {
760  .reg_fields = omap4_dss_reg_fields,
761  .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
762 
763  .features = omap4_dss_feat_list,
764  .num_features = ARRAY_SIZE(omap4_dss_feat_list),
765 
766  .num_mgrs = 3,
767  .num_ovls = 4,
768  .num_wbs = 1,
769  .supported_displays = omap4_dss_supported_displays,
770  .supported_outputs = omap4_dss_supported_outputs,
771  .supported_color_modes = omap4_dss_supported_color_modes,
772  .overlay_caps = omap4_dss_overlay_caps,
773  .clksrc_names = omap4_dss_clk_source_names,
774  .dss_params = omap4_dss_param_range,
775  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
776  .buffer_size_unit = 16,
777  .burst_size_unit = 16,
778 };
779 
780 /* OMAP5 DSS Features */
781 static const struct omap_dss_features omap5_dss_features = {
782  .reg_fields = omap5_dss_reg_fields,
783  .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
784 
785  .features = omap5_dss_feat_list,
786  .num_features = ARRAY_SIZE(omap5_dss_feat_list),
787 
788  .num_mgrs = 3,
789  .num_ovls = 4,
790  .supported_displays = omap5_dss_supported_displays,
791  .supported_outputs = omap5_dss_supported_outputs,
792  .supported_color_modes = omap4_dss_supported_color_modes,
793  .overlay_caps = omap4_dss_overlay_caps,
794  .clksrc_names = omap5_dss_clk_source_names,
795  .dss_params = omap5_dss_param_range,
796  .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
797  .buffer_size_unit = 16,
798  .burst_size_unit = 16,
799 };
800 
801 #if defined(CONFIG_OMAP4_DSS_HDMI)
802 /* HDMI OMAP4 Functions*/
803 static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
804 
805  .video_configure = ti_hdmi_4xxx_basic_configure,
806  .phy_enable = ti_hdmi_4xxx_phy_enable,
807  .phy_disable = ti_hdmi_4xxx_phy_disable,
808  .read_edid = ti_hdmi_4xxx_read_edid,
809  .detect = ti_hdmi_4xxx_detect,
810  .pll_enable = ti_hdmi_4xxx_pll_enable,
811  .pll_disable = ti_hdmi_4xxx_pll_disable,
812  .video_enable = ti_hdmi_4xxx_wp_video_start,
813  .video_disable = ti_hdmi_4xxx_wp_video_stop,
814  .dump_wrapper = ti_hdmi_4xxx_wp_dump,
815  .dump_core = ti_hdmi_4xxx_core_dump,
816  .dump_pll = ti_hdmi_4xxx_pll_dump,
817  .dump_phy = ti_hdmi_4xxx_phy_dump,
818 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
819  .audio_enable = ti_hdmi_4xxx_wp_audio_enable,
820  .audio_disable = ti_hdmi_4xxx_wp_audio_disable,
821  .audio_start = ti_hdmi_4xxx_audio_start,
822  .audio_stop = ti_hdmi_4xxx_audio_stop,
823  .audio_config = ti_hdmi_4xxx_audio_config,
824 #endif
825 
826 };
827 
828 void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
829 {
830  if (cpu_is_omap44xx())
831  ip_data->ops = &omap4_hdmi_functions;
832 }
833 #endif
834 
835 /* Functions returning values related to a DSS feature */
836 int dss_feat_get_num_mgrs(void)
837 {
838  return omap_current_dss_features->num_mgrs;
839 }
840 
841 int dss_feat_get_num_ovls(void)
842 {
843  return omap_current_dss_features->num_ovls;
844 }
845 
846 int dss_feat_get_num_wbs(void)
847 {
848  return omap_current_dss_features->num_wbs;
849 }
850 
851 unsigned long dss_feat_get_param_min(enum dss_range_param param)
852 {
853  return omap_current_dss_features->dss_params[param].min;
854 }
855 
856 unsigned long dss_feat_get_param_max(enum dss_range_param param)
857 {
858  return omap_current_dss_features->dss_params[param].max;
859 }
860 
861 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
862 {
863  return omap_current_dss_features->supported_displays[channel];
864 }
865 
866 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel)
867 {
868  return omap_current_dss_features->supported_outputs[channel];
869 }
870 
871 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
872 {
873  return omap_current_dss_features->supported_color_modes[plane];
874 }
875 
876 enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
877 {
878  return omap_current_dss_features->overlay_caps[plane];
879 }
880 
881 bool dss_feat_color_mode_supported(enum omap_plane plane,
882  enum omap_color_mode color_mode)
883 {
884  return omap_current_dss_features->supported_color_modes[plane] &
885  color_mode;
886 }
887 
888 const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
889 {
890  return omap_current_dss_features->clksrc_names[id];
891 }
892 
893 u32 dss_feat_get_buffer_size_unit(void)
894 {
895  return omap_current_dss_features->buffer_size_unit;
896 }
897 
898 u32 dss_feat_get_burst_size_unit(void)
899 {
900  return omap_current_dss_features->burst_size_unit;
901 }
902 
903 /* DSS has_feature check */
904 bool dss_has_feature(enum dss_feat_id id)
905 {
906  int i;
907  const enum dss_feat_id *features = omap_current_dss_features->features;
908  const int num_features = omap_current_dss_features->num_features;
909 
910  for (i = 0; i < num_features; i++) {
911  if (features[i] == id)
912  return true;
913  }
914 
915  return false;
916 }
917 
918 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
919 {
920  if (id >= omap_current_dss_features->num_reg_fields)
921  BUG();
922 
923  *start = omap_current_dss_features->reg_fields[id].start;
924  *end = omap_current_dss_features->reg_fields[id].end;
925 }
926 
927 bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
928 {
929  return omap_current_dss_features->supported_rotation_types & rot_type;
930 }
931 
932 void dss_features_init(void)
933 {
934  if (cpu_is_omap24xx())
935  omap_current_dss_features = &omap2_dss_features;
936  else if (cpu_is_omap3630())
937  omap_current_dss_features = &omap3630_dss_features;
938  else if (cpu_is_omap34xx()) {
939  if (soc_is_am35xx()) {
940  omap_current_dss_features = &am35xx_dss_features;
941  } else {
942  omap_current_dss_features = &omap3430_dss_features;
943  }
944  }
945  else if (omap_rev() == OMAP4430_REV_ES1_0)
946  omap_current_dss_features = &omap4430_es1_0_dss_features;
947  else if (omap_rev() == OMAP4430_REV_ES2_0 ||
948  omap_rev() == OMAP4430_REV_ES2_1 ||
949  omap_rev() == OMAP4430_REV_ES2_2)
950  omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
951  else if (cpu_is_omap44xx())
952  omap_current_dss_features = &omap4_dss_features;
953  else if (soc_is_omap54xx())
954  omap_current_dss_features = &omap5_dss_features;
955  else
956  DSSWARN("Unsupported OMAP version");
957 }
Generated on Thu Jan 10 2013 14:41:14 for Linux Kernel by   doxygen 1.8.2