e1000_regs.h File Reference

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Macros
#define	E1000_CTRL   0x00000 /* Device Control - RW */
#define	E1000_STATUS   0x00008 /* Device Status - RO */
#define	E1000_EECD   0x00010 /* EEPROM/Flash Control - RW */
#define	E1000_EERD   0x00014 /* EEPROM Read - RW */
#define	E1000_CTRL_EXT   0x00018 /* Extended Device Control - RW */
#define	E1000_MDIC   0x00020 /* MDI Control - RW */
#define	E1000_MDICNFG   0x00E04 /* MDI Config - RW */
#define	E1000_SCTL   0x00024 /* SerDes Control - RW */
#define	E1000_FCAL   0x00028 /* Flow Control Address Low - RW */
#define	E1000_FCAH   0x0002C /* Flow Control Address High -RW */
#define	E1000_FCT   0x00030 /* Flow Control Type - RW */
#define	E1000_CONNSW   0x00034 /* Copper/Fiber switch control - RW */
#define	E1000_VET   0x00038 /* VLAN Ether Type - RW */
#define	E1000_ICR   0x000C0 /* Interrupt Cause Read - R/clr */
#define	E1000_ITR   0x000C4 /* Interrupt Throttling Rate - RW */
#define	E1000_ICS   0x000C8 /* Interrupt Cause Set - WO */
#define	E1000_IMS   0x000D0 /* Interrupt Mask Set - RW */
#define	E1000_IMC   0x000D8 /* Interrupt Mask Clear - WO */
#define	E1000_IAM   0x000E0 /* Interrupt Acknowledge Auto Mask */
#define	E1000_RCTL   0x00100 /* RX Control - RW */
#define	E1000_FCTTV   0x00170 /* Flow Control Transmit Timer Value - RW */
#define	E1000_TXCW   0x00178 /* TX Configuration Word - RW */
#define	E1000_EICR   0x01580 /* Ext. Interrupt Cause Read - R/clr */
#define	E1000_EITR(_n)   (0x01680 + (0x4 * (_n)))
#define	E1000_EICS   0x01520 /* Ext. Interrupt Cause Set - W0 */
#define	E1000_EIMS   0x01524 /* Ext. Interrupt Mask Set/Read - RW */
#define	E1000_EIMC   0x01528 /* Ext. Interrupt Mask Clear - WO */
#define	E1000_EIAC   0x0152C /* Ext. Interrupt Auto Clear - RW */
#define	E1000_EIAM   0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
#define	E1000_GPIE   0x01514 /* General Purpose Interrupt Enable - RW */
#define	E1000_IVAR0   0x01700 /* Interrupt Vector Allocation (array) - RW */
#define	E1000_IVAR_MISC   0x01740 /* IVAR for "other" causes - RW */
#define	E1000_TCTL   0x00400 /* TX Control - RW */
#define	E1000_TCTL_EXT   0x00404 /* Extended TX Control - RW */
#define	E1000_TIPG   0x00410 /* TX Inter-packet gap -RW */
#define	E1000_AIT   0x00458 /* Adaptive Interframe Spacing Throttle - RW */
#define	E1000_LEDCTL   0x00E00 /* LED Control - RW */
#define	E1000_PBA   0x01000 /* Packet Buffer Allocation - RW */
#define	E1000_PBS   0x01008 /* Packet Buffer Size */
#define	E1000_EEMNGCTL   0x01010 /* MNG EEprom Control */
#define	E1000_EEWR   0x0102C /* EEPROM Write Register - RW */
#define	E1000_I2CCMD   0x01028 /* SFPI2C Command Register - RW */
#define	E1000_FRTIMER   0x01048 /* Free Running Timer - RW */
#define	E1000_TCPTIMER   0x0104C /* TCP Timer - RW */
#define	E1000_FCRTL   0x02160 /* Flow Control Receive Threshold Low - RW */
#define	E1000_FCRTH   0x02168 /* Flow Control Receive Threshold High - RW */
#define	E1000_FCRTV   0x02460 /* Flow Control Refresh Timer Value - RW */
#define	E1000_TSYNCRXCTL   0x0B620 /* Rx Time Sync Control register - RW */
#define	E1000_TSYNCTXCTL   0x0B614 /* Tx Time Sync Control register - RW */
#define	E1000_TSYNCRXCFG   0x05F50 /* Time Sync Rx Configuration - RW */
#define	E1000_RXSTMPL   0x0B624 /* Rx timestamp Low - RO */
#define	E1000_RXSTMPH   0x0B628 /* Rx timestamp High - RO */
#define	E1000_RXSATRL   0x0B62C /* Rx timestamp attribute low - RO */
#define	E1000_RXSATRH   0x0B630 /* Rx timestamp attribute high - RO */
#define	E1000_TXSTMPL   0x0B618 /* Tx timestamp value Low - RO */
#define	E1000_TXSTMPH   0x0B61C /* Tx timestamp value High - RO */
#define	E1000_SYSTIML   0x0B600 /* System time register Low - RO */
#define	E1000_SYSTIMH   0x0B604 /* System time register High - RO */
#define	E1000_TIMINCA   0x0B608 /* Increment attributes register - RW */
#define	E1000_TSAUXC   0x0B640 /* Timesync Auxiliary Control register */
#define	E1000_SYSTIMR   0x0B6F8 /* System time register Residue */
#define	E1000_TSICR   0x0B66C /* Interrupt Cause Register */
#define	E1000_TSIM   0x0B674 /* Interrupt Mask Register */
#define	E1000_SAQF(_n)   (0x5980 + 4 * (_n))
#define	E1000_DAQF(_n)   (0x59A0 + 4 * (_n))
#define	E1000_SPQF(_n)   (0x59C0 + 4 * (_n))
#define	E1000_FTQF(_n)   (0x59E0 + 4 * (_n))
#define	E1000_SAQF0   E1000_SAQF(0)
#define	E1000_DAQF0   E1000_DAQF(0)
#define	E1000_SPQF0   E1000_SPQF(0)
#define	E1000_FTQF0   E1000_FTQF(0)
#define	E1000_SYNQF(_n)   (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
#define	E1000_ETQF(_n)   (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
#define	E1000_RQDPC(_n)   (0x0C030 + ((_n) * 0x40))
#define	E1000_DMACR   0x02508 /* Control Register */
#define	E1000_DMCTXTH   0x03550 /* Transmit Threshold */
#define	E1000_DMCTLX   0x02514 /* Time to Lx Request */
#define	E1000_DMCRTRH   0x05DD0 /* Receive Packet Rate Threshold */
#define	E1000_DMCCNT   0x05DD4 /* Current Rx Count */
#define	E1000_FCRTC   0x02170 /* Flow Control Rx high watermark */
#define	E1000_PCIEMISC   0x05BB8 /* PCIE misc config register */
#define	E1000_RTTDQSEL   0x3604 /* Tx Desc Plane Queue Select - WO */
#define	E1000_RTTBCNRM   0x3690 /* Tx BCN Rate-scheduler MMW */
#define	E1000_RTTBCNRC   0x36B0 /* Tx BCN Rate-Scheduler Config - WO */
#define	E1000_RXPBS   0x02404 /* Rx Packet Buffer Size - RW */
#define	E1000_RDBAL(_n)
#define	E1000_RDBAH(_n)
#define	E1000_RDLEN(_n)
#define	E1000_SRRCTL(_n)
#define	E1000_RDH(_n)
#define	E1000_RDT(_n)
#define	E1000_RXDCTL(_n)
#define	E1000_TDBAL(_n)
#define	E1000_TDBAH(_n)
#define	E1000_TDLEN(_n)
#define	E1000_TDH(_n)
#define	E1000_TDT(_n)
#define	E1000_TXDCTL(_n)
#define	E1000_RXCTL(_n)
#define	E1000_DCA_RXCTRL(_n)   E1000_RXCTL(_n)
#define	E1000_TXCTL(_n)
#define	E1000_DCA_TXCTRL(_n)   E1000_TXCTL(_n)
#define	E1000_TDWBAL(_n)
#define	E1000_TDWBAH(_n)
#define	E1000_TDFH   0x03410 /* TX Data FIFO Head - RW */
#define	E1000_TDFT   0x03418 /* TX Data FIFO Tail - RW */
#define	E1000_TDFHS   0x03420 /* TX Data FIFO Head Saved - RW */
#define	E1000_TDFPC   0x03430 /* TX Data FIFO Packet Count - RW */
#define	E1000_DTXCTL   0x03590 /* DMA TX Control - RW */
#define	E1000_CRCERRS   0x04000 /* CRC Error Count - R/clr */
#define	E1000_ALGNERRC   0x04004 /* Alignment Error Count - R/clr */
#define	E1000_SYMERRS   0x04008 /* Symbol Error Count - R/clr */
#define	E1000_RXERRC   0x0400C /* Receive Error Count - R/clr */
#define	E1000_MPC   0x04010 /* Missed Packet Count - R/clr */
#define	E1000_SCC   0x04014 /* Single Collision Count - R/clr */
#define	E1000_ECOL   0x04018 /* Excessive Collision Count - R/clr */
#define	E1000_MCC   0x0401C /* Multiple Collision Count - R/clr */
#define	E1000_LATECOL   0x04020 /* Late Collision Count - R/clr */
#define	E1000_COLC   0x04028 /* Collision Count - R/clr */
#define	E1000_DC   0x04030 /* Defer Count - R/clr */
#define	E1000_TNCRS   0x04034 /* TX-No CRS - R/clr */
#define	E1000_SEC   0x04038 /* Sequence Error Count - R/clr */
#define	E1000_CEXTERR   0x0403C /* Carrier Extension Error Count - R/clr */
#define	E1000_RLEC   0x04040 /* Receive Length Error Count - R/clr */
#define	E1000_XONRXC   0x04048 /* XON RX Count - R/clr */
#define	E1000_XONTXC   0x0404C /* XON TX Count - R/clr */
#define	E1000_XOFFRXC   0x04050 /* XOFF RX Count - R/clr */
#define	E1000_XOFFTXC   0x04054 /* XOFF TX Count - R/clr */
#define	E1000_FCRUC   0x04058 /* Flow Control RX Unsupported Count- R/clr */
#define	E1000_PRC64   0x0405C /* Packets RX (64 bytes) - R/clr */
#define	E1000_PRC127   0x04060 /* Packets RX (65-127 bytes) - R/clr */
#define	E1000_PRC255   0x04064 /* Packets RX (128-255 bytes) - R/clr */
#define	E1000_PRC511   0x04068 /* Packets RX (255-511 bytes) - R/clr */
#define	E1000_PRC1023   0x0406C /* Packets RX (512-1023 bytes) - R/clr */
#define	E1000_PRC1522   0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
#define	E1000_GPRC   0x04074 /* Good Packets RX Count - R/clr */
#define	E1000_BPRC   0x04078 /* Broadcast Packets RX Count - R/clr */
#define	E1000_MPRC   0x0407C /* Multicast Packets RX Count - R/clr */
#define	E1000_GPTC   0x04080 /* Good Packets TX Count - R/clr */
#define	E1000_GORCL   0x04088 /* Good Octets RX Count Low - R/clr */
#define	E1000_GORCH   0x0408C /* Good Octets RX Count High - R/clr */
#define	E1000_GOTCL   0x04090 /* Good Octets TX Count Low - R/clr */
#define	E1000_GOTCH   0x04094 /* Good Octets TX Count High - R/clr */
#define	E1000_RNBC   0x040A0 /* RX No Buffers Count - R/clr */
#define	E1000_RUC   0x040A4 /* RX Undersize Count - R/clr */
#define	E1000_RFC   0x040A8 /* RX Fragment Count - R/clr */
#define	E1000_ROC   0x040AC /* RX Oversize Count - R/clr */
#define	E1000_RJC   0x040B0 /* RX Jabber Count - R/clr */
#define	E1000_MGTPRC   0x040B4 /* Management Packets RX Count - R/clr */
#define	E1000_MGTPDC   0x040B8 /* Management Packets Dropped Count - R/clr */
#define	E1000_MGTPTC   0x040BC /* Management Packets TX Count - R/clr */
#define	E1000_TORL   0x040C0 /* Total Octets RX Low - R/clr */
#define	E1000_TORH   0x040C4 /* Total Octets RX High - R/clr */
#define	E1000_TOTL   0x040C8 /* Total Octets TX Low - R/clr */
#define	E1000_TOTH   0x040CC /* Total Octets TX High - R/clr */
#define	E1000_TPR   0x040D0 /* Total Packets RX - R/clr */
#define	E1000_TPT   0x040D4 /* Total Packets TX - R/clr */
#define	E1000_PTC64   0x040D8 /* Packets TX (64 bytes) - R/clr */
#define	E1000_PTC127   0x040DC /* Packets TX (65-127 bytes) - R/clr */
#define	E1000_PTC255   0x040E0 /* Packets TX (128-255 bytes) - R/clr */
#define	E1000_PTC511   0x040E4 /* Packets TX (256-511 bytes) - R/clr */
#define	E1000_PTC1023   0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
#define	E1000_PTC1522   0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
#define	E1000_MPTC   0x040F0 /* Multicast Packets TX Count - R/clr */
#define	E1000_BPTC   0x040F4 /* Broadcast Packets TX Count - R/clr */
#define	E1000_TSCTC   0x040F8 /* TCP Segmentation Context TX - R/clr */
#define	E1000_TSCTFC   0x040FC /* TCP Segmentation Context TX Fail - R/clr */
#define	E1000_IAC   0x04100 /* Interrupt Assertion Count */
#define	E1000_ICRXPTC   0x04104
#define	E1000_ICRXATC   0x04108
#define	E1000_ICTXPTC   0x0410C
#define	E1000_ICTXATC   0x04110
#define	E1000_ICTXQEC   0x04118
#define	E1000_ICTXQMTC   0x0411C
#define	E1000_ICRXDMTC   0x04120
#define	E1000_ICRXOC   0x04124 /* Interrupt Cause Receiver Overrun Count */
#define	E1000_PCS_CFG0   0x04200 /* PCS Configuration 0 - RW */
#define	E1000_PCS_LCTL   0x04208 /* PCS Link Control - RW */
#define	E1000_PCS_LSTAT   0x0420C /* PCS Link Status - RO */
#define	E1000_CBTMPC   0x0402C /* Circuit Breaker TX Packet Count */
#define	E1000_HTDPMC   0x0403C /* Host Transmit Discarded Packets */
#define	E1000_CBRMPC   0x040FC /* Circuit Breaker RX Packet Count */
#define	E1000_RPTHC   0x04104 /* Rx Packets To Host */
#define	E1000_HGPTC   0x04118 /* Host Good Packets TX Count */
#define	E1000_HTCBDPC   0x04124 /* Host TX Circuit Breaker Dropped Count */
#define	E1000_HGORCL   0x04128 /* Host Good Octets Received Count Low */
#define	E1000_HGORCH   0x0412C /* Host Good Octets Received Count High */
#define	E1000_HGOTCL   0x04130 /* Host Good Octets Transmit Count Low */
#define	E1000_HGOTCH   0x04134 /* Host Good Octets Transmit Count High */
#define	E1000_LENERRS   0x04138 /* Length Errors Count */
#define	E1000_SCVPC   0x04228 /* SerDes/SGMII Code Violation Pkt Count */
#define	E1000_PCS_ANADV   0x04218 /* AN advertisement - RW */
#define	E1000_PCS_LPAB   0x0421C /* Link Partner Ability - RW */
#define	E1000_PCS_NPTX   0x04220 /* AN Next Page Transmit - RW */
#define	E1000_PCS_LPABNP   0x04224 /* Link Partner Ability Next Page - RW */
#define	E1000_RXCSUM   0x05000 /* RX Checksum Control - RW */
#define	E1000_RLPML   0x05004 /* RX Long Packet Max Length */
#define	E1000_RFCTL   0x05008 /* Receive Filter Control*/
#define	E1000_MTA   0x05200 /* Multicast Table Array - RW Array */
#define	E1000_RA   0x05400 /* Receive Address - RW Array */
#define	E1000_RA2   0x054E0 /* 2nd half of receive address array - RW Array */
#define	E1000_PSRTYPE(_i)   (0x05480 + ((_i) * 4))
#define	E1000_RAL(_i)
#define	E1000_RAH(_i)
#define	E1000_IP4AT_REG(_i)   (0x05840 + ((_i) * 8))
#define	E1000_IP6AT_REG(_i)   (0x05880 + ((_i) * 4))
#define	E1000_WUPM_REG(_i)   (0x05A00 + ((_i) * 4))
#define	E1000_FFMT_REG(_i)   (0x09000 + ((_i) * 8))
#define	E1000_FFVT_REG(_i)   (0x09800 + ((_i) * 8))
#define	E1000_FFLT_REG(_i)   (0x05F00 + ((_i) * 8))
#define	E1000_VFTA   0x05600 /* VLAN Filter Table Array - RW Array */
#define	E1000_VT_CTL   0x0581C /* VMDq Control - RW */
#define	E1000_WUC   0x05800 /* Wakeup Control - RW */
#define	E1000_WUFC   0x05808 /* Wakeup Filter Control - RW */
#define	E1000_WUS   0x05810 /* Wakeup Status - RO */
#define	E1000_MANC   0x05820 /* Management Control - RW */
#define	E1000_IPAV   0x05838 /* IP Address Valid - RW */
#define	E1000_WUPL   0x05900 /* Wakeup Packet Length - RW */
#define	E1000_SW_FW_SYNC   0x05B5C /* Software-Firmware Synchronization - RW */
#define	E1000_CCMCTL   0x05B48 /* CCM Control Register */
#define	E1000_GIOCTL   0x05B44 /* GIO Analog Control Register */
#define	E1000_SCCTL   0x05B4C /* PCIc PLL Configuration Register */
#define	E1000_GCR   0x05B00 /* PCI-Ex Control */
#define	E1000_FACTPS   0x05B30 /* Function Active and Power State to MNG */
#define	E1000_SWSM   0x05B50 /* SW Semaphore */
#define	E1000_FWSM   0x05B54 /* FW Semaphore */
#define	E1000_DCA_CTRL   0x05B74 /* DCA Control - RW */
#define	E1000_MRQC   0x05818 /* Multiple Receive Control - RW */
#define	E1000_IMIR(_i)   (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
#define	E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/
#define	E1000_IMIRVP   0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
#define	E1000_MSIXBM(_i)   (0x01600 + ((_i) * 4))
#define	E1000_RETA(_i)   (0x05C00 + ((_i) * 4))
#define	E1000_RSSRK(_i)   (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
#define	E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
#define	E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
#define	E1000_VFLRE   0x00C88 /* VF Register Events - RWC */
#define	E1000_VFRE   0x00C8C /* VF Receive Enables */
#define	E1000_VFTE   0x00C90 /* VF Transmit Enables */
#define	E1000_QDE   0x02408 /* Queue Drop Enable - RW */
#define	E1000_DTXSWC   0x03500 /* DMA Tx Switch Control - RW */
#define	E1000_WVBR   0x03554 /* VM Wrong Behavior - RWS */
#define	E1000_RPLOLR   0x05AF0 /* Replication Offload - RW */
#define	E1000_UTA   0x0A000 /* Unicast Table Array - RW */
#define	E1000_IOVTCL   0x05BBC /* IOV Control Register */
#define	E1000_TXSWC   0x05ACC /* Tx Switch Control */
#define	E1000_P2VMAILBOX(_n)   (0x00C00 + (4 * (_n)))
#define	E1000_VMBMEM(_n)   (0x00800 + (64 * (_n)))
#define	E1000_VMOLR(_n)   (0x05AD0 + (4 * (_n)))
#define	E1000_VLVF(_n)
#define	E1000_VMVIR(_n)   (0x03700 + (4 * (_n)))
#define	wr32(reg, value)   (writel(value, hw->hw_addr + reg))
#define	rd32(reg)   (readl(hw->hw_addr + reg))
#define	wrfl()   ((void)rd32(E1000_STATUS))
#define	array_wr32(reg, offset, value)   (writel(value, hw->hw_addr + reg + ((offset) << 2)))
#define	array_rd32(reg, offset)   (readl(hw->hw_addr + reg + ((offset) << 2)))
#define	E1000_PCIEMISC   0x05BB8 /* PCIE misc config register */
#define	E1000_IPCNFG   0x0E38 /* Internal PHY Configuration */
#define	E1000_EEER   0x0E30 /* Energy Efficient Ethernet */
#define	E1000_EEE_SU   0X0E34 /* EEE Setup */
#define	E1000_THSTAT   0x08110 /* Thermal Sensor Status */
#define	E1000_B2OSPC   0x08FE0 /* BMC2OS packets sent by BMC */
#define	E1000_B2OGPRC   0x04158 /* BMC2OS packets received by host */
#define	E1000_O2BGPTC   0x08FE4 /* OS2BMC packets received by BMC */
#define	E1000_O2BSPC   0x0415C /* OS2BMC packets transmitted by host */
#define	E1000_SRWR   0x12018 /* Shadow Ram Write Register - RW */
#define	E1000_I210_FLMNGCTL   0x12038
#define	E1000_I210_FLMNGDATA   0x1203C
#define	E1000_I210_FLMNGCNT   0x12040
#define	E1000_I210_FLSWCTL   0x12048
#define	E1000_I210_FLSWDATA   0x1204C
#define	E1000_I210_FLSWCNT   0x12050
#define	E1000_I210_FLA   0x1201C
#define	E1000_INVM_DATA_REG(_n)   (0x12120 + 4*(_n))
#define	E1000_INVM_SIZE   64 /* Number of INVM Data Registers */

Macro Definition Documentation

#define array_rd32	(		reg,
			offset
	)		(readl(hw->hw_addr + reg + ((offset) << 2)))

Definition at line 342 of file e1000_regs.h.

#define array_wr32	(		reg,
			offset,
			value
	)		(writel(value, hw->hw_addr + reg + ((offset) << 2)))

Definition at line 340 of file e1000_regs.h.

#define E1000_AIT   0x00458 /* Adaptive Interframe Spacing Throttle - RW */

Definition at line 66 of file e1000_regs.h.

#define E1000_ALGNERRC   0x04004 /* Alignment Error Count - R/clr */

Definition at line 177 of file e1000_regs.h.

#define E1000_B2OGPRC   0x04158 /* BMC2OS packets received by host */

Definition at line 358 of file e1000_regs.h.

#define E1000_B2OSPC   0x08FE0 /* BMC2OS packets sent by BMC */

Definition at line 357 of file e1000_regs.h.

#define E1000_BPRC   0x04078 /* Broadcast Packets RX Count - R/clr */

Definition at line 203 of file e1000_regs.h.

#define E1000_BPTC   0x040F4 /* Broadcast Packets TX Count - R/clr */

Definition at line 231 of file e1000_regs.h.

#define E1000_CBRMPC   0x040FC /* Circuit Breaker RX Packet Count */

Definition at line 255 of file e1000_regs.h.

#define E1000_CBTMPC   0x0402C /* Circuit Breaker TX Packet Count */

Definition at line 253 of file e1000_regs.h.

#define E1000_CCMCTL   0x05B48 /* CCM Control Register */

Definition at line 296 of file e1000_regs.h.

#define E1000_CEXTERR   0x0403C /* Carrier Extension Error Count - R/clr */

Definition at line 189 of file e1000_regs.h.

#define E1000_COLC   0x04028 /* Collision Count - R/clr */

Definition at line 185 of file e1000_regs.h.

#define E1000_CONNSW   0x00034 /* Copper/Fiber switch control - RW */

Definition at line 42 of file e1000_regs.h.

#define E1000_CRCERRS   0x04000 /* CRC Error Count - R/clr */

Definition at line 176 of file e1000_regs.h.

#define E1000_CTRL   0x00000 /* Device Control - RW */

Definition at line 31 of file e1000_regs.h.

#define E1000_CTRL_EXT   0x00018 /* Extended Device Control - RW */

Definition at line 35 of file e1000_regs.h.

#define E1000_DAQF

(

_n

)

(0x59A0 + 4 * (_n))

Definition at line 99 of file e1000_regs.h.

#define E1000_DAQF0   E1000_DAQF(0)

Definition at line 103 of file e1000_regs.h.

#define E1000_DC   0x04030 /* Defer Count - R/clr */

Definition at line 186 of file e1000_regs.h.

#define E1000_DCA_CTRL   0x05B74 /* DCA Control - RW */

Definition at line 303 of file e1000_regs.h.

#define E1000_DCA_RXCTRL

(

_n

)

E1000_RXCTL(_n)

Definition at line 163 of file e1000_regs.h.

#define E1000_DCA_TXCTRL

(

_n

)

E1000_TXCTL(_n)

Definition at line 166 of file e1000_regs.h.

#define E1000_DMACR   0x02508 /* Control Register */

Definition at line 112 of file e1000_regs.h.

#define E1000_DMCCNT   0x05DD4 /* Current Rx Count */

Definition at line 116 of file e1000_regs.h.

#define E1000_DMCRTRH   0x05DD0 /* Receive Packet Rate Threshold */

Definition at line 115 of file e1000_regs.h.

#define E1000_DMCTLX   0x02514 /* Time to Lx Request */

Definition at line 114 of file e1000_regs.h.

#define E1000_DMCTXTH   0x03550 /* Transmit Threshold */

Definition at line 113 of file e1000_regs.h.

#define E1000_DTXCTL   0x03590 /* DMA TX Control - RW */

Definition at line 175 of file e1000_regs.h.

#define E1000_DTXSWC   0x03500 /* DMA Tx Switch Control - RW */

Definition at line 323 of file e1000_regs.h.

#define E1000_ECOL   0x04018 /* Excessive Collision Count - R/clr */

Definition at line 182 of file e1000_regs.h.

#define E1000_EECD   0x00010 /* EEPROM/Flash Control - RW */

Definition at line 33 of file e1000_regs.h.

#define E1000_EEE_SU   0X0E34 /* EEE Setup */

Definition at line 351 of file e1000_regs.h.

#define E1000_EEER   0x0E30 /* Energy Efficient Ethernet */

Definition at line 350 of file e1000_regs.h.

#define E1000_EEMNGCTL   0x01010 /* MNG EEprom Control */

Definition at line 70 of file e1000_regs.h.

#define E1000_EERD   0x00014 /* EEPROM Read - RW */

Definition at line 34 of file e1000_regs.h.

#define E1000_EEWR   0x0102C /* EEPROM Write Register - RW */

Definition at line 71 of file e1000_regs.h.

#define E1000_EIAC   0x0152C /* Ext. Interrupt Auto Clear - RW */

Definition at line 58 of file e1000_regs.h.

#define E1000_EIAM   0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */

Definition at line 59 of file e1000_regs.h.

#define E1000_EICR   0x01580 /* Ext. Interrupt Cause Read - R/clr */

Definition at line 53 of file e1000_regs.h.

#define E1000_EICS   0x01520 /* Ext. Interrupt Cause Set - W0 */

Definition at line 55 of file e1000_regs.h.

#define E1000_EIMC   0x01528 /* Ext. Interrupt Mask Clear - WO */

Definition at line 57 of file e1000_regs.h.

#define E1000_EIMS   0x01524 /* Ext. Interrupt Mask Set/Read - RW */

Definition at line 56 of file e1000_regs.h.

#define E1000_EITR

(

_n

)

(0x01680 + (0x4 * (_n)))

Definition at line 54 of file e1000_regs.h.

#define E1000_ETQF

(

_n

)

(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */

Definition at line 107 of file e1000_regs.h.

#define E1000_FACTPS   0x05B30 /* Function Active and Power State to MNG */

Definition at line 300 of file e1000_regs.h.

#define E1000_FCAH   0x0002C /* Flow Control Address High -RW */

Definition at line 40 of file e1000_regs.h.

#define E1000_FCAL   0x00028 /* Flow Control Address Low - RW */

Definition at line 39 of file e1000_regs.h.

#define E1000_FCRTC   0x02170 /* Flow Control Rx high watermark */

Definition at line 117 of file e1000_regs.h.

#define E1000_FCRTH   0x02168 /* Flow Control Receive Threshold High - RW */

Definition at line 76 of file e1000_regs.h.

#define E1000_FCRTL   0x02160 /* Flow Control Receive Threshold Low - RW */

Definition at line 75 of file e1000_regs.h.

#define E1000_FCRTV   0x02460 /* Flow Control Refresh Timer Value - RW */

Definition at line 77 of file e1000_regs.h.

#define E1000_FCRUC   0x04058 /* Flow Control RX Unsupported Count- R/clr */

Definition at line 195 of file e1000_regs.h.

#define E1000_FCT   0x00030 /* Flow Control Type - RW */

Definition at line 41 of file e1000_regs.h.

#define E1000_FCTTV   0x00170 /* Flow Control Transmit Timer Value - RW */

Definition at line 51 of file e1000_regs.h.

#define E1000_FFLT_REG

(

_i

)

(0x05F00 + ((_i) * 8))

Definition at line 285 of file e1000_regs.h.

#define E1000_FFMT_REG

(

_i

)

(0x09000 + ((_i) * 8))

Definition at line 283 of file e1000_regs.h.

#define E1000_FFVT_REG

(

_i

)

(0x09800 + ((_i) * 8))

Definition at line 284 of file e1000_regs.h.

#define E1000_FRTIMER   0x01048 /* Free Running Timer - RW */

Definition at line 73 of file e1000_regs.h.

#define E1000_FTQF

(

_n

)

(0x59E0 + 4 * (_n))

Definition at line 101 of file e1000_regs.h.

#define E1000_FTQF0   E1000_FTQF(0)

Definition at line 105 of file e1000_regs.h.

#define E1000_FWSM   0x05B54 /* FW Semaphore */

Definition at line 302 of file e1000_regs.h.

#define E1000_GCR   0x05B00 /* PCI-Ex Control */

Definition at line 299 of file e1000_regs.h.

#define E1000_GIOCTL   0x05B44 /* GIO Analog Control Register */

Definition at line 297 of file e1000_regs.h.

#define E1000_GORCH   0x0408C /* Good Octets RX Count High - R/clr */

Definition at line 207 of file e1000_regs.h.

#define E1000_GORCL   0x04088 /* Good Octets RX Count Low - R/clr */

Definition at line 206 of file e1000_regs.h.

#define E1000_GOTCH   0x04094 /* Good Octets TX Count High - R/clr */

Definition at line 209 of file e1000_regs.h.

#define E1000_GOTCL   0x04090 /* Good Octets TX Count Low - R/clr */

Definition at line 208 of file e1000_regs.h.

#define E1000_GPIE   0x01514 /* General Purpose Interrupt Enable - RW */

Definition at line 60 of file e1000_regs.h.

#define E1000_GPRC   0x04074 /* Good Packets RX Count - R/clr */

Definition at line 202 of file e1000_regs.h.

#define E1000_GPTC   0x04080 /* Good Packets TX Count - R/clr */

Definition at line 205 of file e1000_regs.h.

#define E1000_HGORCH   0x0412C /* Host Good Octets Received Count High */

Definition at line 260 of file e1000_regs.h.

#define E1000_HGORCL   0x04128 /* Host Good Octets Received Count Low */

Definition at line 259 of file e1000_regs.h.

#define E1000_HGOTCH   0x04134 /* Host Good Octets Transmit Count High */

Definition at line 262 of file e1000_regs.h.

#define E1000_HGOTCL   0x04130 /* Host Good Octets Transmit Count Low */

Definition at line 261 of file e1000_regs.h.

#define E1000_HGPTC   0x04118 /* Host Good Packets TX Count */

Definition at line 257 of file e1000_regs.h.

#define E1000_HTCBDPC   0x04124 /* Host TX Circuit Breaker Dropped Count */

Definition at line 258 of file e1000_regs.h.

#define E1000_HTDPMC   0x0403C /* Host Transmit Discarded Packets */

Definition at line 254 of file e1000_regs.h.

#define E1000_I210_FLA   0x1201C

Definition at line 371 of file e1000_regs.h.

#define E1000_I210_FLMNGCNT   0x12040

Definition at line 365 of file e1000_regs.h.

#define E1000_I210_FLMNGCTL   0x12038

Definition at line 363 of file e1000_regs.h.

#define E1000_I210_FLMNGDATA   0x1203C

Definition at line 364 of file e1000_regs.h.

#define E1000_I210_FLSWCNT   0x12050

Definition at line 369 of file e1000_regs.h.

#define E1000_I210_FLSWCTL   0x12048

Definition at line 367 of file e1000_regs.h.

#define E1000_I210_FLSWDATA   0x1204C

Definition at line 368 of file e1000_regs.h.

#define E1000_I2CCMD   0x01028 /* SFPI2C Command Register - RW */

Definition at line 72 of file e1000_regs.h.

#define E1000_IAC   0x04100 /* Interrupt Assertion Count */

Definition at line 234 of file e1000_regs.h.

#define E1000_IAM   0x000E0 /* Interrupt Acknowledge Auto Mask */

Definition at line 49 of file e1000_regs.h.

#define E1000_ICR   0x000C0 /* Interrupt Cause Read - R/clr */

Definition at line 44 of file e1000_regs.h.

#define E1000_ICRXATC   0x04108

Definition at line 238 of file e1000_regs.h.

#define E1000_ICRXDMTC   0x04120

Definition at line 248 of file e1000_regs.h.

#define E1000_ICRXOC   0x04124 /* Interrupt Cause Receiver Overrun Count */

Definition at line 249 of file e1000_regs.h.

#define E1000_ICRXPTC   0x04104

Definition at line 236 of file e1000_regs.h.

#define E1000_ICS   0x000C8 /* Interrupt Cause Set - WO */

Definition at line 46 of file e1000_regs.h.

#define E1000_ICTXATC   0x04110

Definition at line 242 of file e1000_regs.h.

#define E1000_ICTXPTC   0x0410C

Definition at line 240 of file e1000_regs.h.

#define E1000_ICTXQEC   0x04118

Definition at line 244 of file e1000_regs.h.

#define E1000_ICTXQMTC   0x0411C

Definition at line 246 of file e1000_regs.h.

#define E1000_IMC   0x000D8 /* Interrupt Mask Clear - WO */

Definition at line 48 of file e1000_regs.h.

#define E1000_IMIR

(

_i

)

(0x05A80 + ((_i) * 4)) /* Immediate Interrupt */

Definition at line 307 of file e1000_regs.h.

#define E1000_IMIREXT

(

_i

)

(0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/

Definition at line 308 of file e1000_regs.h.

#define E1000_IMIRVP   0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */

Definition at line 309 of file e1000_regs.h.

#define E1000_IMS   0x000D0 /* Interrupt Mask Set - RW */

Definition at line 47 of file e1000_regs.h.

#define E1000_INVM_DATA_REG

(

_n

)

(0x12120 + 4*(_n))

Definition at line 373 of file e1000_regs.h.

#define E1000_INVM_SIZE   64 /* Number of INVM Data Registers */

Definition at line 374 of file e1000_regs.h.

#define E1000_IOVTCL   0x05BBC /* IOV Control Register */

Definition at line 327 of file e1000_regs.h.

#define E1000_IP4AT_REG

(

_i

)

(0x05840 + ((_i) * 8))

Definition at line 280 of file e1000_regs.h.

#define E1000_IP6AT_REG

(

_i

)

(0x05880 + ((_i) * 4))

Definition at line 281 of file e1000_regs.h.

#define E1000_IPAV   0x05838 /* IP Address Valid - RW */

Definition at line 292 of file e1000_regs.h.

#define E1000_IPCNFG   0x0E38 /* Internal PHY Configuration */

Definition at line 349 of file e1000_regs.h.

#define E1000_ITR   0x000C4 /* Interrupt Throttling Rate - RW */

Definition at line 45 of file e1000_regs.h.

#define E1000_IVAR0   0x01700 /* Interrupt Vector Allocation (array) - RW */

Definition at line 61 of file e1000_regs.h.

#define E1000_IVAR_MISC   0x01740 /* IVAR for "other" causes - RW */

Definition at line 62 of file e1000_regs.h.

#define E1000_LATECOL   0x04020 /* Late Collision Count - R/clr */

Definition at line 184 of file e1000_regs.h.

#define E1000_LEDCTL   0x00E00 /* LED Control - RW */

Definition at line 67 of file e1000_regs.h.

#define E1000_LENERRS   0x04138 /* Length Errors Count */

Definition at line 263 of file e1000_regs.h.

#define E1000_MANC   0x05820 /* Management Control - RW */

Definition at line 291 of file e1000_regs.h.

#define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */

Definition at line 317 of file e1000_regs.h.

#define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */

Definition at line 318 of file e1000_regs.h.

#define E1000_MCC   0x0401C /* Multiple Collision Count - R/clr */

Definition at line 183 of file e1000_regs.h.

#define E1000_MDIC   0x00020 /* MDI Control - RW */

Definition at line 36 of file e1000_regs.h.

#define E1000_MDICNFG   0x00E04 /* MDI Config - RW */

Definition at line 37 of file e1000_regs.h.

#define E1000_MGTPDC   0x040B8 /* Management Packets Dropped Count - R/clr */

Definition at line 216 of file e1000_regs.h.

#define E1000_MGTPRC   0x040B4 /* Management Packets RX Count - R/clr */

Definition at line 215 of file e1000_regs.h.

#define E1000_MGTPTC   0x040BC /* Management Packets TX Count - R/clr */

Definition at line 217 of file e1000_regs.h.

#define E1000_MPC   0x04010 /* Missed Packet Count - R/clr */

Definition at line 180 of file e1000_regs.h.

#define E1000_MPRC   0x0407C /* Multicast Packets RX Count - R/clr */

Definition at line 204 of file e1000_regs.h.

#define E1000_MPTC   0x040F0 /* Multicast Packets TX Count - R/clr */

Definition at line 230 of file e1000_regs.h.

#define E1000_MRQC   0x05818 /* Multiple Receive Control - RW */

Definition at line 306 of file e1000_regs.h.

#define E1000_MSIXBM

(

_i

)

(0x01600 + ((_i) * 4))

Definition at line 311 of file e1000_regs.h.

#define E1000_MTA   0x05200 /* Multicast Table Array - RW Array */

Definition at line 272 of file e1000_regs.h.

#define E1000_O2BGPTC   0x08FE4 /* OS2BMC packets received by BMC */

Definition at line 359 of file e1000_regs.h.

#define E1000_O2BSPC   0x0415C /* OS2BMC packets transmitted by host */

Definition at line 360 of file e1000_regs.h.

#define E1000_P2VMAILBOX

(

_n

)

(0x00C00 + (4 * (_n)))

Definition at line 330 of file e1000_regs.h.

#define E1000_PBA   0x01000 /* Packet Buffer Allocation - RW */

Definition at line 68 of file e1000_regs.h.

#define E1000_PBS   0x01008 /* Packet Buffer Size */

Definition at line 69 of file e1000_regs.h.

#define E1000_PCIEMISC   0x05BB8 /* PCIE misc config register */

Definition at line 346 of file e1000_regs.h.

#define E1000_PCIEMISC   0x05BB8 /* PCIE misc config register */

Definition at line 346 of file e1000_regs.h.

#define E1000_PCS_ANADV   0x04218 /* AN advertisement - RW */

Definition at line 265 of file e1000_regs.h.

#define E1000_PCS_CFG0   0x04200 /* PCS Configuration 0 - RW */

Definition at line 250 of file e1000_regs.h.

#define E1000_PCS_LCTL   0x04208 /* PCS Link Control - RW */

Definition at line 251 of file e1000_regs.h.

#define E1000_PCS_LPAB   0x0421C /* Link Partner Ability - RW */

Definition at line 266 of file e1000_regs.h.

#define E1000_PCS_LPABNP   0x04224 /* Link Partner Ability Next Page - RW */

Definition at line 268 of file e1000_regs.h.

#define E1000_PCS_LSTAT   0x0420C /* PCS Link Status - RO */

Definition at line 252 of file e1000_regs.h.

#define E1000_PCS_NPTX   0x04220 /* AN Next Page Transmit - RW */

Definition at line 267 of file e1000_regs.h.

#define E1000_PRC1023   0x0406C /* Packets RX (512-1023 bytes) - R/clr */

Definition at line 200 of file e1000_regs.h.

#define E1000_PRC127   0x04060 /* Packets RX (65-127 bytes) - R/clr */

Definition at line 197 of file e1000_regs.h.

#define E1000_PRC1522   0x04070 /* Packets RX (1024-1522 bytes) - R/clr */

Definition at line 201 of file e1000_regs.h.

#define E1000_PRC255   0x04064 /* Packets RX (128-255 bytes) - R/clr */

Definition at line 198 of file e1000_regs.h.

#define E1000_PRC511   0x04068 /* Packets RX (255-511 bytes) - R/clr */

Definition at line 199 of file e1000_regs.h.

#define E1000_PRC64   0x0405C /* Packets RX (64 bytes) - R/clr */

Definition at line 196 of file e1000_regs.h.

#define E1000_PSRTYPE

(

_i

)

(0x05480 + ((_i) * 4))

Definition at line 275 of file e1000_regs.h.

#define E1000_PTC1023   0x040E8 /* Packets TX (512-1023 bytes) - R/clr */

Definition at line 228 of file e1000_regs.h.

#define E1000_PTC127   0x040DC /* Packets TX (65-127 bytes) - R/clr */

Definition at line 225 of file e1000_regs.h.

#define E1000_PTC1522   0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */

Definition at line 229 of file e1000_regs.h.

#define E1000_PTC255   0x040E0 /* Packets TX (128-255 bytes) - R/clr */

Definition at line 226 of file e1000_regs.h.

#define E1000_PTC511   0x040E4 /* Packets TX (256-511 bytes) - R/clr */

Definition at line 227 of file e1000_regs.h.

#define E1000_PTC64   0x040D8 /* Packets TX (64 bytes) - R/clr */

Definition at line 224 of file e1000_regs.h.

#define E1000_QDE   0x02408 /* Queue Drop Enable - RW */

Definition at line 322 of file e1000_regs.h.

#define E1000_RA   0x05400 /* Receive Address - RW Array */

Definition at line 273 of file e1000_regs.h.

#define E1000_RA2   0x054E0 /* 2nd half of receive address array - RW Array */

Definition at line 274 of file e1000_regs.h.

#define E1000_RAH

(

_i

)

Value:

(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
                                       (0x054E4 + ((_i - 16) * 8)))

Definition at line 278 of file e1000_regs.h.

#define E1000_RAL

(

_i

)

Value:

(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
                                       (0x054E0 + ((_i - 16) * 8)))

Definition at line 276 of file e1000_regs.h.

#define E1000_RCTL   0x00100 /* RX Control - RW */

Definition at line 50 of file e1000_regs.h.

#define E1000_RDBAH

(

_n

)

Value:

((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \
                    : (0x0C004 + ((_n) * 0x40)))

Definition at line 137 of file e1000_regs.h.

#define E1000_RDBAL

(

_n

)

Value:

((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \
                    : (0x0C000 + ((_n) * 0x40)))

Definition at line 135 of file e1000_regs.h.

#define E1000_RDH

(

_n

)

Value:

((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \
                    : (0x0C010 + ((_n) * 0x40)))

Definition at line 143 of file e1000_regs.h.

#define E1000_RDLEN

(

_n

)

Value:

((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \
                    : (0x0C008 + ((_n) * 0x40)))

Definition at line 139 of file e1000_regs.h.

#define E1000_RDT

(

_n

)

Value:

((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \
                    : (0x0C018 + ((_n) * 0x40)))

Definition at line 145 of file e1000_regs.h.

#define E1000_RETA

(

_i

)

(0x05C00 + ((_i) * 4))

Definition at line 313 of file e1000_regs.h.

#define E1000_RFC   0x040A8 /* RX Fragment Count - R/clr */

Definition at line 212 of file e1000_regs.h.

#define E1000_RFCTL   0x05008 /* Receive Filter Control*/

Definition at line 271 of file e1000_regs.h.

#define E1000_RJC   0x040B0 /* RX Jabber Count - R/clr */

Definition at line 214 of file e1000_regs.h.

#define E1000_RLEC   0x04040 /* Receive Length Error Count - R/clr */

Definition at line 190 of file e1000_regs.h.

#define E1000_RLPML   0x05004 /* RX Long Packet Max Length */

Definition at line 270 of file e1000_regs.h.

#define E1000_RNBC   0x040A0 /* RX No Buffers Count - R/clr */

Definition at line 210 of file e1000_regs.h.

#define E1000_ROC   0x040AC /* RX Oversize Count - R/clr */

Definition at line 213 of file e1000_regs.h.

#define E1000_RPLOLR   0x05AF0 /* Replication Offload - RW */

Definition at line 325 of file e1000_regs.h.

#define E1000_RPTHC   0x04104 /* Rx Packets To Host */

Definition at line 256 of file e1000_regs.h.

#define E1000_RQDPC

(

_n

)

(0x0C030 + ((_n) * 0x40))

Definition at line 109 of file e1000_regs.h.

#define E1000_RSSRK

(

_i

)

(0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */

Definition at line 314 of file e1000_regs.h.

#define E1000_RTTBCNRC   0x36B0 /* Tx BCN Rate-Scheduler Config - WO */

Definition at line 123 of file e1000_regs.h.

#define E1000_RTTBCNRM   0x3690 /* Tx BCN Rate-scheduler MMW */

Definition at line 122 of file e1000_regs.h.

#define E1000_RTTDQSEL   0x3604 /* Tx Desc Plane Queue Select - WO */

Definition at line 121 of file e1000_regs.h.

#define E1000_RUC   0x040A4 /* RX Undersize Count - R/clr */

Definition at line 211 of file e1000_regs.h.

#define E1000_RXCSUM   0x05000 /* RX Checksum Control - RW */

Definition at line 269 of file e1000_regs.h.

#define E1000_RXCTL

(

_n

)

Value:

((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
                      (0x0C014 + ((_n) * 0x40)))

Definition at line 161 of file e1000_regs.h.

#define E1000_RXDCTL

(

_n

)

Value:

((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \
                    : (0x0C028 + ((_n) * 0x40)))

Definition at line 147 of file e1000_regs.h.

#define E1000_RXERRC   0x0400C /* Receive Error Count - R/clr */

Definition at line 179 of file e1000_regs.h.

#define E1000_RXPBS   0x02404 /* Rx Packet Buffer Size - RW */

Definition at line 126 of file e1000_regs.h.

#define E1000_RXSATRH   0x0B630 /* Rx timestamp attribute high - RO */

Definition at line 86 of file e1000_regs.h.

#define E1000_RXSATRL   0x0B62C /* Rx timestamp attribute low - RO */

Definition at line 85 of file e1000_regs.h.

#define E1000_RXSTMPH   0x0B628 /* Rx timestamp High - RO */

Definition at line 84 of file e1000_regs.h.

#define E1000_RXSTMPL   0x0B624 /* Rx timestamp Low - RO */

Definition at line 83 of file e1000_regs.h.

#define E1000_SAQF

(

_n

)

(0x5980 + 4 * (_n))

Definition at line 98 of file e1000_regs.h.

#define E1000_SAQF0   E1000_SAQF(0)

Definition at line 102 of file e1000_regs.h.

#define E1000_SCC   0x04014 /* Single Collision Count - R/clr */

Definition at line 181 of file e1000_regs.h.

#define E1000_SCCTL   0x05B4C /* PCIc PLL Configuration Register */

Definition at line 298 of file e1000_regs.h.

#define E1000_SCTL   0x00024 /* SerDes Control - RW */

Definition at line 38 of file e1000_regs.h.

#define E1000_SCVPC   0x04228 /* SerDes/SGMII Code Violation Pkt Count */

Definition at line 264 of file e1000_regs.h.

#define E1000_SEC   0x04038 /* Sequence Error Count - R/clr */

Definition at line 188 of file e1000_regs.h.

#define E1000_SPQF

(

_n

)

(0x59C0 + 4 * (_n))

Definition at line 100 of file e1000_regs.h.

#define E1000_SPQF0   E1000_SPQF(0)

Definition at line 104 of file e1000_regs.h.

#define E1000_SRRCTL

(

_n

)

Value:

((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \
                    : (0x0C00C + ((_n) * 0x40)))

Definition at line 141 of file e1000_regs.h.

#define E1000_SRWR   0x12018 /* Shadow Ram Write Register - RW */

Definition at line 362 of file e1000_regs.h.

#define E1000_STATUS   0x00008 /* Device Status - RO */

Definition at line 32 of file e1000_regs.h.

#define E1000_SW_FW_SYNC   0x05B5C /* Software-Firmware Synchronization - RW */

Definition at line 295 of file e1000_regs.h.

#define E1000_SWSM   0x05B50 /* SW Semaphore */

Definition at line 301 of file e1000_regs.h.

#define E1000_SYMERRS   0x04008 /* Symbol Error Count - R/clr */

Definition at line 178 of file e1000_regs.h.

#define E1000_SYNQF

(

_n

)

(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */

Definition at line 106 of file e1000_regs.h.

#define E1000_SYSTIMH   0x0B604 /* System time register High - RO */

Definition at line 90 of file e1000_regs.h.

#define E1000_SYSTIML   0x0B600 /* System time register Low - RO */

Definition at line 89 of file e1000_regs.h.

#define E1000_SYSTIMR   0x0B6F8 /* System time register Residue */

Definition at line 93 of file e1000_regs.h.

#define E1000_TCPTIMER   0x0104C /* TCP Timer - RW */

Definition at line 74 of file e1000_regs.h.

#define E1000_TCTL   0x00400 /* TX Control - RW */

Definition at line 63 of file e1000_regs.h.

#define E1000_TCTL_EXT   0x00404 /* Extended TX Control - RW */

Definition at line 64 of file e1000_regs.h.

#define E1000_TDBAH

(

_n

)

Value:

((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \
                    : (0x0E004 + ((_n) * 0x40)))

Definition at line 151 of file e1000_regs.h.

#define E1000_TDBAL

(

_n

)

Value:

((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \
                    : (0x0E000 + ((_n) * 0x40)))

Definition at line 149 of file e1000_regs.h.

#define E1000_TDFH   0x03410 /* TX Data FIFO Head - RW */

Definition at line 171 of file e1000_regs.h.

#define E1000_TDFHS   0x03420 /* TX Data FIFO Head Saved - RW */

Definition at line 173 of file e1000_regs.h.

#define E1000_TDFPC   0x03430 /* TX Data FIFO Packet Count - RW */

Definition at line 174 of file e1000_regs.h.

#define E1000_TDFT   0x03418 /* TX Data FIFO Tail - RW */

Definition at line 172 of file e1000_regs.h.

#define E1000_TDH

(

_n

)

Value:

((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \
                    : (0x0E010 + ((_n) * 0x40)))

Definition at line 155 of file e1000_regs.h.

#define E1000_TDLEN

(

_n

)

Value:

((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \
                    : (0x0E008 + ((_n) * 0x40)))

Definition at line 153 of file e1000_regs.h.

#define E1000_TDT

(

_n

)

Value:

((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \
                    : (0x0E018 + ((_n) * 0x40)))

Definition at line 157 of file e1000_regs.h.

#define E1000_TDWBAH

(

_n

)

Value:

((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \
                    : (0x0E03C + ((_n) * 0x40)))

Definition at line 169 of file e1000_regs.h.

#define E1000_TDWBAL

(

_n

)

Value:

((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
                    : (0x0E038 + ((_n) * 0x40)))

Definition at line 167 of file e1000_regs.h.

#define E1000_THSTAT   0x08110 /* Thermal Sensor Status */

Definition at line 354 of file e1000_regs.h.

#define E1000_TIMINCA   0x0B608 /* Increment attributes register - RW */

Definition at line 91 of file e1000_regs.h.

#define E1000_TIPG   0x00410 /* TX Inter-packet gap -RW */

Definition at line 65 of file e1000_regs.h.

#define E1000_TNCRS   0x04034 /* TX-No CRS - R/clr */

Definition at line 187 of file e1000_regs.h.

#define E1000_TORH   0x040C4 /* Total Octets RX High - R/clr */

Definition at line 219 of file e1000_regs.h.

#define E1000_TORL   0x040C0 /* Total Octets RX Low - R/clr */

Definition at line 218 of file e1000_regs.h.

#define E1000_TOTH   0x040CC /* Total Octets TX High - R/clr */

Definition at line 221 of file e1000_regs.h.

#define E1000_TOTL   0x040C8 /* Total Octets TX Low - R/clr */

Definition at line 220 of file e1000_regs.h.

#define E1000_TPR   0x040D0 /* Total Packets RX - R/clr */

Definition at line 222 of file e1000_regs.h.

#define E1000_TPT   0x040D4 /* Total Packets TX - R/clr */

Definition at line 223 of file e1000_regs.h.

#define E1000_TSAUXC   0x0B640 /* Timesync Auxiliary Control register */

Definition at line 92 of file e1000_regs.h.

#define E1000_TSCTC   0x040F8 /* TCP Segmentation Context TX - R/clr */

Definition at line 232 of file e1000_regs.h.

#define E1000_TSCTFC   0x040FC /* TCP Segmentation Context TX Fail - R/clr */

Definition at line 233 of file e1000_regs.h.

#define E1000_TSICR   0x0B66C /* Interrupt Cause Register */

Definition at line 94 of file e1000_regs.h.

#define E1000_TSIM   0x0B674 /* Interrupt Mask Register */

Definition at line 95 of file e1000_regs.h.

#define E1000_TSYNCRXCFG   0x05F50 /* Time Sync Rx Configuration - RW */

Definition at line 82 of file e1000_regs.h.

#define E1000_TSYNCRXCTL   0x0B620 /* Rx Time Sync Control register - RW */

Definition at line 80 of file e1000_regs.h.

#define E1000_TSYNCTXCTL   0x0B614 /* Tx Time Sync Control register - RW */

Definition at line 81 of file e1000_regs.h.

#define E1000_TXCTL

(

_n

)

Value:

((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
                      (0x0E014 + ((_n) * 0x40)))

Definition at line 164 of file e1000_regs.h.

#define E1000_TXCW   0x00178 /* TX Configuration Word - RW */

Definition at line 52 of file e1000_regs.h.

#define E1000_TXDCTL

(

_n

)

Value:

((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
                    : (0x0E028 + ((_n) * 0x40)))

Definition at line 159 of file e1000_regs.h.

#define E1000_TXSTMPH   0x0B61C /* Tx timestamp value High - RO */

Definition at line 88 of file e1000_regs.h.

#define E1000_TXSTMPL   0x0B618 /* Tx timestamp value Low - RO */

Definition at line 87 of file e1000_regs.h.

#define E1000_TXSWC   0x05ACC /* Tx Switch Control */

Definition at line 328 of file e1000_regs.h.

#define E1000_UTA   0x0A000 /* Unicast Table Array - RW */

Definition at line 326 of file e1000_regs.h.

#define E1000_VET   0x00038 /* VLAN Ether Type - RW */

Definition at line 43 of file e1000_regs.h.

#define E1000_VFLRE   0x00C88 /* VF Register Events - RWC */

Definition at line 319 of file e1000_regs.h.

#define E1000_VFRE   0x00C8C /* VF Receive Enables */

Definition at line 320 of file e1000_regs.h.

#define E1000_VFTA   0x05600 /* VLAN Filter Table Array - RW Array */

Definition at line 286 of file e1000_regs.h.

#define E1000_VFTE   0x00C90 /* VF Transmit Enables */

Definition at line 321 of file e1000_regs.h.

#define E1000_VLVF

(

_n

)

Value:

(0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
                                                       * Filter - RW */

Definition at line 333 of file e1000_regs.h.

#define E1000_VMBMEM

(

_n

)

(0x00800 + (64 * (_n)))

Definition at line 331 of file e1000_regs.h.

#define E1000_VMOLR

(

_n

)

(0x05AD0 + (4 * (_n)))

Definition at line 332 of file e1000_regs.h.

#define E1000_VMVIR

(

_n

)

(0x03700 + (4 * (_n)))

Definition at line 334 of file e1000_regs.h.

#define E1000_VT_CTL   0x0581C /* VMDq Control - RW */

Definition at line 287 of file e1000_regs.h.

#define E1000_WUC   0x05800 /* Wakeup Control - RW */

Definition at line 288 of file e1000_regs.h.

#define E1000_WUFC   0x05808 /* Wakeup Filter Control - RW */

Definition at line 289 of file e1000_regs.h.

#define E1000_WUPL   0x05900 /* Wakeup Packet Length - RW */

Definition at line 293 of file e1000_regs.h.

#define E1000_WUPM_REG

(

_i

)

(0x05A00 + ((_i) * 4))

Definition at line 282 of file e1000_regs.h.

#define E1000_WUS   0x05810 /* Wakeup Status - RO */

Definition at line 290 of file e1000_regs.h.

#define E1000_WVBR   0x03554 /* VM Wrong Behavior - RWS */

Definition at line 324 of file e1000_regs.h.

#define E1000_XOFFRXC   0x04050 /* XOFF RX Count - R/clr */

Definition at line 193 of file e1000_regs.h.

#define E1000_XOFFTXC   0x04054 /* XOFF TX Count - R/clr */

Definition at line 194 of file e1000_regs.h.

#define E1000_XONRXC   0x04048 /* XON RX Count - R/clr */

Definition at line 191 of file e1000_regs.h.

#define E1000_XONTXC   0x0404C /* XON TX Count - R/clr */

Definition at line 192 of file e1000_regs.h.

#define rd32

(

reg

)

(readl(hw->hw_addr + reg))

Definition at line 337 of file e1000_regs.h.

#define wr32	(		reg,
			value
	)		(writel(value, hw->hw_addr + reg))

Definition at line 336 of file e1000_regs.h.

#define wrfl

(

)

((void)rd32(E1000_STATUS))

Definition at line 338 of file e1000_regs.h.