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Data Structures | Macros | Enumerations
hw.h File Reference
#include <linux/types.h>
#include "defines.h"

Go to the source code of this file.

Data Structures

struct  e1000_rx_desc
 
union  e1000_rx_desc_extended
 
union  e1000_rx_desc_packet_split
 
struct  e1000_tx_desc
 
struct  e1000_context_desc
 
struct  e1000_data_desc
 
struct  e1000_hw_stats
 
struct  e1000_phy_stats
 
struct  e1000_host_mng_dhcp_cookie
 
struct  e1000_host_command_header
 
struct  e1000_host_command_info
 
struct  e1000_host_mng_command_header
 
struct  e1000_host_mng_command_info
 
struct  e1000_mac_operations
 
struct  e1000_phy_operations
 
struct  e1000_nvm_operations
 
struct  e1000_mac_info
 
struct  e1000_phy_info
 
struct  e1000_nvm_info
 
struct  e1000_bus_info
 
struct  e1000_fc_info
 
struct  e1000_dev_spec_82571
 
struct  e1000_dev_spec_80003es2lan
 
struct  e1000_shadow_ram
 
struct  e1000_dev_spec_ich8lan
 
struct  e1000_hw
 

Macros

#define E1000_EITR_82574(_n)   (E1000_EITR_82574_BASE + (_n << 2))
 
#define E1000_POEMB   E1000_PHY_CTRL /* PHY OEM Bits */
 
#define E1000_RDBAL(_n)   (E1000_RDBAL_BASE + (_n << 8))
 
#define E1000_RDBAH(_n)   (E1000_RDBAH_BASE + (_n << 8))
 
#define E1000_RDLEN(_n)   (E1000_RDLEN_BASE + (_n << 8))
 
#define E1000_RDH(_n)   (E1000_RDH_BASE + (_n << 8))
 
#define E1000_RDT(_n)   (E1000_RDT_BASE + (_n << 8))
 
#define E1000_RXDCTL(_n)   (E1000_RXDCTL_BASE + (_n << 8))
 
#define E1000_TDBAL(_n)   (E1000_TDBAL_BASE + (_n << 8))
 
#define E1000_TDBAH(_n)   (E1000_TDBAH_BASE + (_n << 8))
 
#define E1000_TDLEN(_n)   (E1000_TDLEN_BASE + (_n << 8))
 
#define E1000_TDH(_n)   (E1000_TDH_BASE + (_n << 8))
 
#define E1000_TDT(_n)   (E1000_TDT_BASE + (_n << 8))
 
#define E1000_TXDCTL(_n)   (E1000_TXDCTL_BASE + (_n << 8))
 
#define E1000_TARC(_n)   (E1000_TARC_BASE + (_n << 8))
 
#define E1000_RAL(_n)   (E1000_RAL_BASE + ((_n) * 8))
 
#define E1000_RA   (E1000_RAL(0))
 
#define E1000_RAH(_n)   (E1000_RAH_BASE + ((_n) * 8))
 
#define E1000_SHRAL_PCH_LPT(_n)   (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
 
#define E1000_SHRAH_PCH_LPT(_n)   (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
 
#define E1000_SHRAL(_n)   (E1000_SHRAL_BASE + ((_n) * 8))
 
#define E1000_SHRAH(_n)   (E1000_SHRAH_BASE + ((_n) * 8))
 
#define E1000_MDEF(_n)   (E1000_MDEF_BASE + ((_n) * 4))
 
#define E1000_RETA(_n)   (E1000_RETA_BASE + ((_n) * 4))
 
#define E1000_RSSRK(_n)   (E1000_RSSRK_BASE + ((_n) * 4))
 
#define E1000_PCH_RAICC(_n)   (E1000_PCH_RAICC_BASE + ((_n) * 4))
 
#define E1000_CRC_OFFSET   E1000_PCH_RAICC_BASE
 
#define E1000_MAX_PHY_ADDR   4
 
#define IGP01E1000_PHY_PORT_CONFIG   0x10 /* Port Config */
 
#define IGP01E1000_PHY_PORT_STATUS   0x11 /* Status */
 
#define IGP01E1000_PHY_PORT_CTRL   0x12 /* Control */
 
#define IGP01E1000_PHY_LINK_HEALTH   0x13 /* PHY Link Health */
 
#define IGP02E1000_PHY_POWER_MGMT   0x19 /* Power Management */
 
#define IGP01E1000_PHY_PAGE_SELECT   0x1F /* Page Select */
 
#define BM_PHY_PAGE_SELECT   22 /* Page Select for BM */
 
#define IGP_PAGE_SHIFT   5
 
#define PHY_REG_MASK   0x1F
 
#define BM_WUC_PAGE   800
 
#define BM_WUC_ADDRESS_OPCODE   0x11
 
#define BM_WUC_DATA_OPCODE   0x12
 
#define BM_WUC_ENABLE_PAGE   769
 
#define BM_WUC_ENABLE_REG   17
 
#define BM_WUC_ENABLE_BIT   (1 << 2)
 
#define BM_WUC_HOST_WU_BIT   (1 << 4)
 
#define BM_WUC_ME_WU_BIT   (1 << 5)
 
#define BM_WUC   PHY_REG(BM_WUC_PAGE, 1)
 
#define BM_WUFC   PHY_REG(BM_WUC_PAGE, 2)
 
#define BM_WUS   PHY_REG(BM_WUC_PAGE, 3)
 
#define IGP01E1000_PHY_PCS_INIT_REG   0x00B4
 
#define IGP01E1000_PHY_POLARITY_MASK   0x0078
 
#define IGP01E1000_PSCR_AUTO_MDIX   0x1000
 
#define IGP01E1000_PSCR_FORCE_MDI_MDIX   0x2000 /* 0=MDI, 1=MDIX */
 
#define IGP01E1000_PSCFR_SMART_SPEED   0x0080
 
#define IGP02E1000_PM_SPD   0x0001 /* Smart Power Down */
 
#define IGP02E1000_PM_D0_LPLU   0x0002 /* For D0a states */
 
#define IGP02E1000_PM_D3_LPLU   0x0004 /* For all other states */
 
#define IGP01E1000_PLHR_SS_DOWNGRADE   0x8000
 
#define IGP01E1000_PSSR_POLARITY_REVERSED   0x0002
 
#define IGP01E1000_PSSR_MDIX   0x0800
 
#define IGP01E1000_PSSR_SPEED_MASK   0xC000
 
#define IGP01E1000_PSSR_SPEED_1000MBPS   0xC000
 
#define IGP02E1000_PHY_CHANNEL_NUM   4
 
#define IGP02E1000_PHY_AGC_A   0x11B1
 
#define IGP02E1000_PHY_AGC_B   0x12B1
 
#define IGP02E1000_PHY_AGC_C   0x14B1
 
#define IGP02E1000_PHY_AGC_D   0x18B1
 
#define IGP02E1000_AGC_LENGTH_SHIFT   9 /* Course - 15:13, Fine - 12:9 */
 
#define IGP02E1000_AGC_LENGTH_MASK   0x7F
 
#define IGP02E1000_AGC_RANGE   15
 
#define E1000_VFTA_ENTRY_SHIFT   5
 
#define E1000_VFTA_ENTRY_MASK   0x7F
 
#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK   0x1F
 
#define E1000_HICR_EN   0x01 /* Enable bit - RO */
 
#define E1000_HICR_C   0x02
 
#define E1000_HICR_FW_RESET_ENABLE   0x40
 
#define E1000_HICR_FW_RESET   0x80
 
#define E1000_FWSM_MODE_MASK   0xE
 
#define E1000_FWSM_MODE_SHIFT   1
 
#define E1000_MNG_IAMT_MODE   0x3
 
#define E1000_MNG_DHCP_COOKIE_LENGTH   0x10
 
#define E1000_MNG_DHCP_COOKIE_OFFSET   0x6F0
 
#define E1000_MNG_DHCP_COMMAND_TIMEOUT   10
 
#define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64
 
#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING   0x1
 
#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN   0x2
 
#define E1000_STM_OPCODE   0xDB00
 
#define E1000_KMRNCTRLSTA_OFFSET   0x001F0000
 
#define E1000_KMRNCTRLSTA_OFFSET_SHIFT   16
 
#define E1000_KMRNCTRLSTA_REN   0x00200000
 
#define E1000_KMRNCTRLSTA_CTRL_OFFSET   0x1 /* Kumeran Control */
 
#define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3 /* Kumeran Diagnostic */
 
#define E1000_KMRNCTRLSTA_TIMEOUTS   0x4 /* Kumeran Timeouts */
 
#define E1000_KMRNCTRLSTA_INBAND_PARAM   0x9 /* Kumeran InBand Parameters */
 
#define E1000_KMRNCTRLSTA_IBIST_DISABLE   0x0200 /* Kumeran IBIST Disable */
 
#define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000 /* Nearend Loopback mode */
 
#define E1000_KMRNCTRLSTA_K1_CONFIG   0x7
 
#define E1000_KMRNCTRLSTA_K1_ENABLE   0x0002
 
#define E1000_KMRNCTRLSTA_HD_CTRL   0x10 /* Kumeran HD Control */
 
#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10
 
#define IFE_PHY_SPECIAL_CONTROL   0x11 /* 100BaseTx PHY Special Control */
 
#define IFE_PHY_SPECIAL_CONTROL_LED   0x1B /* PHY Special and LED Control */
 
#define IFE_PHY_MDIX_CONTROL   0x1C /* MDI/MDI-X Control */
 
#define IFE_PESC_POLARITY_REVERSED   0x0100
 
#define IFE_PSC_AUTO_POLARITY_DISABLE   0x0010
 
#define IFE_PSC_FORCE_POLARITY   0x0020
 
#define IFE_PSCL_PROBE_MODE   0x0020
 
#define IFE_PSCL_PROBE_LEDS_OFF   0x0006 /* Force LEDs 0 and 2 off */
 
#define IFE_PSCL_PROBE_LEDS_ON   0x0007 /* Force LEDs 0 and 2 on */
 
#define IFE_PMC_MDIX_STATUS   0x0020 /* 1=MDI-X, 0=MDI */
 
#define IFE_PMC_FORCE_MDIX   0x0040 /* 1=force MDI-X, 0=force MDI */
 
#define IFE_PMC_AUTO_MDIX   0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
 
#define E1000_CABLE_LENGTH_UNDEFINED   0xFF
 
#define E1000_DEV_ID_82571EB_COPPER   0x105E
 
#define E1000_DEV_ID_82571EB_FIBER   0x105F
 
#define E1000_DEV_ID_82571EB_SERDES   0x1060
 
#define E1000_DEV_ID_82571EB_QUAD_COPPER   0x10A4
 
#define E1000_DEV_ID_82571PT_QUAD_COPPER   0x10D5
 
#define E1000_DEV_ID_82571EB_QUAD_FIBER   0x10A5
 
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
 
#define E1000_DEV_ID_82571EB_SERDES_DUAL   0x10D9
 
#define E1000_DEV_ID_82571EB_SERDES_QUAD   0x10DA
 
#define E1000_DEV_ID_82572EI_COPPER   0x107D
 
#define E1000_DEV_ID_82572EI_FIBER   0x107E
 
#define E1000_DEV_ID_82572EI_SERDES   0x107F
 
#define E1000_DEV_ID_82572EI   0x10B9
 
#define E1000_DEV_ID_82573E   0x108B
 
#define E1000_DEV_ID_82573E_IAMT   0x108C
 
#define E1000_DEV_ID_82573L   0x109A
 
#define E1000_DEV_ID_82574L   0x10D3
 
#define E1000_DEV_ID_82574LA   0x10F6
 
#define E1000_DEV_ID_82583V   0x150C
 
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
 
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
 
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
 
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
 
#define E1000_DEV_ID_ICH8_82567V_3   0x1501
 
#define E1000_DEV_ID_ICH8_IGP_M_AMT   0x1049
 
#define E1000_DEV_ID_ICH8_IGP_AMT   0x104A
 
#define E1000_DEV_ID_ICH8_IGP_C   0x104B
 
#define E1000_DEV_ID_ICH8_IFE   0x104C
 
#define E1000_DEV_ID_ICH8_IFE_GT   0x10C4
 
#define E1000_DEV_ID_ICH8_IFE_G   0x10C5
 
#define E1000_DEV_ID_ICH8_IGP_M   0x104D
 
#define E1000_DEV_ID_ICH9_IGP_AMT   0x10BD
 
#define E1000_DEV_ID_ICH9_BM   0x10E5
 
#define E1000_DEV_ID_ICH9_IGP_M_AMT   0x10F5
 
#define E1000_DEV_ID_ICH9_IGP_M   0x10BF
 
#define E1000_DEV_ID_ICH9_IGP_M_V   0x10CB
 
#define E1000_DEV_ID_ICH9_IGP_C   0x294C
 
#define E1000_DEV_ID_ICH9_IFE   0x10C0
 
#define E1000_DEV_ID_ICH9_IFE_GT   0x10C3
 
#define E1000_DEV_ID_ICH9_IFE_G   0x10C2
 
#define E1000_DEV_ID_ICH10_R_BM_LM   0x10CC
 
#define E1000_DEV_ID_ICH10_R_BM_LF   0x10CD
 
#define E1000_DEV_ID_ICH10_R_BM_V   0x10CE
 
#define E1000_DEV_ID_ICH10_D_BM_LM   0x10DE
 
#define E1000_DEV_ID_ICH10_D_BM_LF   0x10DF
 
#define E1000_DEV_ID_ICH10_D_BM_V   0x1525
 
#define E1000_DEV_ID_PCH_M_HV_LM   0x10EA
 
#define E1000_DEV_ID_PCH_M_HV_LC   0x10EB
 
#define E1000_DEV_ID_PCH_D_HV_DM   0x10EF
 
#define E1000_DEV_ID_PCH_D_HV_DC   0x10F0
 
#define E1000_DEV_ID_PCH2_LV_LM   0x1502
 
#define E1000_DEV_ID_PCH2_LV_V   0x1503
 
#define E1000_DEV_ID_PCH_LPT_I217_LM   0x153A
 
#define E1000_DEV_ID_PCH_LPT_I217_V   0x153B
 
#define E1000_DEV_ID_PCH_LPTLP_I218_LM   0x155A
 
#define E1000_DEV_ID_PCH_LPTLP_I218_V   0x1559
 
#define E1000_REVISION_4   4
 
#define E1000_FUNC_1   1
 
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
 
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
 
#define MAX_PS_BUFFERS   4
 
#define E1000_HI_MAX_DATA_LENGTH   252
 
#define E1000_HI_MAX_MNG_DATA_LENGTH   0x6F8
 
#define MAX_MTA_REG   128
 
#define E1000_ICH8_SHADOW_RAM_WORDS   2048
 

Enumerations

enum  e1e_registers {
  E1000_CTRL = 0x00000, E1000_STATUS = 0x00008, E1000_EECD = 0x00010, E1000_EERD = 0x00014,
  E1000_CTRL_EXT = 0x00018, E1000_FLA = 0x0001C, E1000_MDIC = 0x00020, E1000_SCTL = 0x00024,
  E1000_FCAL = 0x00028, E1000_FCAH = 0x0002C, E1000_FEXTNVM4 = 0x00024, E1000_FEXTNVM = 0x00028,
  E1000_FCT = 0x00030, E1000_VET = 0x00038, E1000_FEXTNVM3 = 0x0003C, E1000_ICR = 0x000C0,
  E1000_ITR = 0x000C4, E1000_ICS = 0x000C8, E1000_IMS = 0x000D0, E1000_IMC = 0x000D8,
  E1000_EIAC_82574 = 0x000DC, E1000_IAM = 0x000E0, E1000_IVAR = 0x000E4, E1000_EITR_82574_BASE = 0x000E8,
  E1000_RCTL = 0x00100, E1000_FCTTV = 0x00170, E1000_TXCW = 0x00178, E1000_RXCW = 0x00180,
  E1000_TCTL = 0x00400, E1000_TCTL_EXT = 0x00404, E1000_TIPG = 0x00410, E1000_AIT = 0x00458,
  E1000_LEDCTL = 0x00E00, E1000_EXTCNF_CTRL = 0x00F00, E1000_EXTCNF_SIZE = 0x00F08, E1000_PHY_CTRL = 0x00F10,
  E1000_PBA = 0x01000, E1000_PBS = 0x01008, E1000_EEMNGCTL = 0x01010, E1000_EEWR = 0x0102C,
  E1000_FLOP = 0x0103C, E1000_PBA_ECC = 0x01100, E1000_ERT = 0x02008, E1000_FCRTL = 0x02160,
  E1000_FCRTH = 0x02168, E1000_PSRCTL = 0x02170, E1000_RDBAL_BASE = 0x02800, E1000_RDBAH_BASE = 0x02804,
  E1000_RDLEN_BASE = 0x02808, E1000_RDH_BASE = 0x02810, E1000_RDT_BASE = 0x02818, E1000_RDTR = 0x02820,
  E1000_RXDCTL_BASE = 0x02828, E1000_RADV = 0x0282C, E1000_KABGTXD = 0x03004, E1000_TDBAL_BASE = 0x03800,
  E1000_TDBAH_BASE = 0x03804, E1000_TDLEN_BASE = 0x03808, E1000_TDH_BASE = 0x03810, E1000_TDT_BASE = 0x03818,
  E1000_TIDV = 0x03820, E1000_TXDCTL_BASE = 0x03828, E1000_TADV = 0x0382C, E1000_TARC_BASE = 0x03840,
  E1000_CRCERRS = 0x04000, E1000_ALGNERRC = 0x04004, E1000_SYMERRS = 0x04008, E1000_RXERRC = 0x0400C,
  E1000_MPC = 0x04010, E1000_SCC = 0x04014, E1000_ECOL = 0x04018, E1000_MCC = 0x0401C,
  E1000_LATECOL = 0x04020, E1000_COLC = 0x04028, E1000_DC = 0x04030, E1000_TNCRS = 0x04034,
  E1000_SEC = 0x04038, E1000_CEXTERR = 0x0403C, E1000_RLEC = 0x04040, E1000_XONRXC = 0x04048,
  E1000_XONTXC = 0x0404C, E1000_XOFFRXC = 0x04050, E1000_XOFFTXC = 0x04054, E1000_FCRUC = 0x04058,
  E1000_PRC64 = 0x0405C, E1000_PRC127 = 0x04060, E1000_PRC255 = 0x04064, E1000_PRC511 = 0x04068,
  E1000_PRC1023 = 0x0406C, E1000_PRC1522 = 0x04070, E1000_GPRC = 0x04074, E1000_BPRC = 0x04078,
  E1000_MPRC = 0x0407C, E1000_GPTC = 0x04080, E1000_GORCL = 0x04088, E1000_GORCH = 0x0408C,
  E1000_GOTCL = 0x04090, E1000_GOTCH = 0x04094, E1000_RNBC = 0x040A0, E1000_RUC = 0x040A4,
  E1000_RFC = 0x040A8, E1000_ROC = 0x040AC, E1000_RJC = 0x040B0, E1000_MGTPRC = 0x040B4,
  E1000_MGTPDC = 0x040B8, E1000_MGTPTC = 0x040BC, E1000_TORL = 0x040C0, E1000_TORH = 0x040C4,
  E1000_TOTL = 0x040C8, E1000_TOTH = 0x040CC, E1000_TPR = 0x040D0, E1000_TPT = 0x040D4,
  E1000_PTC64 = 0x040D8, E1000_PTC127 = 0x040DC, E1000_PTC255 = 0x040E0, E1000_PTC511 = 0x040E4,
  E1000_PTC1023 = 0x040E8, E1000_PTC1522 = 0x040EC, E1000_MPTC = 0x040F0, E1000_BPTC = 0x040F4,
  E1000_TSCTC = 0x040F8, E1000_TSCTFC = 0x040FC, E1000_IAC = 0x04100, E1000_ICRXPTC = 0x04104,
  E1000_ICRXATC = 0x04108, E1000_ICTXPTC = 0x0410C, E1000_ICTXATC = 0x04110, E1000_ICTXQEC = 0x04118,
  E1000_ICTXQMTC = 0x0411C, E1000_ICRXDMTC = 0x04120, E1000_ICRXOC = 0x04124, E1000_RXCSUM = 0x05000,
  E1000_RFCTL = 0x05008, E1000_MTA = 0x05200, E1000_RAL_BASE = 0x05400, E1000_RAH_BASE = 0x05404,
  E1000_SHRAL_PCH_LPT_BASE = 0x05408, E1000_SHRAH_PCH_LTP_BASE = 0x0540C, E1000_SHRAL_BASE = 0x05438, E1000_SHRAH_BASE = 0x0543C,
  E1000_VFTA = 0x05600, E1000_WUC = 0x05800, E1000_WUFC = 0x05808, E1000_WUS = 0x05810,
  E1000_MRQC = 0x05818, E1000_MANC = 0x05820, E1000_FFLT = 0x05F00, E1000_HOST_IF = 0x08800,
  E1000_KMRNCTRLSTA = 0x00034, E1000_MANC2H = 0x05860, E1000_MDEF_BASE = 0x05890, E1000_SW_FW_SYNC = 0x05B5C,
  E1000_GCR = 0x05B00, E1000_GCR2 = 0x05B64, E1000_FACTPS = 0x05B30, E1000_SWSM = 0x05B50,
  E1000_FWSM = 0x05B54, E1000_SWSM2 = 0x05B58, E1000_RETA_BASE = 0x05C00, E1000_RSSRK_BASE = 0x05C80,
  E1000_FFLT_DBG = 0x05F04, E1000_PCH_RAICC_BASE = 0x05F50, E1000_HICR = 0x08F00
}
 
enum  e1000_mac_type {
  e1000_undefined = 0, e1000_82542_rev2_0, e1000_82542_rev2_1, e1000_82543,
  e1000_82544, e1000_82540, e1000_82545, e1000_82545_rev_3,
  e1000_82546, e1000_ce4100, e1000_82546_rev_3, e1000_82541,
  e1000_82541_rev_2, e1000_82547, e1000_82547_rev_2, e1000_num_macs,
  e1000_82571, e1000_82572, e1000_82573, e1000_82574,
  e1000_82583, e1000_80003es2lan, e1000_ich8lan, e1000_ich9lan,
  e1000_ich10lan, e1000_pchlan, e1000_pch2lan, e1000_pch_lpt,
  e1000_undefined = 0, e1000_82575, e1000_82576, e1000_82580,
  e1000_i350, e1000_i210, e1000_i211, e1000_num_macs,
  e1000_undefined = 0, e1000_vfadapt, e1000_vfadapt_i350, e1000_num_macs
}
 
enum  e1000_media_type {
  e1000_media_type_copper = 0, e1000_media_type_fiber = 1, e1000_media_type_internal_serdes = 2, e1000_num_media_types,
  e1000_media_type_unknown = 0, e1000_media_type_copper = 1, e1000_media_type_fiber = 2, e1000_media_type_internal_serdes = 3,
  e1000_num_media_types, e1000_media_type_unknown = 0, e1000_media_type_copper = 1, e1000_media_type_internal_serdes = 2,
  e1000_num_media_types
}
 
enum  e1000_nvm_type {
  e1000_nvm_unknown = 0, e1000_nvm_none, e1000_nvm_eeprom_spi, e1000_nvm_flash_hw,
  e1000_nvm_flash_sw, e1000_nvm_unknown = 0, e1000_nvm_none, e1000_nvm_eeprom_spi,
  e1000_nvm_flash_hw, e1000_nvm_flash_sw
}
 
enum  e1000_nvm_override {
  e1000_nvm_override_none = 0, e1000_nvm_override_spi_small, e1000_nvm_override_spi_large, e1000_nvm_override_none = 0,
  e1000_nvm_override_spi_small, e1000_nvm_override_spi_large
}
 
enum  e1000_phy_type {
  e1000_phy_m88 = 0, e1000_phy_igp, e1000_phy_8211, e1000_phy_8201,
  e1000_phy_undefined = 0xFF, e1000_phy_unknown = 0, e1000_phy_none, e1000_phy_m88,
  e1000_phy_igp, e1000_phy_igp_2, e1000_phy_gg82563, e1000_phy_igp_3,
  e1000_phy_ife, e1000_phy_bm, e1000_phy_82578, e1000_phy_82577,
  e1000_phy_82579, e1000_phy_i217, e1000_phy_unknown = 0, e1000_phy_none,
  e1000_phy_m88, e1000_phy_igp, e1000_phy_igp_2, e1000_phy_gg82563,
  e1000_phy_igp_3, e1000_phy_ife, e1000_phy_82580, e1000_phy_i210
}
 
enum  e1000_bus_width {
  e1000_bus_width_unknown = 0, e1000_bus_width_32, e1000_bus_width_64, e1000_bus_width_reserved,
  e1000_bus_width_unknown = 0, e1000_bus_width_pcie_x1, e1000_bus_width_pcie_x2, e1000_bus_width_pcie_x4 = 4,
  e1000_bus_width_32, e1000_bus_width_64, e1000_bus_width_reserved, e1000_bus_width_unknown = 0,
  e1000_bus_width_pcie_x1, e1000_bus_width_pcie_x2, e1000_bus_width_pcie_x4 = 4, e1000_bus_width_pcie_x8 = 8,
  e1000_bus_width_32, e1000_bus_width_64, e1000_bus_width_reserved
}
 
enum  e1000_1000t_rx_status {
  e1000_1000t_rx_status_not_ok = 0, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined = 0xFF, e1000_1000t_rx_status_not_ok = 0,
  e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined = 0xFF, e1000_1000t_rx_status_not_ok = 0, e1000_1000t_rx_status_ok,
  e1000_1000t_rx_status_undefined = 0xFF
}
 
enum  e1000_rev_polarity {
  e1000_rev_polarity_normal = 0, e1000_rev_polarity_reversed, e1000_rev_polarity_undefined = 0xFF, e1000_rev_polarity_normal = 0,
  e1000_rev_polarity_reversed, e1000_rev_polarity_undefined = 0xFF, e1000_rev_polarity_normal = 0, e1000_rev_polarity_reversed,
  e1000_rev_polarity_undefined = 0xFF
}
 
enum  e1000_fc_mode {
  e1000_fc_none = 0, e1000_fc_rx_pause, e1000_fc_tx_pause, e1000_fc_full,
  e1000_fc_default = 0xFF, e1000_fc_none = 0, e1000_fc_rx_pause, e1000_fc_tx_pause,
  e1000_fc_full, e1000_fc_default = 0xFF
}
 
enum  e1000_ms_type {
  e1000_ms_hw_default = 0, e1000_ms_force_master, e1000_ms_force_slave, e1000_ms_auto,
  e1000_ms_hw_default = 0, e1000_ms_force_master, e1000_ms_force_slave, e1000_ms_auto,
  e1000_ms_hw_default = 0, e1000_ms_force_master, e1000_ms_force_slave, e1000_ms_auto
}
 
enum  e1000_smart_speed {
  e1000_smart_speed_default = 0, e1000_smart_speed_on, e1000_smart_speed_off, e1000_smart_speed_default = 0,
  e1000_smart_speed_on, e1000_smart_speed_off, e1000_smart_speed_default = 0, e1000_smart_speed_on,
  e1000_smart_speed_off
}
 
enum  e1000_serdes_link_state { e1000_serdes_link_down = 0, e1000_serdes_link_autoneg_progress, e1000_serdes_link_autoneg_complete, e1000_serdes_link_forced_up }
 

Macro Definition Documentation

#define BM_PHY_PAGE_SELECT   22 /* Page Select for BM */

Definition at line 251 of file hw.h.

#define BM_WUC   PHY_REG(BM_WUC_PAGE, 1)

Definition at line 264 of file hw.h.

#define BM_WUC_ADDRESS_OPCODE   0x11

Definition at line 256 of file hw.h.

#define BM_WUC_DATA_OPCODE   0x12

Definition at line 257 of file hw.h.

#define BM_WUC_ENABLE_BIT   (1 << 2)

Definition at line 260 of file hw.h.

#define BM_WUC_ENABLE_PAGE   769

Definition at line 258 of file hw.h.

#define BM_WUC_ENABLE_REG   17

Definition at line 259 of file hw.h.

#define BM_WUC_HOST_WU_BIT   (1 << 4)

Definition at line 261 of file hw.h.

#define BM_WUC_ME_WU_BIT   (1 << 5)

Definition at line 262 of file hw.h.

#define BM_WUC_PAGE   800

Definition at line 255 of file hw.h.

#define BM_WUFC   PHY_REG(BM_WUC_PAGE, 2)

Definition at line 265 of file hw.h.

#define BM_WUS   PHY_REG(BM_WUC_PAGE, 3)

Definition at line 266 of file hw.h.

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0

Definition at line 422 of file hw.h.

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3

Definition at line 423 of file hw.h.

#define E1000_CABLE_LENGTH_UNDEFINED   0xFF

Definition at line 357 of file hw.h.

#define E1000_CRC_OFFSET   E1000_PCH_RAICC_BASE

Definition at line 238 of file hw.h.

#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096

Definition at line 379 of file hw.h.

#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA

Definition at line 381 of file hw.h.

#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098

Definition at line 380 of file hw.h.

#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB

Definition at line 382 of file hw.h.

#define E1000_DEV_ID_82571EB_COPPER   0x105E

Definition at line 359 of file hw.h.

#define E1000_DEV_ID_82571EB_FIBER   0x105F

Definition at line 360 of file hw.h.

#define E1000_DEV_ID_82571EB_QUAD_COPPER   0x10A4

Definition at line 362 of file hw.h.

#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC

Definition at line 365 of file hw.h.

#define E1000_DEV_ID_82571EB_QUAD_FIBER   0x10A5

Definition at line 364 of file hw.h.

#define E1000_DEV_ID_82571EB_SERDES   0x1060

Definition at line 361 of file hw.h.

#define E1000_DEV_ID_82571EB_SERDES_DUAL   0x10D9

Definition at line 366 of file hw.h.

#define E1000_DEV_ID_82571EB_SERDES_QUAD   0x10DA

Definition at line 367 of file hw.h.

#define E1000_DEV_ID_82571PT_QUAD_COPPER   0x10D5

Definition at line 363 of file hw.h.

#define E1000_DEV_ID_82572EI   0x10B9

Definition at line 371 of file hw.h.

#define E1000_DEV_ID_82572EI_COPPER   0x107D

Definition at line 368 of file hw.h.

#define E1000_DEV_ID_82572EI_FIBER   0x107E

Definition at line 369 of file hw.h.

#define E1000_DEV_ID_82572EI_SERDES   0x107F

Definition at line 370 of file hw.h.

#define E1000_DEV_ID_82573E   0x108B

Definition at line 372 of file hw.h.

#define E1000_DEV_ID_82573E_IAMT   0x108C

Definition at line 373 of file hw.h.

#define E1000_DEV_ID_82573L   0x109A

Definition at line 374 of file hw.h.

#define E1000_DEV_ID_82574L   0x10D3

Definition at line 375 of file hw.h.

#define E1000_DEV_ID_82574LA   0x10F6

Definition at line 376 of file hw.h.

#define E1000_DEV_ID_82583V   0x150C

Definition at line 377 of file hw.h.

#define E1000_DEV_ID_ICH10_D_BM_LF   0x10DF

Definition at line 405 of file hw.h.

#define E1000_DEV_ID_ICH10_D_BM_LM   0x10DE

Definition at line 404 of file hw.h.

#define E1000_DEV_ID_ICH10_D_BM_V   0x1525

Definition at line 406 of file hw.h.

#define E1000_DEV_ID_ICH10_R_BM_LF   0x10CD

Definition at line 402 of file hw.h.

#define E1000_DEV_ID_ICH10_R_BM_LM   0x10CC

Definition at line 401 of file hw.h.

#define E1000_DEV_ID_ICH10_R_BM_V   0x10CE

Definition at line 403 of file hw.h.

#define E1000_DEV_ID_ICH8_82567V_3   0x1501

Definition at line 384 of file hw.h.

#define E1000_DEV_ID_ICH8_IFE   0x104C

Definition at line 388 of file hw.h.

#define E1000_DEV_ID_ICH8_IFE_G   0x10C5

Definition at line 390 of file hw.h.

#define E1000_DEV_ID_ICH8_IFE_GT   0x10C4

Definition at line 389 of file hw.h.

#define E1000_DEV_ID_ICH8_IGP_AMT   0x104A

Definition at line 386 of file hw.h.

#define E1000_DEV_ID_ICH8_IGP_C   0x104B

Definition at line 387 of file hw.h.

#define E1000_DEV_ID_ICH8_IGP_M   0x104D

Definition at line 391 of file hw.h.

#define E1000_DEV_ID_ICH8_IGP_M_AMT   0x1049

Definition at line 385 of file hw.h.

#define E1000_DEV_ID_ICH9_BM   0x10E5

Definition at line 393 of file hw.h.

#define E1000_DEV_ID_ICH9_IFE   0x10C0

Definition at line 398 of file hw.h.

#define E1000_DEV_ID_ICH9_IFE_G   0x10C2

Definition at line 400 of file hw.h.

#define E1000_DEV_ID_ICH9_IFE_GT   0x10C3

Definition at line 399 of file hw.h.

#define E1000_DEV_ID_ICH9_IGP_AMT   0x10BD

Definition at line 392 of file hw.h.

#define E1000_DEV_ID_ICH9_IGP_C   0x294C

Definition at line 397 of file hw.h.

#define E1000_DEV_ID_ICH9_IGP_M   0x10BF

Definition at line 395 of file hw.h.

#define E1000_DEV_ID_ICH9_IGP_M_AMT   0x10F5

Definition at line 394 of file hw.h.

#define E1000_DEV_ID_ICH9_IGP_M_V   0x10CB

Definition at line 396 of file hw.h.

#define E1000_DEV_ID_PCH2_LV_LM   0x1502

Definition at line 411 of file hw.h.

#define E1000_DEV_ID_PCH2_LV_V   0x1503

Definition at line 412 of file hw.h.

#define E1000_DEV_ID_PCH_D_HV_DC   0x10F0

Definition at line 410 of file hw.h.

#define E1000_DEV_ID_PCH_D_HV_DM   0x10EF

Definition at line 409 of file hw.h.

#define E1000_DEV_ID_PCH_LPT_I217_LM   0x153A

Definition at line 413 of file hw.h.

#define E1000_DEV_ID_PCH_LPT_I217_V   0x153B

Definition at line 414 of file hw.h.

#define E1000_DEV_ID_PCH_LPTLP_I218_LM   0x155A

Definition at line 415 of file hw.h.

#define E1000_DEV_ID_PCH_LPTLP_I218_V   0x1559

Definition at line 416 of file hw.h.

#define E1000_DEV_ID_PCH_M_HV_LC   0x10EB

Definition at line 408 of file hw.h.

#define E1000_DEV_ID_PCH_M_HV_LM   0x10EA

Definition at line 407 of file hw.h.

#define E1000_EITR_82574 (   _n)    (E1000_EITR_82574_BASE + (_n << 2))

Definition at line 64 of file hw.h.

#define E1000_FUNC_1   1

Definition at line 420 of file hw.h.

#define E1000_FWSM_MODE_MASK   0xE

Definition at line 308 of file hw.h.

#define E1000_FWSM_MODE_SHIFT   1

Definition at line 309 of file hw.h.

#define E1000_HI_MAX_DATA_LENGTH   252

Definition at line 756 of file hw.h.

#define E1000_HI_MAX_MNG_DATA_LENGTH   0x6F8

Definition at line 771 of file hw.h.

#define E1000_HICR_C   0x02

Definition at line 304 of file hw.h.

#define E1000_HICR_EN   0x01 /* Enable bit - RO */

Definition at line 302 of file hw.h.

#define E1000_HICR_FW_RESET   0x80

Definition at line 306 of file hw.h.

#define E1000_HICR_FW_RESET_ENABLE   0x40

Definition at line 305 of file hw.h.

#define E1000_ICH8_SHADOW_RAM_WORDS   2048

Definition at line 977 of file hw.h.

#define E1000_KMRNCTRLSTA_CTRL_OFFSET   0x1 /* Kumeran Control */

Definition at line 325 of file hw.h.

#define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000 /* Nearend Loopback mode */

Definition at line 330 of file hw.h.

#define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3 /* Kumeran Diagnostic */

Definition at line 326 of file hw.h.

#define E1000_KMRNCTRLSTA_HD_CTRL   0x10 /* Kumeran HD Control */

Definition at line 333 of file hw.h.

#define E1000_KMRNCTRLSTA_IBIST_DISABLE   0x0200 /* Kumeran IBIST Disable */

Definition at line 329 of file hw.h.

#define E1000_KMRNCTRLSTA_INBAND_PARAM   0x9 /* Kumeran InBand Parameters */

Definition at line 328 of file hw.h.

#define E1000_KMRNCTRLSTA_K1_CONFIG   0x7

Definition at line 331 of file hw.h.

#define E1000_KMRNCTRLSTA_K1_ENABLE   0x0002

Definition at line 332 of file hw.h.

#define E1000_KMRNCTRLSTA_OFFSET   0x001F0000

Definition at line 322 of file hw.h.

#define E1000_KMRNCTRLSTA_OFFSET_SHIFT   16

Definition at line 323 of file hw.h.

#define E1000_KMRNCTRLSTA_REN   0x00200000

Definition at line 324 of file hw.h.

#define E1000_KMRNCTRLSTA_TIMEOUTS   0x4 /* Kumeran Timeouts */

Definition at line 327 of file hw.h.

#define E1000_MAX_PHY_ADDR   4

Definition at line 242 of file hw.h.

#define E1000_MDEF (   _n)    (E1000_MDEF_BASE + ((_n) * 4))

Definition at line 223 of file hw.h.

#define E1000_MNG_DHCP_COMMAND_TIMEOUT   10

Definition at line 314 of file hw.h.

#define E1000_MNG_DHCP_COOKIE_LENGTH   0x10

Definition at line 312 of file hw.h.

#define E1000_MNG_DHCP_COOKIE_OFFSET   0x6F0

Definition at line 313 of file hw.h.

#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING   0x1

Definition at line 316 of file hw.h.

#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN   0x2

Definition at line 317 of file hw.h.

#define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64

Definition at line 315 of file hw.h.

#define E1000_MNG_IAMT_MODE   0x3

Definition at line 311 of file hw.h.

#define E1000_PCH_RAICC (   _n)    (E1000_PCH_RAICC_BASE + ((_n) * 4))

Definition at line 237 of file hw.h.

#define E1000_POEMB   E1000_PHY_CTRL /* PHY OEM Bits */

Definition at line 77 of file hw.h.

#define E1000_RA   (E1000_RAL(0))

Definition at line 200 of file hw.h.

#define E1000_RAH (   _n)    (E1000_RAH_BASE + ((_n) * 8))

Definition at line 202 of file hw.h.

#define E1000_RAL (   _n)    (E1000_RAL_BASE + ((_n) * 8))

Definition at line 199 of file hw.h.

#define E1000_RDBAH (   _n)    (E1000_RDBAH_BASE + (_n << 8))

Definition at line 99 of file hw.h.

#define E1000_RDBAL (   _n)    (E1000_RDBAL_BASE + (_n << 8))

Definition at line 97 of file hw.h.

#define E1000_RDH (   _n)    (E1000_RDH_BASE + (_n << 8))

Definition at line 103 of file hw.h.

#define E1000_RDLEN (   _n)    (E1000_RDLEN_BASE + (_n << 8))

Definition at line 101 of file hw.h.

#define E1000_RDT (   _n)    (E1000_RDT_BASE + (_n << 8))

Definition at line 105 of file hw.h.

#define E1000_RETA (   _n)    (E1000_RETA_BASE + ((_n) * 4))

Definition at line 232 of file hw.h.

#define E1000_REVISION_4   4

Definition at line 418 of file hw.h.

#define E1000_RSSRK (   _n)    (E1000_RSSRK_BASE + ((_n) * 4))

Definition at line 234 of file hw.h.

#define E1000_RXDCTL (   _n)    (E1000_RXDCTL_BASE + (_n << 8))

Definition at line 108 of file hw.h.

#define E1000_SHRAH (   _n)    (E1000_SHRAH_BASE + ((_n) * 8))

Definition at line 210 of file hw.h.

#define E1000_SHRAH_PCH_LPT (   _n)    (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))

Definition at line 206 of file hw.h.

#define E1000_SHRAL (   _n)    (E1000_SHRAL_BASE + ((_n) * 8))

Definition at line 208 of file hw.h.

#define E1000_SHRAL_PCH_LPT (   _n)    (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))

Definition at line 204 of file hw.h.

#define E1000_STM_OPCODE   0xDB00

Definition at line 320 of file hw.h.

#define E1000_TARC (   _n)    (E1000_TARC_BASE + (_n << 8))

Definition at line 127 of file hw.h.

#define E1000_TDBAH (   _n)    (E1000_TDBAH_BASE + (_n << 8))

Definition at line 115 of file hw.h.

#define E1000_TDBAL (   _n)    (E1000_TDBAL_BASE + (_n << 8))

Definition at line 113 of file hw.h.

#define E1000_TDH (   _n)    (E1000_TDH_BASE + (_n << 8))

Definition at line 119 of file hw.h.

#define E1000_TDLEN (   _n)    (E1000_TDLEN_BASE + (_n << 8))

Definition at line 117 of file hw.h.

#define E1000_TDT (   _n)    (E1000_TDT_BASE + (_n << 8))

Definition at line 121 of file hw.h.

#define E1000_TXDCTL (   _n)    (E1000_TXDCTL_BASE + (_n << 8))

Definition at line 124 of file hw.h.

#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK   0x1F

Definition at line 300 of file hw.h.

#define E1000_VFTA_ENTRY_MASK   0x7F

Definition at line 299 of file hw.h.

#define E1000_VFTA_ENTRY_SHIFT   5

Definition at line 298 of file hw.h.

#define IFE_PESC_POLARITY_REVERSED   0x0100

Definition at line 341 of file hw.h.

#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10

Definition at line 335 of file hw.h.

#define IFE_PHY_MDIX_CONTROL   0x1C /* MDI/MDI-X Control */

Definition at line 338 of file hw.h.

#define IFE_PHY_SPECIAL_CONTROL   0x11 /* 100BaseTx PHY Special Control */

Definition at line 336 of file hw.h.

#define IFE_PHY_SPECIAL_CONTROL_LED   0x1B /* PHY Special and LED Control */

Definition at line 337 of file hw.h.

#define IFE_PMC_AUTO_MDIX   0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */

Definition at line 355 of file hw.h.

#define IFE_PMC_FORCE_MDIX   0x0040 /* 1=force MDI-X, 0=force MDI */

Definition at line 354 of file hw.h.

#define IFE_PMC_MDIX_STATUS   0x0020 /* 1=MDI-X, 0=MDI */

Definition at line 353 of file hw.h.

#define IFE_PSC_AUTO_POLARITY_DISABLE   0x0010

Definition at line 344 of file hw.h.

#define IFE_PSC_FORCE_POLARITY   0x0020

Definition at line 345 of file hw.h.

#define IFE_PSCL_PROBE_LEDS_OFF   0x0006 /* Force LEDs 0 and 2 off */

Definition at line 349 of file hw.h.

#define IFE_PSCL_PROBE_LEDS_ON   0x0007 /* Force LEDs 0 and 2 on */

Definition at line 350 of file hw.h.

#define IFE_PSCL_PROBE_MODE   0x0020

Definition at line 348 of file hw.h.

#define IGP01E1000_PHY_LINK_HEALTH   0x13 /* PHY Link Health */

Definition at line 248 of file hw.h.

#define IGP01E1000_PHY_PAGE_SELECT   0x1F /* Page Select */

Definition at line 250 of file hw.h.

#define IGP01E1000_PHY_PCS_INIT_REG   0x00B4

Definition at line 268 of file hw.h.

#define IGP01E1000_PHY_POLARITY_MASK   0x0078

Definition at line 269 of file hw.h.

#define IGP01E1000_PHY_PORT_CONFIG   0x10 /* Port Config */

Definition at line 245 of file hw.h.

#define IGP01E1000_PHY_PORT_CTRL   0x12 /* Control */

Definition at line 247 of file hw.h.

#define IGP01E1000_PHY_PORT_STATUS   0x11 /* Status */

Definition at line 246 of file hw.h.

#define IGP01E1000_PLHR_SS_DOWNGRADE   0x8000

Definition at line 280 of file hw.h.

#define IGP01E1000_PSCFR_SMART_SPEED   0x0080

Definition at line 274 of file hw.h.

#define IGP01E1000_PSCR_AUTO_MDIX   0x1000

Definition at line 271 of file hw.h.

#define IGP01E1000_PSCR_FORCE_MDI_MDIX   0x2000 /* 0=MDI, 1=MDIX */

Definition at line 272 of file hw.h.

#define IGP01E1000_PSSR_MDIX   0x0800

Definition at line 283 of file hw.h.

#define IGP01E1000_PSSR_POLARITY_REVERSED   0x0002

Definition at line 282 of file hw.h.

#define IGP01E1000_PSSR_SPEED_1000MBPS   0xC000

Definition at line 285 of file hw.h.

#define IGP01E1000_PSSR_SPEED_MASK   0xC000

Definition at line 284 of file hw.h.

#define IGP02E1000_AGC_LENGTH_MASK   0x7F

Definition at line 294 of file hw.h.

#define IGP02E1000_AGC_LENGTH_SHIFT   9 /* Course - 15:13, Fine - 12:9 */

Definition at line 293 of file hw.h.

#define IGP02E1000_AGC_RANGE   15

Definition at line 295 of file hw.h.

#define IGP02E1000_PHY_AGC_A   0x11B1

Definition at line 288 of file hw.h.

#define IGP02E1000_PHY_AGC_B   0x12B1

Definition at line 289 of file hw.h.

#define IGP02E1000_PHY_AGC_C   0x14B1

Definition at line 290 of file hw.h.

#define IGP02E1000_PHY_AGC_D   0x18B1

Definition at line 291 of file hw.h.

#define IGP02E1000_PHY_CHANNEL_NUM   4

Definition at line 287 of file hw.h.

#define IGP02E1000_PHY_POWER_MGMT   0x19 /* Power Management */

Definition at line 249 of file hw.h.

#define IGP02E1000_PM_D0_LPLU   0x0002 /* For D0a states */

Definition at line 277 of file hw.h.

#define IGP02E1000_PM_D3_LPLU   0x0004 /* For all other states */

Definition at line 278 of file hw.h.

#define IGP02E1000_PM_SPD   0x0001 /* Smart Power Down */

Definition at line 276 of file hw.h.

#define IGP_PAGE_SHIFT   5

Definition at line 252 of file hw.h.

#define MAX_MTA_REG   128

Definition at line 878 of file hw.h.

#define MAX_PS_BUFFERS   4

Definition at line 563 of file hw.h.

#define PHY_REG_MASK   0x1F

Definition at line 253 of file hw.h.

Enumeration Type Documentation

Enumerator:
e1000_1000t_rx_status_not_ok 
e1000_1000t_rx_status_ok 
e1000_1000t_rx_status_undefined 
e1000_1000t_rx_status_not_ok 
e1000_1000t_rx_status_ok 
e1000_1000t_rx_status_undefined 
e1000_1000t_rx_status_not_ok 
e1000_1000t_rx_status_ok 
e1000_1000t_rx_status_undefined 

Definition at line 488 of file hw.h.

Enumerator:
e1000_bus_width_unknown 
e1000_bus_width_32 
e1000_bus_width_64 
e1000_bus_width_reserved 
e1000_bus_width_unknown 
e1000_bus_width_pcie_x1 
e1000_bus_width_pcie_x2 
e1000_bus_width_pcie_x4 
e1000_bus_width_32 
e1000_bus_width_64 
e1000_bus_width_reserved 
e1000_bus_width_unknown 
e1000_bus_width_pcie_x1 
e1000_bus_width_pcie_x2 
e1000_bus_width_pcie_x4 
e1000_bus_width_pcie_x8 
e1000_bus_width_32 
e1000_bus_width_64 
e1000_bus_width_reserved 

Definition at line 478 of file hw.h.

Enumerator:
e1000_fc_none 
e1000_fc_rx_pause 
e1000_fc_tx_pause 
e1000_fc_full 
e1000_fc_default 
e1000_fc_none 
e1000_fc_rx_pause 
e1000_fc_tx_pause 
e1000_fc_full 
e1000_fc_default 

Definition at line 500 of file hw.h.

Enumerator:
e1000_undefined 
e1000_82542_rev2_0 
e1000_82542_rev2_1 
e1000_82543 
e1000_82544 
e1000_82540 
e1000_82545 
e1000_82545_rev_3 
e1000_82546 
e1000_ce4100 
e1000_82546_rev_3 
e1000_82541 
e1000_82541_rev_2 
e1000_82547 
e1000_82547_rev_2 
e1000_num_macs 
e1000_82571 
e1000_82572 
e1000_82573 
e1000_82574 
e1000_82583 
e1000_80003es2lan 
e1000_ich8lan 
e1000_ich9lan 
e1000_ich10lan 
e1000_pchlan 
e1000_pch2lan 
e1000_pch_lpt 
e1000_undefined 
e1000_82575 
e1000_82576 
e1000_82580 
e1000_i350 
e1000_i210 
e1000_i211 
e1000_num_macs 
e1000_undefined 
e1000_vfadapt 
e1000_vfadapt_i350 
e1000_num_macs 

Definition at line 425 of file hw.h.

Enumerator:
e1000_media_type_copper 
e1000_media_type_fiber 
e1000_media_type_internal_serdes 
e1000_num_media_types 
e1000_media_type_unknown 
e1000_media_type_copper 
e1000_media_type_fiber 
e1000_media_type_internal_serdes 
e1000_num_media_types 
e1000_media_type_unknown 
e1000_media_type_copper 
e1000_media_type_internal_serdes 
e1000_num_media_types 

Definition at line 440 of file hw.h.

Enumerator:
e1000_ms_hw_default 
e1000_ms_force_master 
e1000_ms_force_slave 
e1000_ms_auto 
e1000_ms_hw_default 
e1000_ms_force_master 
e1000_ms_force_slave 
e1000_ms_auto 
e1000_ms_hw_default 
e1000_ms_force_master 
e1000_ms_force_slave 
e1000_ms_auto 

Definition at line 508 of file hw.h.

Enumerator:
e1000_nvm_override_none 
e1000_nvm_override_spi_small 
e1000_nvm_override_spi_large 
e1000_nvm_override_none 
e1000_nvm_override_spi_small 
e1000_nvm_override_spi_large 

Definition at line 456 of file hw.h.

Enumerator:
e1000_nvm_unknown 
e1000_nvm_none 
e1000_nvm_eeprom_spi 
e1000_nvm_flash_hw 
e1000_nvm_flash_sw 
e1000_nvm_unknown 
e1000_nvm_none 
e1000_nvm_eeprom_spi 
e1000_nvm_flash_hw 
e1000_nvm_flash_sw 

Definition at line 448 of file hw.h.

Enumerator:
e1000_phy_m88 
e1000_phy_igp 
e1000_phy_8211 
e1000_phy_8201 
e1000_phy_undefined 
e1000_phy_unknown 
e1000_phy_none 
e1000_phy_m88 
e1000_phy_igp 
e1000_phy_igp_2 
e1000_phy_gg82563 
e1000_phy_igp_3 
e1000_phy_ife 
e1000_phy_bm 
e1000_phy_82578 
e1000_phy_82577 
e1000_phy_82579 
e1000_phy_i217 
e1000_phy_unknown 
e1000_phy_none 
e1000_phy_m88 
e1000_phy_igp 
e1000_phy_igp_2 
e1000_phy_gg82563 
e1000_phy_igp_3 
e1000_phy_ife 
e1000_phy_82580 
e1000_phy_i210 

Definition at line 462 of file hw.h.

Enumerator:
e1000_rev_polarity_normal 
e1000_rev_polarity_reversed 
e1000_rev_polarity_undefined 
e1000_rev_polarity_normal 
e1000_rev_polarity_reversed 
e1000_rev_polarity_undefined 
e1000_rev_polarity_normal 
e1000_rev_polarity_reversed 
e1000_rev_polarity_undefined 

Definition at line 494 of file hw.h.

Enumerator:
e1000_serdes_link_down 
e1000_serdes_link_autoneg_progress 
e1000_serdes_link_autoneg_complete 
e1000_serdes_link_forced_up 

Definition at line 521 of file hw.h.

Enumerator:
e1000_smart_speed_default 
e1000_smart_speed_on 
e1000_smart_speed_off 
e1000_smart_speed_default 
e1000_smart_speed_on 
e1000_smart_speed_off 
e1000_smart_speed_default 
e1000_smart_speed_on 
e1000_smart_speed_off 

Definition at line 515 of file hw.h.

Enumerator:
E1000_CTRL 
E1000_STATUS 
E1000_EECD 
E1000_EERD 
E1000_CTRL_EXT 
E1000_FLA 
E1000_MDIC 
E1000_SCTL 
E1000_FCAL 
E1000_FCAH 
E1000_FEXTNVM4 
E1000_FEXTNVM 
E1000_FCT 
E1000_VET 
E1000_FEXTNVM3 
E1000_ICR 
E1000_ITR 
E1000_ICS 
E1000_IMS 
E1000_IMC 
E1000_EIAC_82574 
E1000_IAM 
E1000_IVAR 
E1000_EITR_82574_BASE 
E1000_RCTL 
E1000_FCTTV 
E1000_TXCW 
E1000_RXCW 
E1000_TCTL 
E1000_TCTL_EXT 
E1000_TIPG 
E1000_AIT 
E1000_LEDCTL 
E1000_EXTCNF_CTRL 
E1000_EXTCNF_SIZE 
E1000_PHY_CTRL 
E1000_PBA 
E1000_PBS 
E1000_EEMNGCTL 
E1000_EEWR 
E1000_FLOP 
E1000_PBA_ECC 
E1000_ERT 
E1000_FCRTL 
E1000_FCRTH 
E1000_PSRCTL 
E1000_RDBAL_BASE 
E1000_RDBAH_BASE 
E1000_RDLEN_BASE 
E1000_RDH_BASE 
E1000_RDT_BASE 
E1000_RDTR 
E1000_RXDCTL_BASE 
E1000_RADV 
E1000_KABGTXD 
E1000_TDBAL_BASE 
E1000_TDBAH_BASE 
E1000_TDLEN_BASE 
E1000_TDH_BASE 
E1000_TDT_BASE 
E1000_TIDV 
E1000_TXDCTL_BASE 
E1000_TADV 
E1000_TARC_BASE 
E1000_CRCERRS 
E1000_ALGNERRC 
E1000_SYMERRS 
E1000_RXERRC 
E1000_MPC 
E1000_SCC 
E1000_ECOL 
E1000_MCC 
E1000_LATECOL 
E1000_COLC 
E1000_DC 
E1000_TNCRS 
E1000_SEC 
E1000_CEXTERR 
E1000_RLEC 
E1000_XONRXC 
E1000_XONTXC 
E1000_XOFFRXC 
E1000_XOFFTXC 
E1000_FCRUC 
E1000_PRC64 
E1000_PRC127 
E1000_PRC255 
E1000_PRC511 
E1000_PRC1023 
E1000_PRC1522 
E1000_GPRC 
E1000_BPRC 
E1000_MPRC 
E1000_GPTC 
E1000_GORCL 
E1000_GORCH 
E1000_GOTCL 
E1000_GOTCH 
E1000_RNBC 
E1000_RUC 
E1000_RFC 
E1000_ROC 
E1000_RJC 
E1000_MGTPRC 
E1000_MGTPDC 
E1000_MGTPTC 
E1000_TORL 
E1000_TORH 
E1000_TOTL 
E1000_TOTH 
E1000_TPR 
E1000_TPT 
E1000_PTC64 
E1000_PTC127 
E1000_PTC255 
E1000_PTC511 
E1000_PTC1023 
E1000_PTC1522 
E1000_MPTC 
E1000_BPTC 
E1000_TSCTC 
E1000_TSCTFC 
E1000_IAC 
E1000_ICRXPTC 
E1000_ICRXATC 
E1000_ICTXPTC 
E1000_ICTXATC 
E1000_ICTXQEC 
E1000_ICTXQMTC 
E1000_ICRXDMTC 
E1000_ICRXOC 
E1000_RXCSUM 
E1000_RFCTL 
E1000_MTA 
E1000_RAL_BASE 
E1000_RAH_BASE 
E1000_SHRAL_PCH_LPT_BASE 
E1000_SHRAH_PCH_LTP_BASE 
E1000_SHRAL_BASE 
E1000_SHRAH_BASE 
E1000_VFTA 
E1000_WUC 
E1000_WUFC 
E1000_WUS 
E1000_MRQC 
E1000_MANC 
E1000_FFLT 
E1000_HOST_IF 
E1000_KMRNCTRLSTA 
E1000_MANC2H 
E1000_MDEF_BASE 
E1000_SW_FW_SYNC 
E1000_GCR 
E1000_GCR2 
E1000_FACTPS 
E1000_SWSM 
E1000_FWSM 
E1000_SWSM2 
E1000_RETA_BASE 
E1000_RSSRK_BASE 
E1000_FFLT_DBG 
E1000_PCH_RAICC_BASE 
E1000_HICR 

Definition at line 39 of file hw.h.