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emu10k1.h
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1 #ifndef __SOUND_EMU10K1_H
2 #define __SOUND_EMU10K1_H
3 
4 #include <linux/types.h>
5 
6 /*
7  * Copyright (c) by Jaroslav Kysela <[email protected]>,
8  * Creative Labs, Inc.
9  * Definitions for EMU10K1 (SB Live!) chips
10  *
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25  *
26  */
27 
28 #ifdef __KERNEL__
29 
30 #include <sound/pcm.h>
31 #include <sound/rawmidi.h>
32 #include <sound/hwdep.h>
33 #include <sound/ac97_codec.h>
34 #include <sound/util_mem.h>
35 #include <sound/pcm-indirect.h>
36 #include <sound/timer.h>
37 #include <linux/interrupt.h>
38 #include <linux/mutex.h>
39 
40 #include <asm/io.h>
41 
42 /* ------------------- DEFINES -------------------- */
43 
44 #define EMUPAGESIZE 4096
45 #define MAXREQVOICES 8
46 #define MAXPAGES 8192
47 #define RESERVED 0
48 #define NUM_MIDI 16
49 #define NUM_G 64 /* use all channels */
50 #define NUM_FXSENDS 4
51 #define NUM_EFX_PLAYBACK 16
52 
53 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
54 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
55 #define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */
56  /* See ALSA bug #1276 - rlrevell */
57 
58 #define TMEMSIZE 256*1024
59 #define TMEMSIZEREG 4
60 
61 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
62 
63 // Audigy specify registers are prefixed with 'A_'
64 
65 /************************************************************************************************/
66 /* PCI function 0 registers, address = <val> + PCIBASE0 */
67 /************************************************************************************************/
68 
69 #define PTR 0x00 /* Indexed register set pointer register */
70  /* NOTE: The CHANNELNUM and ADDRESS words can */
71  /* be modified independently of each other. */
72 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
73  /* channel number of the register to be */
74  /* accessed. For non per-channel registers the */
75  /* value should be set to zero. */
76 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
77 #define A_PTR_ADDRESS_MASK 0x0fff0000
78 
79 #define DATA 0x04 /* Indexed register set data register */
80 
81 #define IPR 0x08 /* Global interrupt pending register */
82  /* Clear pending interrupts by writing a 1 to */
83  /* the relevant bits and zero to the other bits */
84 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
85  to interrupt */
86 #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
87  which INTE bits enable it) */
88 
89 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
90 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
91 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
92 
93 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
94 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
95 
96 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
97 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
98 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
99 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
100 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
101 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
102 #define IPR_MUTE 0x00040000 /* Mute button pressed */
103 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
104 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
105 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
106 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
107 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
108 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
109 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
110 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
111 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
112 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
113 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
114 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
115 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
116  /* highest set channel in CLIPL, CLIPH, HLIPL, */
117  /* or HLIPH. When IP is written with CL set, */
118  /* the bit in H/CLIPL or H/CLIPH corresponding */
119  /* to the CIN value written will be cleared. */
120 
121 #define INTE 0x0c /* Interrupt enable register */
122 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
123 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
124 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
125 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
126 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
127 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
128 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
129 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
130 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
131 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
132 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
133 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
134 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
135 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
136 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
137 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
138 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
139 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
140 
141 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
142  /* NOTE: There is no reason to use this under */
143  /* Linux, and it will cause odd hardware */
144  /* behavior and possibly random segfaults and */
145  /* lockups if enabled. */
146 
147 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
148 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
149 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
150 
151 
152 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
153  /* NOTE: This bit must always be enabled */
154 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
155 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
156 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
157 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
158 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
159 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
160 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
161 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
162 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
163 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
164 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
165 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
166 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
167 
168 #define WC 0x10 /* Wall Clock register */
169 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
170 #define WC_SAMPLECOUNTER 0x14060010
171 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
172  /* NOTE: Each channel takes 1/64th of a sample */
173  /* period to be serviced. */
174 
175 #define HCFG 0x14 /* Hardware config register */
176  /* NOTE: There is no reason to use the legacy */
177  /* SoundBlaster emulation stuff described below */
178  /* under Linux, and all kinds of weird hardware */
179  /* behavior can result if you try. Don't. */
180 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
181 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
182 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
183 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
184 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
185 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
186 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
187 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
188 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
189 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
190 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
191 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
192  /* NOTE: The rest of the bits in this register */
193  /* _are_ relevant under Linux. */
194 #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
195 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
196 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
197 #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
198 
199 /* Specific to Alice2, CA0102 */
200 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
201 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
202 #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
203  /* will automatically mute their output when */
204  /* they are not rate-locked to the external */
205  /* async audio source */
206 #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
207  /* will automatically mute their output when */
208  /* the SPDIF V-bit indicates invalid audio */
209 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
210 #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
211 /* 0x00000800 not used on Alice2 */
212 #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
213  /* phase track the previous input. */
214  /* I2S0 can phase track the last S/PDIF input */
215 #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
216  /* conversion for the corresponding */
217  /* I2S format input */
218 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
219 
220 
221 
222 /* Older chips */
223 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
224 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
225 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
226 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
227 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
228 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
229 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
230 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
231 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
232 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
233  /* 1 = Force all 3 async digital inputs to use */
234  /* the same async sample rate tracker (ZVIDEO) */
235 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
236 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
237 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
238 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
239 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
240  /* will automatically mute their output when */
241  /* they are not rate-locked to the external */
242  /* async audio source */
243 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
244  /* NOTE: This should generally never be used. */
245 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
246  /* NOTE: This should generally never be used. */
247 #define HCFG_LOCKTANKCACHE 0x01020014
248 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
249  /* NOTE: This is a 'cheap' way to implement a */
250  /* master mute function on the mute button, and */
251  /* in general should not be used unless a more */
252  /* sophisticated master mute function has not */
253  /* been written. */
254 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
255  /* Should be set to 1 when the EMU10K1 is */
256  /* completely initialized. */
257 
258 //For Audigy, MPU port move to 0x70-0x74 ptr register
259 
260 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
261 
262 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
263 #define MUCMD_RESET 0xff /* RESET command */
264 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
265  /* NOTE: All other commands are ignored */
266 
267 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
268 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
269 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
270 
271 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
272 #define A_GPINPUT_MASK 0xff00
273 #define A_GPOUTPUT_MASK 0x00ff
274 
275 // Audigy output/GPIO stuff taken from the kX drivers
276 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
277 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
278 #define A_IOCFG_ENABLE_DIGITAL 0x0004
279 #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
280 #define A_IOCFG_UNKNOWN_20 0x0020
281 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
282 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
283 #define A_IOCFG_GPOUT2 0x0001 /* IR */
284 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
285  /* + digital for generic 10k2 */
286 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
287 #define A_IOCFG_FRONT_JACK 0x4000
288 #define A_IOCFG_REAR_JACK 0x8000
289 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
290 
291 /* outputs:
292  * for audigy2 platinum: 0xa00
293  * for a2 platinum ex: 0x1c00
294  * for a1 platinum: 0x0
295  */
296 
297 #define TIMER 0x1a /* Timer terminal count register */
298  /* NOTE: After the rate is changed, a maximum */
299  /* of 1024 sample periods should be allowed */
300  /* before the new rate is guaranteed accurate. */
301 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
302  /* 0 == 1024 periods, [1..4] are not useful */
303 #define TIMER_RATE 0x0a00001a
304 
305 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
306 
307 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
308 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
309 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
310 
311 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
312 #define PTR2 0x20 /* Indexed register set pointer register */
313 #define DATA2 0x24 /* Indexed register set data register */
314 #define IPR2 0x28 /* P16V interrupt pending register */
315 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
316 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
317 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
318 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
319  /* 0x00000100 Playback. Only in once per period.
320  * 0x00110000 Capture. Int on half buffer.
321  */
322 #define INTE2 0x2c /* P16V Interrupt enable register. */
323 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
324 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
325 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
326 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
327 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
328 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
329 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
330 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
331 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
332 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
333 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
334  /* 0x00000000 2-channel output. */
335  /* 0x00000200 8-channel output. */
336  /* 0x00000004 pauses stream/irq fail. */
337  /* Rest of bits no nothing to sound output */
338  /* bit 0: Enable P16V audio.
339  * bit 1: Lock P16V record memory cache.
340  * bit 2: Lock P16V playback memory cache.
341  * bit 3: Dummy record insert zero samples.
342  * bit 8: Record 8-channel in phase.
343  * bit 9: Playback 8-channel in phase.
344  * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
345  * bit 13: Playback mixer enable.
346  * bit 14: Route SRC48 mixer output to fx engine.
347  * bit 15: Enable IEEE 1394 chip.
348  */
349 #define IPR3 0x38 /* Cdif interrupt pending register */
350 #define INTE3 0x3c /* Cdif interrupt enable register. */
351 /************************************************************************************************/
352 /* PCI function 1 registers, address = <val> + PCIBASE1 */
353 /************************************************************************************************/
354 
355 #define JOYSTICK1 0x00 /* Analog joystick port register */
356 #define JOYSTICK2 0x01 /* Analog joystick port register */
357 #define JOYSTICK3 0x02 /* Analog joystick port register */
358 #define JOYSTICK4 0x03 /* Analog joystick port register */
359 #define JOYSTICK5 0x04 /* Analog joystick port register */
360 #define JOYSTICK6 0x05 /* Analog joystick port register */
361 #define JOYSTICK7 0x06 /* Analog joystick port register */
362 #define JOYSTICK8 0x07 /* Analog joystick port register */
363 
364 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
365 /* When reading, use these bitfields: */
366 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
367 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
368 
369 
370 /********************************************************************************************************/
371 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
372 /********************************************************************************************************/
373 
374 #define CPF 0x00 /* Current pitch and fraction register */
375 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
376 #define CPF_CURRENTPITCH 0x10100000
377 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
378 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
379 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
380 
381 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
382 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
383 #define PTRX_PITCHTARGET 0x10100001
384 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
385 #define PTRX_FXSENDAMOUNT_A 0x08080001
386 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
387 #define PTRX_FXSENDAMOUNT_B 0x08000001
388 
389 #define CVCF 0x02 /* Current volume and filter cutoff register */
390 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
391 #define CVCF_CURRENTVOL 0x10100002
392 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
393 #define CVCF_CURRENTFILTER 0x10000002
394 
395 #define VTFT 0x03 /* Volume target and filter cutoff target register */
396 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
397 #define VTFT_VOLUMETARGET 0x10100003
398 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
399 #define VTFT_FILTERTARGET 0x10000003
400 
401 #define Z1 0x05 /* Filter delay memory 1 register */
402 
403 #define Z2 0x04 /* Filter delay memory 2 register */
404 
405 #define PSST 0x06 /* Send C amount and loop start address register */
406 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
407 
408 #define PSST_FXSENDAMOUNT_C 0x08180006
409 
410 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
411 #define PSST_LOOPSTARTADDR 0x18000006
412 
413 #define DSL 0x07 /* Send D amount and loop start address register */
414 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
415 
416 #define DSL_FXSENDAMOUNT_D 0x08180007
417 
418 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
419 #define DSL_LOOPENDADDR 0x18000007
420 
421 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
422 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
423 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
424  /* 1 == full band, 7 == lowpass */
425  /* ROM 0 is used when pitch shifting downward or less */
426  /* then 3 semitones upward. Increasingly higher ROM */
427  /* numbers are used, typically in steps of 3 semitones, */
428  /* as upward pitch shifting is performed. */
429 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
430 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
431 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
432 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
433 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
434 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
435 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
436 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
437 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
438 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
439 #define CCCA_CURRADDR 0x18000008
440 
441 /* undefine CCR to avoid conflict with the definition for SH */
442 #undef CCR
443 #define CCR 0x09 /* Cache control register */
444 #define CCR_CACHEINVALIDSIZE 0x07190009
445 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
446 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
447 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
448 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
449 #define CCR_READADDRESS 0x06100009
450 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
451 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
452  /* NOTE: This is valid only if CACHELOOPFLAG is set */
453 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
454 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
455 
456 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
457  /* NOTE: This register is normally not used */
458 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
459 
460 #define FXRT 0x0b /* Effects send routing register */
461  /* NOTE: It is illegal to assign the same routing to */
462  /* two effects sends. */
463 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
464 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
465 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
466 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
467 
468 #define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
469 #define MAPA 0x0c /* Cache map A */
470 
471 #define MAPB 0x0d /* Cache map B */
472 
473 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
474 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
475 
476 /* 0x0e, 0x0f: Not used */
477 
478 #define ENVVOL 0x10 /* Volume envelope register */
479 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
480  /* 0x8000-n == 666*n usec delay */
481 
482 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
483 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
484 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
485 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
486  /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
487 
488 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
489 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
490 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
491 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
492  /* this channel and from writing to pitch, filter and */
493  /* volume targets. */
494 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
495  /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
496 
497 #define LFOVAL1 0x13 /* Modulation LFO value */
498 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
499  /* 0x8000-n == 666*n usec delay */
500 
501 #define ENVVAL 0x14 /* Modulation envelope register */
502 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
503  /* 0x8000-n == 666*n usec delay */
504 
505 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
506 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
507 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
508 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
509  /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
510 
511 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
512 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
513 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
514 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
515  /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
516 
517 #define LFOVAL2 0x17 /* Vibrato LFO register */
518 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
519  /* 0x8000-n == 666*n usec delay */
520 
521 #define IP 0x18 /* Initial pitch register */
522 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
523  /* 4 bits of octave, 12 bits of fractional octave */
524 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
525 
526 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
527 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
528  /* 6 most significant bits are semitones */
529  /* 2 least significant bits are fractions */
530 #define IFATN_FILTERCUTOFF 0x08080019
531 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
532 #define IFATN_ATTENUATION 0x08000019
533 
534 
535 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
536 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
537  /* Signed 2's complement, +/- one octave peak extremes */
538 #define PEFE_PITCHAMOUNT 0x0808001a
539 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
540  /* Signed 2's complement, +/- six octaves peak extremes */
541 #define PEFE_FILTERAMOUNT 0x0800001a
542 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
543 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
544  /* Signed 2's complement, +/- one octave extremes */
545 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
546  /* Signed 2's complement, +/- three octave extremes */
547 
548 
549 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
550 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
551  /* Signed 2's complement, with +/- 12dB extremes */
552 
553 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
554  /* ??Hz steps, maximum of ?? Hz. */
555 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
556 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
557  /* Signed 2's complement, +/- one octave extremes */
558 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
559  /* 0.039Hz steps, maximum of 9.85 Hz. */
560 
561 #define TEMPENV 0x1e /* Tempory envelope register */
562 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
563  /* NOTE: All channels contain internal variables; do */
564  /* not write to these locations. */
565 
566 /* 0x1f: not used */
567 
568 #define CD0 0x20 /* Cache data 0 register */
569 #define CD1 0x21 /* Cache data 1 register */
570 #define CD2 0x22 /* Cache data 2 register */
571 #define CD3 0x23 /* Cache data 3 register */
572 #define CD4 0x24 /* Cache data 4 register */
573 #define CD5 0x25 /* Cache data 5 register */
574 #define CD6 0x26 /* Cache data 6 register */
575 #define CD7 0x27 /* Cache data 7 register */
576 #define CD8 0x28 /* Cache data 8 register */
577 #define CD9 0x29 /* Cache data 9 register */
578 #define CDA 0x2a /* Cache data A register */
579 #define CDB 0x2b /* Cache data B register */
580 #define CDC 0x2c /* Cache data C register */
581 #define CDD 0x2d /* Cache data D register */
582 #define CDE 0x2e /* Cache data E register */
583 #define CDF 0x2f /* Cache data F register */
584 
585 /* 0x30-3f seem to be the same as 0x20-2f */
586 
587 #define PTB 0x40 /* Page table base register */
588 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
589 
590 #define TCB 0x41 /* Tank cache base register */
591 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
592 
593 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
594 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
595 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
596  /* NOTE: To guarantee phase coherency, both channels */
597  /* must be disabled prior to enabling both channels. */
598 #define A_ADCCR_RCHANENABLE 0x00000020
599 #define A_ADCCR_LCHANENABLE 0x00000010
600 
601 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
602 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
603 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
604 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
605 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
606 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
607 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
608 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
609 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
610 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
611 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
612 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
613 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
614 
615 #define FXWC 0x43 /* FX output write channels register */
616  /* When set, each bit enables the writing of the */
617  /* corresponding FX output channel (internal registers */
618  /* 0x20-0x3f) to host memory. This mode of recording */
619  /* is 16bit, 48KHz only. All 32 channels can be enabled */
620  /* simultaneously. */
621 
622 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
623 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
624 #define FXWC_DEFAULTROUTE_A (1<<12)
625 #define FXWC_DEFAULTROUTE_D (1<<13)
626 #define FXWC_ADCLEFT (1<<18)
627 #define FXWC_CDROMSPDIFLEFT (1<<18)
628 #define FXWC_ADCRIGHT (1<<19)
629 #define FXWC_CDROMSPDIFRIGHT (1<<19)
630 #define FXWC_MIC (1<<20)
631 #define FXWC_ZOOMLEFT (1<<20)
632 #define FXWC_ZOOMRIGHT (1<<21)
633 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
634 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
635 
636 #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
637 
638 #define TCBS 0x44 /* Tank cache buffer size register */
639 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
640 #define TCBS_BUFFSIZE_16K 0x00000000
641 #define TCBS_BUFFSIZE_32K 0x00000001
642 #define TCBS_BUFFSIZE_64K 0x00000002
643 #define TCBS_BUFFSIZE_128K 0x00000003
644 #define TCBS_BUFFSIZE_256K 0x00000004
645 #define TCBS_BUFFSIZE_512K 0x00000005
646 #define TCBS_BUFFSIZE_1024K 0x00000006
647 #define TCBS_BUFFSIZE_2048K 0x00000007
648 
649 #define MICBA 0x45 /* AC97 microphone buffer address register */
650 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
651 
652 #define ADCBA 0x46 /* ADC buffer address register */
653 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
654 
655 #define FXBA 0x47 /* FX Buffer Address */
656 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
657 
658 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
659 
660 #define MICBS 0x49 /* Microphone buffer size register */
661 
662 #define ADCBS 0x4a /* ADC buffer size register */
663 
664 #define FXBS 0x4b /* FX buffer size register */
665 
666 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
667 
668 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
669 #define ADCBS_BUFSIZE_NONE 0x00000000
670 #define ADCBS_BUFSIZE_384 0x00000001
671 #define ADCBS_BUFSIZE_448 0x00000002
672 #define ADCBS_BUFSIZE_512 0x00000003
673 #define ADCBS_BUFSIZE_640 0x00000004
674 #define ADCBS_BUFSIZE_768 0x00000005
675 #define ADCBS_BUFSIZE_896 0x00000006
676 #define ADCBS_BUFSIZE_1024 0x00000007
677 #define ADCBS_BUFSIZE_1280 0x00000008
678 #define ADCBS_BUFSIZE_1536 0x00000009
679 #define ADCBS_BUFSIZE_1792 0x0000000a
680 #define ADCBS_BUFSIZE_2048 0x0000000b
681 #define ADCBS_BUFSIZE_2560 0x0000000c
682 #define ADCBS_BUFSIZE_3072 0x0000000d
683 #define ADCBS_BUFSIZE_3584 0x0000000e
684 #define ADCBS_BUFSIZE_4096 0x0000000f
685 #define ADCBS_BUFSIZE_5120 0x00000010
686 #define ADCBS_BUFSIZE_6144 0x00000011
687 #define ADCBS_BUFSIZE_7168 0x00000012
688 #define ADCBS_BUFSIZE_8192 0x00000013
689 #define ADCBS_BUFSIZE_10240 0x00000014
690 #define ADCBS_BUFSIZE_12288 0x00000015
691 #define ADCBS_BUFSIZE_14366 0x00000016
692 #define ADCBS_BUFSIZE_16384 0x00000017
693 #define ADCBS_BUFSIZE_20480 0x00000018
694 #define ADCBS_BUFSIZE_24576 0x00000019
695 #define ADCBS_BUFSIZE_28672 0x0000001a
696 #define ADCBS_BUFSIZE_32768 0x0000001b
697 #define ADCBS_BUFSIZE_40960 0x0000001c
698 #define ADCBS_BUFSIZE_49152 0x0000001d
699 #define ADCBS_BUFSIZE_57344 0x0000001e
700 #define ADCBS_BUFSIZE_65536 0x0000001f
701 
702 /* Current Send B, A Amounts */
703 #define A_CSBA 0x4c
704 
705 /* Current Send D, C Amounts */
706 #define A_CSDC 0x4d
707 
708 /* Current Send F, E Amounts */
709 #define A_CSFE 0x4e
710 
711 /* Current Send H, G Amounts */
712 #define A_CSHG 0x4f
713 
714 
715 #define CDCS 0x50 /* CD-ROM digital channel status register */
716 
717 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
718 
719 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
720 
721 /* S/PDIF Input C Channel Status */
722 #define A_SPSC 0x52
723 
724 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
725 
726 #define A_DBG 0x53
727 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
728 #define A_DBG_ZC 0x40000000 /* zero tram counter */
729 #define A_DBG_STEP_ADDR 0x000003ff
730 #define A_DBG_SATURATION_OCCURED 0x20000000
731 #define A_DBG_SATURATION_ADDR 0x0ffc0000
732 
733 // NOTE: 0x54,55,56: 64-bit
734 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
735 
736 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
737 
738 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
739 
740 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
741 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
742 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
743 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
744 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
745 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
746 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
747 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
748 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
749 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
750 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
751 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
752 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
753 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
754 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
755 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
756 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
757 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
758 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
759 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
760 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
761 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
762 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
763 
764 /* 0x57: Not used */
765 
766 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
767 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
768 
769 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
770 
771 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
772 
773 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
774 
775 #define SOLEL 0x5c /* Stop on loop enable low register */
776 
777 #define SOLEH 0x5d /* Stop on loop enable high register */
778 
779 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
780 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
781 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
782 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
783 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
784 
785 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
786 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
787 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
788 #define AC97SLOT_CNTR 0x10 /* Center enable */
789 #define AC97SLOT_LFE 0x20 /* LFE enable */
790 
791 /* PCB Revision */
792 #define A_PCB 0x5f
793 
794 // NOTE: 0x60,61,62: 64-bit
795 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
796 
797 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
798 
799 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
800  /* NOTE: This one has no SPDIFLOCKED field */
801  /* Assumes sample lock */
802 
803 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
804 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
805 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
806 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
807 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
808 
809 /* Note that these values can vary +/- by a small amount */
810 #define SRCS_SPDIFRATE_44 0x0003acd9
811 #define SRCS_SPDIFRATE_48 0x00040000
812 #define SRCS_SPDIFRATE_96 0x00080000
813 
814 #define MICIDX 0x63 /* Microphone recording buffer index register */
815 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
816 #define MICIDX_IDX 0x10000063
817 
818 #define ADCIDX 0x64 /* ADC recording buffer index register */
819 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
820 #define ADCIDX_IDX 0x10000064
821 
822 #define A_ADCIDX 0x63
823 #define A_ADCIDX_IDX 0x10000063
824 
825 #define A_MICIDX 0x64
826 #define A_MICIDX_IDX 0x10000064
827 
828 #define FXIDX 0x65 /* FX recording buffer index register */
829 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
830 #define FXIDX_IDX 0x10000065
831 
832 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
833 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */
834 
835 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */
836 
837 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */
838 
839 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */
840 
841 /* S/PDIF Host Record Index (bypasses SRC) */
842 #define A_SPRI 0x6a
843 /* S/PDIF Host Record Address */
844 #define A_SPRA 0x6b
845 /* S/PDIF Host Record Control */
846 #define A_SPRC 0x6c
847 /* Delayed Interrupt Counter & Enable */
848 #define A_DICE 0x6d
849 /* Tank Table Base */
850 #define A_TTB 0x6e
851 /* Tank Delay Offset */
852 #define A_TDOF 0x6f
853 
854 /* This is the MPU port on the card (via the game port) */
855 #define A_MUDATA1 0x70
856 #define A_MUCMD1 0x71
857 #define A_MUSTAT1 A_MUCMD1
858 
859 /* This is the MPU port on the Audigy Drive */
860 #define A_MUDATA2 0x72
861 #define A_MUCMD2 0x73
862 #define A_MUSTAT2 A_MUCMD2
863 
864 /* The next two are the Audigy equivalent of FXWC */
865 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
866 /* Each bit selects a channel for recording */
867 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
868 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
869 
870 /* Extended Hardware Control */
871 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
872 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
873 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
874 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */
875 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
876 #define A_SPDIF_48000 0x00000000
877 #define A_SPDIF_192000 0x00000020
878 #define A_SPDIF_96000 0x00000040
879 #define A_SPDIF_44100 0x00000080
880 
881 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
882 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
883 #define A_I2S_CAPTURE_192000 0x00000200
884 #define A_I2S_CAPTURE_96000 0x00000400
885 #define A_I2S_CAPTURE_44100 0x00000800
886 
887 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
888 #define A_PCM_48000 0x00000000
889 #define A_PCM_192000 0x00002000
890 #define A_PCM_96000 0x00004000
891 #define A_PCM_44100 0x00008000
892 
893 /* I2S0 Sample Rate Tracker Status */
894 #define A_SRT3 0x77
895 
896 /* I2S1 Sample Rate Tracker Status */
897 #define A_SRT4 0x78
898 
899 /* I2S2 Sample Rate Tracker Status */
900 #define A_SRT5 0x79
901 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
902 
903 /* Tank Table DMA Address */
904 #define A_TTDA 0x7a
905 /* Tank Table DMA Data */
906 #define A_TTDD 0x7b
907 
908 #define A_FXRT2 0x7c
909 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
910 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
911 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
912 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
913 
914 #define A_SENDAMOUNTS 0x7d
915 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
916 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
917 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
918 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
919 /* 0x7c, 0x7e "high bit is used for filtering" */
920 
921 /* The send amounts for this one are the same as used with the emu10k1 */
922 #define A_FXRT1 0x7e
923 #define A_FXRT_CHANNELA 0x0000003f
924 #define A_FXRT_CHANNELB 0x00003f00
925 #define A_FXRT_CHANNELC 0x003f0000
926 #define A_FXRT_CHANNELD 0x3f000000
927 
928 /* 0x7f: Not used */
929 /* Each FX general purpose register is 32 bits in length, all bits are used */
930 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
931 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
932 
933 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
934 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
935 
936 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
937 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
938 /* locations are for external TRAM. */
939 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
940 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
941 
942 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
943 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
944 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
945 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
946 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
947 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
948 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
949 
950 #define MICROCODEBASE 0x400 /* Microcode data base address */
951 
952 /* Each DSP microcode instruction is mapped into 2 doublewords */
953 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
954 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
955 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
956 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
957 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
958 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
959 
960 
961 /* Audigy Soundcard have a different instruction format */
962 #define A_MICROCODEBASE 0x600
963 #define A_LOWORD_OPY_MASK 0x000007ff
964 #define A_LOWORD_OPX_MASK 0x007ff000
965 #define A_HIWORD_OPCODE_MASK 0x0f000000
966 #define A_HIWORD_RESULT_MASK 0x007ff000
967 #define A_HIWORD_OPA_MASK 0x000007ff
968 
969 /************************************************************************************************/
970 /* EMU1010m HANA FPGA registers */
971 /************************************************************************************************/
972 #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
973 #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
974 #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
975 #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
976 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
977 #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
978 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
979  /* Must be written after power on to reset DLL */
980  /* One is unable to detect the Audio dock without this */
981 #define EMU_HANA_WCLOCK_SRC_MASK 0x07
982 #define EMU_HANA_WCLOCK_INT_48K 0x00
983 #define EMU_HANA_WCLOCK_INT_44_1K 0x01
984 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
985 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
986 #define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
987 #define EMU_HANA_WCLOCK_2ND_HANA 0x05
988 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
989 #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
990 #define EMU_HANA_WCLOCK_MULT_MASK 0x18
991 #define EMU_HANA_WCLOCK_1X 0x00
992 #define EMU_HANA_WCLOCK_2X 0x08
993 #define EMU_HANA_WCLOCK_4X 0x10
994 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
995 
996 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
997 #define EMU_HANA_DEFCLOCK_48K 0x00
998 #define EMU_HANA_DEFCLOCK_44_1K 0x01
999 
1000 #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
1001 #define EMU_MUTE 0x00
1002 #define EMU_UNMUTE 0x01
1003 
1004 #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
1005 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
1006 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
1007 
1008 #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
1009 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1010 #define EMU_HANA_IRQ_ADAT 0x02
1011 #define EMU_HANA_IRQ_DOCK 0x04
1012 #define EMU_HANA_IRQ_DOCK_LOST 0x08
1013 
1014 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
1015 #define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
1016 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1017 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1018 #define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
1019 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1020 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1021 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1022 
1023 #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
1024 #define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1025 #define EMU_HANA_OPTICAL_IN_ADAT 0x01
1026 #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1027 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1028 
1029 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1030 #define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */
1031 #define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */
1032 
1033 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1034 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
1035 #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
1036 #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
1037 #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
1038 
1039 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1040 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
1041 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1042 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
1043 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
1044 #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
1045 #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
1046 
1047 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1048 #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
1049 #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
1050 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
1051 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
1052 #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
1053 #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
1054 
1055 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1056 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1057 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1058 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1059 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1060 
1061 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1062 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1063 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1064 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1065 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1066 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1067 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1068 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1069 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1070 
1071 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1072 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
1073 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
1074 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
1075 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
1076 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
1077 
1078 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1079 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1080 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
1081 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
1082 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
1083 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1084 
1085 /* 0x14 - 0x1f Unused R/W registers */
1086 #define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */
1087 #if 0 /* Already defined for reg 0x09 IRQ_ENABLE */
1088 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1089 #define EMU_HANA_IRQ_ADAT 0x02
1090 #define EMU_HANA_IRQ_DOCK 0x04
1091 #define EMU_HANA_IRQ_DOCK_LOST 0x08
1092 #endif
1093 
1094 #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
1095 #define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */
1096 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
1097 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
1098 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
1099 
1100 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */
1101 
1102 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1103 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1104 
1105 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1106 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1107 
1108 #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
1109 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1110 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1111 
1112 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1113 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1114 
1115 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1116 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1117 
1118 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1119 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1120 
1121 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1122 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1123 /* 0x30 - 0x3f Unused Read only registers */
1124 
1125 /************************************************************************************************/
1126 /* EMU1010m HANA Destinations */
1127 /************************************************************************************************/
1128 /* Hana, original 1010,1212,1820 using Alice2
1129  * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1130  * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1131  * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
1132  * 0x01, 0x00: Dock DAC 1 Left
1133  * 0x01, 0x04: Dock DAC 1 Right
1134  * 0x01, 0x08: Dock DAC 2 Left
1135  * 0x01, 0x0c: Dock DAC 2 Right
1136  * 0x01, 0x10: Dock DAC 3 Left
1137  * 0x01, 0x12: PHONES Left
1138  * 0x01, 0x14: Dock DAC 3 Right
1139  * 0x01, 0x16: PHONES Right
1140  * 0x01, 0x18: Dock DAC 4 Left
1141  * 0x01, 0x1a: S/PDIF Left
1142  * 0x01, 0x1c: Dock DAC 4 Right
1143  * 0x01, 0x1e: S/PDIF Right
1144  * 0x02, 0x00: Hana S/PDIF Left
1145  * 0x02, 0x01: Hana S/PDIF Right
1146  * 0x03, 0x00: Hanoa DAC Left
1147  * 0x03, 0x01: Hanoa DAC Right
1148  * 0x04, 0x00-0x07: Hana ADAT
1149  * 0x05, 0x00: I2S0 Left to Alice2
1150  * 0x05, 0x01: I2S0 Right to Alice2
1151  * 0x06, 0x00: I2S0 Left to Alice2
1152  * 0x06, 0x01: I2S0 Right to Alice2
1153  * 0x07, 0x00: I2S0 Left to Alice2
1154  * 0x07, 0x01: I2S0 Right to Alice2
1155  *
1156  * Hana2 never released, but used Tina
1157  * Not needed.
1158  *
1159  * Hana3, rev2 1010,1212,1616 using Tina
1160  * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1161  * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1162  * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1163  * 0x01, 0x00: Dock DAC 1 Left
1164  * 0x01, 0x04: Dock DAC 1 Right
1165  * 0x01, 0x08: Dock DAC 2 Left
1166  * 0x01, 0x0c: Dock DAC 2 Right
1167  * 0x01, 0x10: Dock DAC 3 Left
1168  * 0x01, 0x12: Dock S/PDIF Left
1169  * 0x01, 0x14: Dock DAC 3 Right
1170  * 0x01, 0x16: Dock S/PDIF Right
1171  * 0x01, 0x18-0x1f: Dock ADAT 0-7
1172  * 0x02, 0x00: Hana3 S/PDIF Left
1173  * 0x02, 0x01: Hana3 S/PDIF Right
1174  * 0x03, 0x00: Hanoa DAC Left
1175  * 0x03, 0x01: Hanoa DAC Right
1176  * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1177  * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1178  * 0x06-0x07: Not used
1179  *
1180  * HanaLite, rev1 0404 using Alice2
1181  * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1182  * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1183  * 0x01: Not used
1184  * 0x02, 0x00: S/PDIF Left
1185  * 0x02, 0x01: S/PDIF Right
1186  * 0x03, 0x00: DAC Left
1187  * 0x03, 0x01: DAC Right
1188  * 0x04-0x07: Not used
1189  *
1190  * HanaLiteLite, rev2 0404 using Alice2
1191  * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1192  * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1193  * 0x01: Not used
1194  * 0x02, 0x00: S/PDIF Left
1195  * 0x02, 0x01: S/PDIF Right
1196  * 0x03, 0x00: DAC Left
1197  * 0x03, 0x01: DAC Right
1198  * 0x04-0x07: Not used
1199  *
1200  * Mana, Cardbus 1616 using Tina2
1201  * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1202  * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1203  * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1204  * 0x01, 0x00: Dock DAC 1 Left
1205  * 0x01, 0x04: Dock DAC 1 Right
1206  * 0x01, 0x08: Dock DAC 2 Left
1207  * 0x01, 0x0c: Dock DAC 2 Right
1208  * 0x01, 0x10: Dock DAC 3 Left
1209  * 0x01, 0x12: Dock S/PDIF Left
1210  * 0x01, 0x14: Dock DAC 3 Right
1211  * 0x01, 0x16: Dock S/PDIF Right
1212  * 0x01, 0x18-0x1f: Dock ADAT 0-7
1213  * 0x02: Not used
1214  * 0x03, 0x00: Mana DAC Left
1215  * 0x03, 0x01: Mana DAC Right
1216  * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1217  * 0x05-0x07: Not used
1218  *
1219  *
1220  */
1221 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1222  * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture
1223  * - 16 x EMU_DST_ALICE2_EMU32_X.
1224  */
1225 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1226 /* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
1227  * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on
1228  * setup of mixer control for each destination - see emumixer.c -
1229  * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]
1230  */
1231 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
1232 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1233 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1234 #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1235 #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1236 #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1237 #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1238 #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1239 #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1240 #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1241 #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1242 #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
1243 #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
1244 #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
1245 #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
1246 #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
1247 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1248 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1249 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1250 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1251 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1252 #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1253 #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1254 #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1255 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1256 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1257 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1258 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1259 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1260 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1261 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1262 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1263 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1264 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1265 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1266 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1267 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1268 #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1269 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1270 #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1271 #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1272 #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1273 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1274 #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1275 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1276 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1277 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1278 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1279 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1280 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1281 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1282 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1283 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1284 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1285 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1286 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1287 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1288 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1289 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1290 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1291 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1292 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1293 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1294 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1295 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1296 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1297 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1298 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1299 #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
1300 #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
1301 #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
1302 #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
1303 #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
1304 #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
1305 #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
1306 
1307 /* Additional destinations for 1616(M)/Microdock */
1308 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1309 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112
1310 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1311 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113
1312 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1313 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116
1314 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1315 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117
1316 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1317 #define EMU_DST_MDOCK_ADAT 0x0118
1318 
1319 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1320 #define EMU_DST_MANA_DAC_LEFT 0x0300
1321 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1322 #define EMU_DST_MANA_DAC_RIGHT 0x0301
1323 
1324 /************************************************************************************************/
1325 /* EMU1010m HANA Sources */
1326 /************************************************************************************************/
1327 /* Hana, original 1010,1212,1820 using Alice2
1328  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1329  * 0x00,0x00-0x1f: Silence
1330  * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1331  * 0x01, 0x00: Dock Mic A
1332  * 0x01, 0x04: Dock Mic B
1333  * 0x01, 0x08: Dock ADC 1 Left
1334  * 0x01, 0x0c: Dock ADC 1 Right
1335  * 0x01, 0x10: Dock ADC 2 Left
1336  * 0x01, 0x14: Dock ADC 2 Right
1337  * 0x01, 0x18: Dock ADC 3 Left
1338  * 0x01, 0x1c: Dock ADC 3 Right
1339  * 0x02, 0x00: Hana ADC Left
1340  * 0x02, 0x01: Hana ADC Right
1341  * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1342  * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1343  * 0x04, 0x00-0x07: Hana ADAT
1344  * 0x05, 0x00: Hana S/PDIF Left
1345  * 0x05, 0x01: Hana S/PDIF Right
1346  * 0x06-0x07: Not used
1347  *
1348  * Hana2 never released, but used Tina
1349  * Not needed.
1350  *
1351  * Hana3, rev2 1010,1212,1616 using Tina
1352  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1353  * 0x00,0x00-0x1f: Silence
1354  * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1355  * 0x01, 0x00: Dock Mic A
1356  * 0x01, 0x04: Dock Mic B
1357  * 0x01, 0x08: Dock ADC 1 Left
1358  * 0x01, 0x0c: Dock ADC 1 Right
1359  * 0x01, 0x10: Dock ADC 2 Left
1360  * 0x01, 0x12: Dock S/PDIF Left
1361  * 0x01, 0x14: Dock ADC 2 Right
1362  * 0x01, 0x16: Dock S/PDIF Right
1363  * 0x01, 0x18-0x1f: Dock ADAT 0-7
1364  * 0x01, 0x18: Dock ADC 3 Left
1365  * 0x01, 0x1c: Dock ADC 3 Right
1366  * 0x02, 0x00: Hanoa ADC Left
1367  * 0x02, 0x01: Hanoa ADC Right
1368  * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1369  * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1370  * 0x04, 0x00-0x07: Hana3 ADAT
1371  * 0x05, 0x00: Hana3 S/PDIF Left
1372  * 0x05, 0x01: Hana3 S/PDIF Right
1373  * 0x06-0x07: Not used
1374  *
1375  * HanaLite, rev1 0404 using Alice2
1376  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1377  * 0x00,0x00-0x1f: Silence
1378  * 0x01: Not used
1379  * 0x02, 0x00: ADC Left
1380  * 0x02, 0x01: ADC Right
1381  * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1382  * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1383  * 0x04: Not used
1384  * 0x05, 0x00: S/PDIF Left
1385  * 0x05, 0x01: S/PDIF Right
1386  * 0x06-0x07: Not used
1387  *
1388  * HanaLiteLite, rev2 0404 using Alice2
1389  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1390  * 0x00,0x00-0x1f: Silence
1391  * 0x01: Not used
1392  * 0x02, 0x00: ADC Left
1393  * 0x02, 0x01: ADC Right
1394  * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1395  * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1396  * 0x04: Not used
1397  * 0x05, 0x00: S/PDIF Left
1398  * 0x05, 0x01: S/PDIF Right
1399  * 0x06-0x07: Not used
1400  *
1401  * Mana, Cardbus 1616 using Tina2
1402  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1403  * 0x00,0x00-0x1f: Silence
1404  * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1405  * 0x01, 0x00: Dock Mic A
1406  * 0x01, 0x04: Dock Mic B
1407  * 0x01, 0x08: Dock ADC 1 Left
1408  * 0x01, 0x0c: Dock ADC 1 Right
1409  * 0x01, 0x10: Dock ADC 2 Left
1410  * 0x01, 0x12: Dock S/PDIF Left
1411  * 0x01, 0x14: Dock ADC 2 Right
1412  * 0x01, 0x16: Dock S/PDIF Right
1413  * 0x01, 0x18-0x1f: Dock ADAT 0-7
1414  * 0x01, 0x18: Dock ADC 3 Left
1415  * 0x01, 0x1c: Dock ADC 3 Right
1416  * 0x02: Not used
1417  * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1418  * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1419  * 0x04-0x07: Not used
1420  *
1421  */
1422 
1423 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1424  * destinations using mixer control for each destination - see emumixer.c
1425  * Sources are either physical inputs of FPGA,
1426  * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
1427  * 16 x EMU_SRC_ALICE_EMU32B
1428  */
1429 #define EMU_SRC_SILENCE 0x0000 /* Silence */
1430 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1431 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1432 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1433 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1434 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1435 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1436 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1437 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1438 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1439 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1440 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1441 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1442 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1443 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1444 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1445 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1446 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1447 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1448 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1449 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1450 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1451 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1452 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1453 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1454 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1455 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1456 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1457 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1458 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1459 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1460 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1461 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1462 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1463 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1464 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1465 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1466 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1467 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1468 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1469 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1470 #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
1471 #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
1472 #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
1473 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1474 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1475 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1476 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1477 
1478 /* Additional inputs for 1616(M)/Microdock */
1479 /* Microdock S/PDIF Left, 1st or 48kHz only */
1480 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112
1481 /* Microdock S/PDIF Left, 2nd or 96kHz */
1482 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113
1483 /* Microdock S/PDIF Right, 1st or 48kHz only */
1484 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116
1485 /* Microdock S/PDIF Right, 2nd or 96kHz */
1486 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117
1487 /* Microdock ADAT 8 channel in +8 to +f */
1488 #define EMU_SRC_MDOCK_ADAT 0x0118
1489 
1490 /* 0x600 and 0x700 no used */
1491 
1492 /* ------------------- STRUCTURES -------------------- */
1493 
1494 enum {
1495  EMU10K1_EFX,
1496  EMU10K1_PCM,
1497  EMU10K1_SYNTH,
1498  EMU10K1_MIDI
1499 };
1500 
1501 struct snd_emu10k1;
1502 
1503 struct snd_emu10k1_voice {
1504  struct snd_emu10k1 *emu;
1505  int number;
1506  unsigned int use: 1,
1507  pcm: 1,
1508  efx: 1,
1509  synth: 1,
1510  midi: 1;
1511  void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1512 
1513  struct snd_emu10k1_pcm *epcm;
1514 };
1515 
1516 enum {
1517  PLAYBACK_EMUVOICE,
1518  PLAYBACK_EFX,
1519  CAPTURE_AC97ADC,
1520  CAPTURE_AC97MIC,
1521  CAPTURE_EFX
1522 };
1523 
1524 struct snd_emu10k1_pcm {
1525  struct snd_emu10k1 *emu;
1526  int type;
1527  struct snd_pcm_substream *substream;
1528  struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1529  struct snd_emu10k1_voice *extra;
1530  unsigned short running;
1531  unsigned short first_ptr;
1532  struct snd_util_memblk *memblk;
1533  unsigned int start_addr;
1534  unsigned int ccca_start_addr;
1535  unsigned int capture_ipr; /* interrupt acknowledge mask */
1536  unsigned int capture_inte; /* interrupt enable mask */
1537  unsigned int capture_ba_reg; /* buffer address register */
1538  unsigned int capture_bs_reg; /* buffer size register */
1539  unsigned int capture_idx_reg; /* buffer index register */
1540  unsigned int capture_cr_val; /* control value */
1541  unsigned int capture_cr_val2; /* control value2 (for audigy) */
1542  unsigned int capture_bs_val; /* buffer size value */
1543  unsigned int capture_bufsize; /* buffer size in bytes */
1544 };
1545 
1546 struct snd_emu10k1_pcm_mixer {
1547  /* mono, left, right x 8 sends (4 on emu10k1) */
1548  unsigned char send_routing[3][8];
1549  unsigned char send_volume[3][8];
1550  unsigned short attn[3];
1551  struct snd_emu10k1_pcm *epcm;
1552 };
1553 
1554 #define snd_emu10k1_compose_send_routing(route) \
1555 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1556 
1557 #define snd_emu10k1_compose_audigy_fxrt1(route) \
1558 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1559 
1560 #define snd_emu10k1_compose_audigy_fxrt2(route) \
1561 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1562 
1563 struct snd_emu10k1_memblk {
1564  struct snd_util_memblk mem;
1565  /* private part */
1566  int first_page, last_page, pages, mapped_page;
1567  unsigned int map_locked;
1568  struct list_head mapped_link;
1569  struct list_head mapped_order_link;
1570 };
1571 
1572 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1573 
1574 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1575 
1576 struct snd_emu10k1_fx8010_ctl {
1577  struct list_head list; /* list link container */
1578  unsigned int vcount;
1579  unsigned int count; /* count of GPR (1..16) */
1580  unsigned short gpr[32]; /* GPR number(s) */
1581  unsigned int value[32];
1582  unsigned int min; /* minimum range */
1583  unsigned int max; /* maximum range */
1584  unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1585  struct snd_kcontrol *kcontrol;
1586 };
1587 
1588 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1589 
1590 struct snd_emu10k1_fx8010_irq {
1591  struct snd_emu10k1_fx8010_irq *next;
1592  snd_fx8010_irq_handler_t *handler;
1593  unsigned short gpr_running;
1594  void *private_data;
1595 };
1596 
1597 struct snd_emu10k1_fx8010_pcm {
1598  unsigned int valid: 1,
1599  opened: 1,
1600  active: 1;
1601  unsigned int channels; /* 16-bit channels count */
1602  unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1603  unsigned int buffer_size; /* count of buffered samples */
1604  unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1605  unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1606  unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1607  unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1608  unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1609  unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1610  unsigned char etram[32]; /* external TRAM address & data */
1611  struct snd_pcm_indirect pcm_rec;
1612  unsigned int tram_pos;
1613  unsigned int tram_shift;
1614  struct snd_emu10k1_fx8010_irq *irq;
1615 };
1616 
1617 struct snd_emu10k1_fx8010 {
1618  unsigned short fxbus_mask; /* used FX buses (bitmask) */
1619  unsigned short extin_mask; /* used external inputs (bitmask) */
1620  unsigned short extout_mask; /* used external outputs (bitmask) */
1621  unsigned short pad1;
1622  unsigned int itram_size; /* internal TRAM size in samples */
1623  struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1624  unsigned int dbg; /* FX debugger register */
1625  unsigned char name[128];
1626  int gpr_size; /* size of allocated GPR controls */
1627  int gpr_count; /* count of used kcontrols */
1628  struct list_head gpr_ctl; /* GPR controls */
1629  struct mutex lock;
1630  struct snd_emu10k1_fx8010_pcm pcm[8];
1631  spinlock_t irq_lock;
1632  struct snd_emu10k1_fx8010_irq *irq_handlers;
1633 };
1634 
1635 struct snd_emu10k1_midi {
1636  struct snd_emu10k1 *emu;
1637  struct snd_rawmidi *rmidi;
1638  struct snd_rawmidi_substream *substream_input;
1639  struct snd_rawmidi_substream *substream_output;
1640  unsigned int midi_mode;
1641  spinlock_t input_lock;
1642  spinlock_t output_lock;
1643  spinlock_t open_lock;
1644  int tx_enable, rx_enable;
1645  int port;
1646  int ipr_tx, ipr_rx;
1647  void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1648 };
1649 
1650 enum {
1651  EMU_MODEL_SB,
1652  EMU_MODEL_EMU1010,
1653  EMU_MODEL_EMU1010B,
1654  EMU_MODEL_EMU1616,
1655  EMU_MODEL_EMU0404,
1656 };
1657 
1658 struct snd_emu_chip_details {
1659  u32 vendor;
1660  u32 device;
1661  u32 subsystem;
1662  unsigned char revision;
1663  unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1664  unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1665  unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1666  unsigned char ca0108_chip; /* Audigy 2 Value */
1667  unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
1668  unsigned char ca0151_chip; /* P16V */
1669  unsigned char spk71; /* Has 7.1 speakers */
1670  unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1671  unsigned char spdif_bug; /* Has Spdif phasing bug */
1672  unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1673  unsigned char ecard; /* APS EEPROM */
1674  unsigned char emu_model; /* EMU model type */
1675  unsigned char spi_dac; /* SPI interface for DAC */
1676  unsigned char i2c_adc; /* I2C interface for ADC */
1677  unsigned char adc_1361t; /* Use Philips 1361T ADC */
1678  unsigned char invert_shared_spdif; /* analog/digital switch inverted */
1679  const char *driver;
1680  const char *name;
1681  const char *id; /* for backward compatibility - can be NULL if not needed */
1682 };
1683 
1684 struct snd_emu1010 {
1685  unsigned int output_source[64];
1686  unsigned int input_source[64];
1687  unsigned int adc_pads; /* bit mask */
1688  unsigned int dac_pads; /* bit mask */
1689  unsigned int internal_clock; /* 44100 or 48000 */
1690  unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
1691  unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
1692  struct task_struct *firmware_thread;
1693 };
1694 
1695 struct snd_emu10k1 {
1696  int irq;
1697 
1698  unsigned long port; /* I/O port number */
1699  unsigned int tos_link: 1, /* tos link detected */
1700  rear_ac97: 1, /* rear channels are on AC'97 */
1701  enable_ir: 1;
1702  unsigned int support_tlv :1;
1703  /* Contains profile of card capabilities */
1704  const struct snd_emu_chip_details *card_capabilities;
1705  unsigned int audigy; /* is Audigy? */
1706  unsigned int revision; /* chip revision */
1707  unsigned int serial; /* serial number */
1708  unsigned short model; /* subsystem id */
1709  unsigned int card_type; /* EMU10K1_CARD_* */
1710  unsigned int ecard_ctrl; /* ecard control bits */
1711  unsigned long dma_mask; /* PCI DMA mask */
1712  unsigned int delay_pcm_irq; /* in samples */
1713  int max_cache_pages; /* max memory size / PAGE_SIZE */
1714  struct snd_dma_buffer silent_page; /* silent page */
1715  struct snd_dma_buffer ptb_pages; /* page table pages */
1716  struct snd_dma_device p16v_dma_dev;
1717  struct snd_dma_buffer p16v_buffer;
1718 
1719  struct snd_util_memhdr *memhdr; /* page allocation list */
1720  struct snd_emu10k1_memblk *reserved_page; /* reserved page */
1721 
1722  struct list_head mapped_link_head;
1723  struct list_head mapped_order_link_head;
1724  void **page_ptr_table;
1725  unsigned long *page_addr_table;
1726  spinlock_t memblk_lock;
1727 
1728  unsigned int spdif_bits[3]; /* s/pdif out setup */
1729  unsigned int i2c_capture_source;
1730  u8 i2c_capture_volume[4][2];
1731 
1732  struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
1733  int gpr_base;
1734 
1735  struct snd_ac97 *ac97;
1736 
1737  struct pci_dev *pci;
1738  struct snd_card *card;
1739  struct snd_pcm *pcm;
1740  struct snd_pcm *pcm_mic;
1741  struct snd_pcm *pcm_efx;
1742  struct snd_pcm *pcm_multi;
1743  struct snd_pcm *pcm_p16v;
1744 
1745  spinlock_t synth_lock;
1746  void *synth;
1747  int (*get_synth_voice)(struct snd_emu10k1 *emu);
1748 
1749  spinlock_t reg_lock;
1750  spinlock_t emu_lock;
1751  spinlock_t voice_lock;
1752  spinlock_t spi_lock; /* serialises access to spi port */
1753  spinlock_t i2c_lock; /* serialises access to i2c port */
1754 
1755  struct snd_emu10k1_voice voices[NUM_G];
1756  struct snd_emu10k1_voice p16v_voices[4];
1757  struct snd_emu10k1_voice p16v_capture_voice;
1758  int p16v_device_offset;
1759  u32 p16v_capture_source;
1760  u32 p16v_capture_channel;
1761  struct snd_emu1010 emu1010;
1762  struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1763  struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1764  struct snd_kcontrol *ctl_send_routing;
1765  struct snd_kcontrol *ctl_send_volume;
1766  struct snd_kcontrol *ctl_attn;
1767  struct snd_kcontrol *ctl_efx_send_routing;
1768  struct snd_kcontrol *ctl_efx_send_volume;
1769  struct snd_kcontrol *ctl_efx_attn;
1770 
1771  void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1772  void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1773  void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1774  void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1775  void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1776  void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1777 
1778  struct snd_pcm_substream *pcm_capture_substream;
1779  struct snd_pcm_substream *pcm_capture_mic_substream;
1780  struct snd_pcm_substream *pcm_capture_efx_substream;
1781  struct snd_pcm_substream *pcm_playback_efx_substream;
1782 
1783  struct snd_timer *timer;
1784 
1785  struct snd_emu10k1_midi midi;
1786  struct snd_emu10k1_midi midi2; /* for audigy */
1787 
1788  unsigned int efx_voices_mask[2];
1789  unsigned int next_free_voice;
1790 
1791 #ifdef CONFIG_PM_SLEEP
1792  unsigned int *saved_ptr;
1793  unsigned int *saved_gpr;
1794  unsigned int *tram_val_saved;
1795  unsigned int *tram_addr_saved;
1796  unsigned int *saved_icode;
1797  unsigned int *p16v_saved;
1798  unsigned int saved_a_iocfg, saved_hcfg;
1799 #endif
1800 
1801 };
1802 
1803 int snd_emu10k1_create(struct snd_card *card,
1804  struct pci_dev *pci,
1805  unsigned short extin_mask,
1806  unsigned short extout_mask,
1807  long max_cache_bytes,
1808  int enable_ir,
1809  uint subsystem,
1810  struct snd_emu10k1 ** remu);
1811 
1812 int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1813 int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1814 int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1815 int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1816 int snd_p16v_free(struct snd_emu10k1 * emu);
1817 int snd_p16v_mixer(struct snd_emu10k1 * emu);
1818 int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1819 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1820 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1821 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1822 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);
1823 
1824 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1825 
1826 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1827 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1828 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1829 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1830 int snd_emu10k1_done(struct snd_emu10k1 * emu);
1831 
1832 /* I/O functions */
1833 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1834 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1835 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1836 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1837 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1838 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1839 int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value);
1840 int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value);
1841 int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src);
1842 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1843 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1844 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1845 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1846 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1847 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1848 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1849 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1850 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1851 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1852 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1853 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1854 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1855 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1856 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1857 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1858 
1859 #ifdef CONFIG_PM_SLEEP
1860 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1861 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1862 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1863 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1864 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1865 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1866 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1867 int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1868 void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1869 void snd_p16v_suspend(struct snd_emu10k1 *emu);
1870 void snd_p16v_resume(struct snd_emu10k1 *emu);
1871 #endif
1872 
1873 /* memory allocation */
1874 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1875 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1876 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1877 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1878 int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1879 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1880 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1881 
1882 /* voice allocation */
1883 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1884 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1885 
1886 /* MIDI uart */
1887 int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1888 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1889 
1890 /* proc interface */
1891 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1892 
1893 /* fx8010 irq handler */
1894 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1895  snd_fx8010_irq_handler_t *handler,
1896  unsigned char gpr_running,
1897  void *private_data,
1898  struct snd_emu10k1_fx8010_irq **r_irq);
1899 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1900  struct snd_emu10k1_fx8010_irq *irq);
1901 
1902 #endif /* __KERNEL__ */
1903 
1904 /*
1905  * ---- FX8010 ----
1906  */
1907 
1908 #define EMU10K1_CARD_CREATIVE 0x00000000
1909 #define EMU10K1_CARD_EMUAPS 0x00000001
1910 
1911 #define EMU10K1_FX8010_PCM_COUNT 8
1912 
1913 /* instruction set */
1914 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
1915 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1916 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
1917 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1918 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
1919 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1920 #define iACC3 0x06 /* R = A + X + Y ; saturation */
1921 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
1922 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
1923 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
1924 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
1925 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
1926 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
1927 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
1928 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1929 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
1930 
1931 /* GPRs */
1932 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1933 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1934 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
1935 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
1936  /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
1937 
1938 #define C_00000000 0x40
1939 #define C_00000001 0x41
1940 #define C_00000002 0x42
1941 #define C_00000003 0x43
1942 #define C_00000004 0x44
1943 #define C_00000008 0x45
1944 #define C_00000010 0x46
1945 #define C_00000020 0x47
1946 #define C_00000100 0x48
1947 #define C_00010000 0x49
1948 #define C_00080000 0x4a
1949 #define C_10000000 0x4b
1950 #define C_20000000 0x4c
1951 #define C_40000000 0x4d
1952 #define C_80000000 0x4e
1953 #define C_7fffffff 0x4f
1954 #define C_ffffffff 0x50
1955 #define C_fffffffe 0x51
1956 #define C_c0000000 0x52
1957 #define C_4f1bbcdc 0x53
1958 #define C_5a7ef9db 0x54
1959 #define C_00100000 0x55 /* ?? */
1960 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
1961 #define GPR_COND 0x57 /* CCR, condition register */
1962 #define GPR_NOISE0 0x58 /* noise source */
1963 #define GPR_NOISE1 0x59 /* noise source */
1964 #define GPR_IRQ 0x5a /* IRQ register */
1965 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
1966 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1967 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1968 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1969 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1970 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1971 
1972 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1973 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1974 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1975 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1976 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1977 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1978 
1979 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
1980 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
1981 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
1982 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
1983 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
1984 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
1985 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
1986 #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
1987 #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
1988 #define A_GPR(x) (A_FXGPREGBASE + (x))
1989 
1990 /* cc_reg constants */
1991 #define CC_REG_NORMALIZED C_00000001
1992 #define CC_REG_BORROW C_00000002
1993 #define CC_REG_MINUS C_00000004
1994 #define CC_REG_ZERO C_00000008
1995 #define CC_REG_SATURATE C_00000010
1996 #define CC_REG_NONZERO C_00000100
1997 
1998 /* FX buses */
1999 #define FXBUS_PCM_LEFT 0x00
2000 #define FXBUS_PCM_RIGHT 0x01
2001 #define FXBUS_PCM_LEFT_REAR 0x02
2002 #define FXBUS_PCM_RIGHT_REAR 0x03
2003 #define FXBUS_MIDI_LEFT 0x04
2004 #define FXBUS_MIDI_RIGHT 0x05
2005 #define FXBUS_PCM_CENTER 0x06
2006 #define FXBUS_PCM_LFE 0x07
2007 #define FXBUS_PCM_LEFT_FRONT 0x08
2008 #define FXBUS_PCM_RIGHT_FRONT 0x09
2009 #define FXBUS_MIDI_REVERB 0x0c
2010 #define FXBUS_MIDI_CHORUS 0x0d
2011 #define FXBUS_PCM_LEFT_SIDE 0x0e
2012 #define FXBUS_PCM_RIGHT_SIDE 0x0f
2013 #define FXBUS_PT_LEFT 0x14
2014 #define FXBUS_PT_RIGHT 0x15
2015 
2016 /* Inputs */
2017 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
2018 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
2019 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
2020 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
2021 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
2022 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
2023 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
2024 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
2025 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
2026 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
2027 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
2028 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
2029 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
2030 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
2031 
2032 /* Outputs */
2033 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
2034 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
2035 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
2036 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
2037 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
2038 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
2039 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
2040 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
2041 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
2042 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
2043 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
2044 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
2045 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
2046 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
2047 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
2048 #define EXTOUT_ACENTER 0x11 /* Analog Center */
2049 #define EXTOUT_ALFE 0x12 /* Analog LFE */
2050 
2051 /* Audigy Inputs */
2052 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
2053 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
2054 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
2055 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
2056 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
2057 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
2058 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
2059 #define A_EXTIN_LINE2_R 0x09 /* right */
2060 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
2061 #define A_EXTIN_ADC_R 0x0b /* right */
2062 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
2063 #define A_EXTIN_AUX2_R 0x0d /* - right */
2064 
2065 /* Audigiy Outputs */
2066 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
2067 #define A_EXTOUT_FRONT_R 0x01 /* right */
2068 #define A_EXTOUT_CENTER 0x02 /* digital front center */
2069 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
2070 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
2071 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
2072 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
2073 #define A_EXTOUT_REAR_R 0x07 /* right */
2074 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
2075 #define A_EXTOUT_AFRONT_R 0x09 /* right */
2076 #define A_EXTOUT_ACENTER 0x0a /* analog center */
2077 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
2078 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
2079 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
2080 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
2081 #define A_EXTOUT_AREAR_R 0x0f /* right */
2082 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
2083 #define A_EXTOUT_AC97_R 0x11 /* right */
2084 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
2085 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
2086 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
2087 
2088 /* Audigy constants */
2089 #define A_C_00000000 0xc0
2090 #define A_C_00000001 0xc1
2091 #define A_C_00000002 0xc2
2092 #define A_C_00000003 0xc3
2093 #define A_C_00000004 0xc4
2094 #define A_C_00000008 0xc5
2095 #define A_C_00000010 0xc6
2096 #define A_C_00000020 0xc7
2097 #define A_C_00000100 0xc8
2098 #define A_C_00010000 0xc9
2099 #define A_C_00000800 0xca
2100 #define A_C_10000000 0xcb
2101 #define A_C_20000000 0xcc
2102 #define A_C_40000000 0xcd
2103 #define A_C_80000000 0xce
2104 #define A_C_7fffffff 0xcf
2105 #define A_C_ffffffff 0xd0
2106 #define A_C_fffffffe 0xd1
2107 #define A_C_c0000000 0xd2
2108 #define A_C_4f1bbcdc 0xd3
2109 #define A_C_5a7ef9db 0xd4
2110 #define A_C_00100000 0xd5
2111 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
2112 #define A_GPR_COND 0xd7 /* CCR, condition register */
2113 #define A_GPR_NOISE0 0xd8 /* noise source */
2114 #define A_GPR_NOISE1 0xd9 /* noise source */
2115 #define A_GPR_IRQ 0xda /* IRQ register */
2116 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
2117 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
2118 
2119 /* definitions for debug register */
2120 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
2121 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
2122 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
2123 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
2124 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
2125 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
2126 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
2127 
2128 /* tank memory address line */
2129 #ifndef __KERNEL__
2130 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
2131 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
2132 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
2133 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
2134 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
2135 #endif
2136 
2137 struct snd_emu10k1_fx8010_info {
2138  unsigned int internal_tram_size; /* in samples */
2139  unsigned int external_tram_size; /* in samples */
2140  char fxbus_names[16][32]; /* names of FXBUSes */
2141  char extin_names[16][32]; /* names of external inputs */
2142  char extout_names[32][32]; /* names of external outputs */
2143  unsigned int gpr_controls; /* count of GPR controls */
2144 };
2145 
2146 #define EMU10K1_GPR_TRANSLATION_NONE 0
2147 #define EMU10K1_GPR_TRANSLATION_TABLE100 1
2148 #define EMU10K1_GPR_TRANSLATION_BASS 2
2149 #define EMU10K1_GPR_TRANSLATION_TREBLE 3
2150 #define EMU10K1_GPR_TRANSLATION_ONOFF 4
2151 
2152 struct snd_emu10k1_fx8010_control_gpr {
2153  struct snd_ctl_elem_id id; /* full control ID definition */
2154  unsigned int vcount; /* visible count */
2155  unsigned int count; /* count of GPR (1..16) */
2156  unsigned short gpr[32]; /* GPR number(s) */
2157  unsigned int value[32]; /* initial values */
2158  unsigned int min; /* minimum range */
2159  unsigned int max; /* maximum range */
2160  unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
2161  const unsigned int *tlv;
2162 };
2163 
2164 /* old ABI without TLV support */
2165 struct snd_emu10k1_fx8010_control_old_gpr {
2166  struct snd_ctl_elem_id id;
2167  unsigned int vcount;
2168  unsigned int count;
2169  unsigned short gpr[32];
2170  unsigned int value[32];
2171  unsigned int min;
2172  unsigned int max;
2173  unsigned int translation;
2174 };
2175 
2176 struct snd_emu10k1_fx8010_code {
2177  char name[128];
2178 
2179  DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
2180  __u32 __user *gpr_map; /* initializers */
2181 
2182  unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
2183  struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */
2184 
2185  unsigned int gpr_del_control_count; /* count of GPR controls to remove */
2186  struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */
2187 
2188  unsigned int gpr_list_control_count; /* count of GPR controls to list */
2189  unsigned int gpr_list_control_total; /* total count of GPR controls */
2190  struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */
2191 
2192  DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
2193  __u32 __user *tram_data_map; /* data initializers */
2194  __u32 __user *tram_addr_map; /* map initializers */
2195 
2196  DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
2197  __u32 __user *code; /* one instruction - 64 bits */
2198 };
2199 
2200 struct snd_emu10k1_fx8010_tram {
2201  unsigned int address; /* 31.bit == 1 -> external TRAM */
2202  unsigned int size; /* size in samples (4 bytes) */
2203  unsigned int *samples; /* pointer to samples (20-bit) */
2204  /* NULL->clear memory */
2205 };
2206 
2207 struct snd_emu10k1_fx8010_pcm_rec {
2208  unsigned int substream; /* substream number */
2209  unsigned int res1; /* reserved */
2210  unsigned int channels; /* 16-bit channels count, zero = remove this substream */
2211  unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
2212  unsigned int buffer_size; /* count of buffered samples */
2213  unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
2214  unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
2215  unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
2216  unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
2217  unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
2218  unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
2219  unsigned char pad; /* reserved */
2220  unsigned char etram[32]; /* external TRAM address & data (one per channel) */
2221  unsigned int res2; /* reserved */
2222 };
2223 
2224 #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
2225 
2226 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
2227 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
2228 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
2229 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
2230 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
2231 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
2232 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
2233 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
2234 #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
2235 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
2236 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
2237 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
2238 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
2239 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
2240 
2241 /* typedefs for compatibility to user-space */
2242 typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
2243 typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
2244 typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
2245 typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
2246 typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
2247 
2248 #endif /* __SOUND_EMU10K1_H */
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