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| #define | ENE_STATUS 0 /* hardware status - unused */ |
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| #define | ENE_ADDR_HI 1 /* hi byte of register address */ |
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| #define | ENE_ADDR_LO 2 /* low byte of register address */ |
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| #define | ENE_IO 3 /* read/write window */ |
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| #define | ENE_IO_SIZE 4 |
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| #define | ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */ |
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| #define | ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */ |
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| #define | ENE_FW_PACKET_SIZE 4 |
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| #define | ENE_FW1 0xF8F8 /* flagr */ |
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| #define | ENE_FW1_ENABLE 0x01 /* enable fw processing */ |
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| #define | ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */ |
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| #define | ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/ |
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| #define | ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/ |
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| #define | ENE_FW1_LED_ON 0x10 /* turn on a led */ |
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| #define | ENE_FW1_WPATTERN 0x20 /* enable wake pattern */ |
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| #define | ENE_FW1_WAKE 0x40 /* enable wake from S3 */ |
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| #define | ENE_FW1_IRQ 0x80 /* enable interrupt */ |
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| #define | ENE_FW2 0xF8F9 /* flagw */ |
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| #define | ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */ |
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| #define | ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/ |
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| #define | ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */ |
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| #define | ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */ |
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| #define | ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */ |
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| #define | ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/ |
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| #define | ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */ |
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| #define | ENE_FW_RX_POINTER 0xF8FA |
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| #define | ENE_FW_SMPL_BUF_FAN 0xF8FB |
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| #define | ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */ |
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| #define | ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */ |
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| #define | ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */ |
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| #define | ENE_GPIOFS1 0xFC01 |
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| #define | ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */ |
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| #define | ENE_GPIOFS8 0xFC08 |
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| #define | ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */ |
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| #define | ENEB_IRQ 0xFD09 /* IRQ number */ |
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| #define | ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */ |
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| #define | ENEB_IRQ_STATUS 0xFD80 /* irq status */ |
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| #define | ENEB_IRQ_STATUS_IR 0x20 /* IR irq */ |
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| #define | ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */ |
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| #define | ENE_FAN_AS_IN1_EN 0xCD |
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| #define | ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */ |
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| #define | ENE_FAN_AS_IN2_EN 0x03 |
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| #define | ENE_IRQ 0xFE9B /* new irq settings register */ |
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| #define | ENE_IRQ_MASK 0x0F /* irq number mask */ |
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| #define | ENE_IRQ_UNK_EN 0x10 /* always enabled */ |
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| #define | ENE_IRQ_STATUS 0x20 /* irq status and ACK */ |
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| #define | ENE_CIRCFG 0xFEC0 |
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| #define | ENE_CIRCFG_RX_EN 0x01 /* RX enable */ |
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| #define | ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */ |
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| #define | ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */ |
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| #define | ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */ |
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| #define | ENE_CIRCFG_TX_EN 0x10 /* TX enable */ |
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| #define | ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */ |
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| #define | ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */ |
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| #define | ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */ |
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| #define | ENE_CIRCFG2 0xFEC1 |
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| #define | ENE_CIRCFG2_RLC 0x00 |
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| #define | ENE_CIRCFG2_RC5 0x01 |
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| #define | ENE_CIRCFG2_RC6 0x02 |
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| #define | ENE_CIRCFG2_NEC 0x03 |
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| #define | ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */ |
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| #define | ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */ |
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| #define | ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */ |
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| #define | ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */ |
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| #define | ENE_CIRPF 0xFEC2 |
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| #define | ENE_CIRHIGH 0xFEC3 |
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| #define | ENE_CIRBIT 0xFEC4 |
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| #define | ENE_CIRSTART 0xFEC5 |
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| #define | ENE_CIRSTART2 0xFEC6 |
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| #define | ENE_CIRDAT_IN 0xFEC7 |
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| #define | ENE_CIRRLC_CFG 0xFEC8 |
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| #define | ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */ |
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| #define | ENE_DEFAULT_SAMPLE_PERIOD 50 |
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| #define | ENE_CIRRLC_OUT0 0xFEC9 |
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| #define | ENE_CIRRLC_OUT1 0xFECA |
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| #define | ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */ |
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| #define | ENE_CIRRLC_OUT_MASK 0x7F |
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| #define | ENE_CIRCAR_PULS 0xFECB |
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| #define | ENE_CIRCAR_PRD 0xFECC |
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| #define | ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */ |
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| #define | ENE_CIRCAR_HPRD 0xFECD |
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| #define | ENE_CIRMOD_PRD 0xFECE |
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| #define | ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/ |
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| #define | ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */ |
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| #define | ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */ |
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| #define | ENE_CIRMOD_HPRD 0xFECF |
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| #define | ENE_ECHV 0xFF00 /* hardware revision */ |
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| #define | ENE_PLLFRH 0xFF16 |
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| #define | ENE_PLLFRL 0xFF17 |
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| #define | ENE_DEFAULT_PLL_FREQ 1000 |
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| #define | ENE_ECSTS 0xFF1D |
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| #define | ENE_ECSTS_RSRVD 0x04 |
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| #define | ENE_ECVER_MAJOR 0xFF1E /* chip version */ |
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| #define | ENE_ECVER_MINOR 0xFF1F |
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| #define | ENE_HW_VER_OLD 0xFD00 |
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| #define | ENE_DRIVER_NAME "ene_ir" |
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| #define | ENE_IRQ_RX 1 |
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| #define | ENE_IRQ_TX 2 |
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| #define | ENE_HW_B 1 /* 3926B */ |
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| #define | ENE_HW_C 2 /* 3926C */ |
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| #define | ENE_HW_D 3 /* 3926D or later */ |
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| #define | __dbg(level, format,...) |
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| #define | dbg(format,...) __dbg(1, format, ## __VA_ARGS__) |
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| #define | dbg_verbose(format,...) __dbg(2, format, ## __VA_ARGS__) |
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| #define | dbg_regs(format,...) __dbg(3, format, ## __VA_ARGS__) |
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1.8.2