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| #define | R592_TPC_EXEC 0x00 |
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| #define | R592_TPC_EXEC_LEN_SHIFT 16 /* Bits 16..25 are TPC len */ |
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| #define | R592_TPC_EXEC_BIG_FIFO (1 << 26) /* If bit 26 is set, large fifo is used (reg 48) */ |
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| #define | R592_TPC_EXEC_TPC_SHIFT 28 /* Bits 28..31 are the TPC number */ |
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| #define | R592_SFIFO 0x08 |
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| #define | R592_STATUS 0x10 |
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| #define | R592_STATUS_P_CMDNACK (1 << 16) /* INT reg: NACK (parallel mode) */ |
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| #define | R592_STATUS_P_BREQ (1 << 17) /* INT reg: card ready (parallel mode)*/ |
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| #define | R592_STATUS_P_INTERR (1 << 18) /* INT reg: int error (parallel mode)*/ |
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| #define | R592_STATUS_P_CED (1 << 19) /* INT reg: command done (parallel mode) */ |
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| #define | R592_STATUS_SFIFO_FULL (1 << 20) /* Small Fifo almost full (last chunk is written) */ |
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| #define | R592_STATUS_SFIFO_EMPTY (1 << 21) /* Small Fifo empty */ |
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| #define | R592_STATUS_SEND_ERR (1 << 24) /* Send failed */ |
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| #define | R592_STATUS_RECV_ERR (1 << 25) /* Receive failed */ |
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| #define | R592_STATUS_RDY (1 << 28) /* RDY signal received */ |
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| #define | R592_STATUS_CED (1 << 29) /* INT: Command done (serial mode)*/ |
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| #define | R592_STATUS_SFIFO_INPUT (1 << 30) /* Small fifo received data*/ |
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| #define | R592_SFIFO_SIZE 32 /* total size of small fifo is 32 bytes */ |
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| #define | R592_SFIFO_PACKET 8 /* packet size of small fifo */ |
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| #define | R592_IO 0x18 |
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| #define | R592_IO_16 (1 << 16) /* Set by default, can be cleared */ |
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| #define | R592_IO_18 (1 << 18) /* Set by default, can be cleared */ |
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| #define | R592_IO_SERIAL1 (1 << 20) /* Set by default, can be cleared, (cleared on parallel) */ |
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| #define | R592_IO_22 (1 << 22) /* Set by default, can be cleared */ |
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| #define | R592_IO_DIRECTION (1 << 24) /* TPC direction (1 write 0 read) */ |
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| #define | R592_IO_26 (1 << 26) /* Set by default, can be cleared */ |
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| #define | R592_IO_SERIAL2 (1 << 30) /* Set by default, can be cleared (cleared on parallel), serial doesn't work if unset */ |
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| #define | R592_IO_RESET (1 << 31) /* Reset, sets defaults*/ |
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| #define | R592_POWER 0x20 /* bits 0-7 writeable */ |
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| #define | R592_POWER_0 (1 << 0) /* set on start, cleared on stop - must be set*/ |
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| #define | R592_POWER_1 (1 << 1) /* set on start, cleared on stop - must be set*/ |
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| #define | R592_POWER_3 (1 << 3) /* must be clear */ |
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| #define | R592_POWER_20 (1 << 5) /* set before switch to parallel */ |
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| #define | R592_IO_MODE 0x24 |
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| #define | R592_IO_MODE_SERIAL 1 |
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| #define | R592_IO_MODE_PARALLEL 3 |
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| #define | R592_REG_MSC 0x28 |
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| #define | R592_REG_MSC_PRSNT (1 << 1) /* card present (only status)*/ |
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| #define | R592_REG_MSC_IRQ_INSERT (1 << 8) /* detect insert / card insered */ |
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| #define | R592_REG_MSC_IRQ_REMOVE (1 << 9) /* detect removal / card removed */ |
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| #define | R592_REG_MSC_FIFO_EMPTY (1 << 10) /* fifo is empty */ |
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| #define | R592_REG_MSC_FIFO_DMA_DONE (1 << 11) /* dma enable / dma done */ |
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| #define | R592_REG_MSC_FIFO_USER_ORN (1 << 12) /* set if software reads empty fifo (if R592_REG_MSC_FIFO_EMPTY is set) */ |
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| #define | R592_REG_MSC_FIFO_MISMATH (1 << 13) /* set if amount of data in fifo doesn't match amount in TPC */ |
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| #define | R592_REG_MSC_FIFO_DMA_ERR (1 << 14) /* IO failure */ |
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| #define | R592_REG_MSC_LED (1 << 15) /* clear to turn led off (only status)*/ |
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| #define | DMA_IRQ_ACK_MASK (R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR) |
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| #define | DMA_IRQ_EN_MASK (DMA_IRQ_ACK_MASK << 16) |
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| #define | IRQ_ALL_ACK_MASK 0x00007F00 |
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| #define | IRQ_ALL_EN_MASK (IRQ_ALL_ACK_MASK << 16) |
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| #define | R592_FIFO_DMA 0x2C |
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| #define | R592_FIFO_PIO 0x30 |
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| #define | R592_LFIFO_SIZE 512 /* large fifo size */ |
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| #define | R592_FIFO_DMA_SETTINGS 0x34 |
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| #define | R592_FIFO_DMA_SETTINGS_EN (1 << 0) /* DMA enabled */ |
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| #define | R592_FIFO_DMA_SETTINGS_DIR (1 << 1) /* Dma direction (1 read, 0 write) */ |
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| #define | R592_FIFO_DMA_SETTINGS_CAP (1 << 24) /* Dma is aviable */ |
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| #define | R592_REG38 0x38 |
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| #define | R592_REG38_CHANGE (1 << 16) /* Start bit */ |
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| #define | R592_REG38_DONE (1 << 20) /* HW set this after the delay */ |
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| #define | R592_REG38_SHIFT 17 |
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| #define | R592_REG_3C 0x3C |
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| #define | DRV_NAME "r592" |
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| #define | message(format,...) printk(KERN_INFO DRV_NAME ": " format "\n", ## __VA_ARGS__) |
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| #define | __dbg(level, format,...) |
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| #define | dbg(format,...) __dbg(1, format, ## __VA_ARGS__) |
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| #define | dbg_verbose(format,...) __dbg(2, format, ## __VA_ARGS__) |
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| #define | dbg_reg(format,...) __dbg(3, format, ## __VA_ARGS__) |
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1.8.2