62 chan->
base.vblank.ctxdma = gpuobj->
node->offset >> 4;
74 chan->
base.vblank.offset = *(
u32 *)args;
83 chan->
base.vblank.value = *(
u32 *)args;
102 list_add(&chan->
base.vblank.head, &disp->
vblank.list);
103 chan->
base.vblank.crtc = crtc;
104 spin_unlock_irqrestore(&disp->
vblank.lock, flags);
110 void *args,
u32 size)
114 return chan->
base.flip(chan->
base.flip_data);
119 nv50_software_omthds[] = {
120 { 0x018c, nv50_software_mthd_dma_vblsem },
121 { 0x0400, nv50_software_mthd_vblsem_offset },
122 { 0x0404, nv50_software_mthd_vblsem_value },
123 { 0x0408, nv50_software_mthd_vblsem_release },
124 { 0x0500, nv50_software_mthd_flip },
129 nv50_software_sclass[] = {
148 *pobject = nv_object(chan);
152 chan->
base.vblank.channel = nv_gpuobj(parent->
parent)->addr >> 12;
157 nv50_software_cclass = {
160 .ctor = nv50_software_context_ctor,
180 *pobject = nv_object(priv);
184 nv_engine(priv)->cclass = &nv50_software_cclass;
185 nv_engine(priv)->sclass = nv50_software_sclass;
194 .ctor = nv50_software_ctor,